JPH0568866B2 - - Google Patents
Info
- Publication number
- JPH0568866B2 JPH0568866B2 JP61315203A JP31520386A JPH0568866B2 JP H0568866 B2 JPH0568866 B2 JP H0568866B2 JP 61315203 A JP61315203 A JP 61315203A JP 31520386 A JP31520386 A JP 31520386A JP H0568866 B2 JPH0568866 B2 JP H0568866B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- type region
- substrate
- photoelectric conversion
- intrinsic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 45
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 17
- 239000013078 crystal Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Description
【発明の詳細な説明】
『産業上の利用分野』
本発明は基板上に設けられた半導体の一主表面
にのみ＋電極となるＰ型の領域と−電極となるＮ
型の領域とを選択的に設け、作製の容易かつ構造
の簡単な光電変換装置に関する。Detailed Description of the Invention "Industrial Application Field" The present invention provides a P-type region that serves as a + electrode and an N-type region that serves as a - electrode only on one main surface of a semiconductor provided on a substrate.
The present invention relates to a photoelectric conversion device that is easy to manufacture and has a simple structure by selectively providing mold regions.
『従来の技術』
従来、光電変換装置に関してはPNまたはPIN
接合を単結晶の珪素基板に形成した太陽電池、ま
たはフオトセルが知られている。しかしこのPN
またはPIN接合は単結晶の珪素基板の表面と裏面
にその＋電極または−電極を有し、その接合面は
基板の主面に実質的に平行に設け、この接合面に
光が多量に照射されるように工夫がなされていた
にすぎなかつた。"Conventional technology" Conventionally, photoelectric conversion devices used PN or PIN.
2. Description of the Related Art Solar cells or photocells in which a junction is formed on a single crystal silicon substrate are known. But this PN
Alternatively, a PIN junction has positive or negative electrodes on the front and back surfaces of a single-crystal silicon substrate, and the bonding surface is provided substantially parallel to the main surface of the substrate, and a large amount of light is irradiated onto this bonding surface. It was simply a matter of devising a way to make it work.
『発明が解決しようとする問題点』
これら従来の光電変換装置は半導体基板の主面
に平行に接合面を設けていた為、電界のかかる方
向と光照射面が垂直となつてしまい光照射強度が
電界のかかる方向で一様ではなく、効率よく電
子・ホールを発生させることはできなかつた。``Problems to be solved by the invention'' These conventional photoelectric conversion devices had a bonding surface parallel to the main surface of the semiconductor substrate, so the direction in which the electric field was applied was perpendicular to the light irradiation surface, resulting in light irradiation intensity. The electric field was not uniform in the direction in which it was applied, and it was not possible to efficiently generate electrons and holes.
また、単結晶基板は極めてへきかいしやすく高
価であり、加工がしにくく、光電変換装置を集積
化して複数個を直列または並列に配列させること
ができない等多くの欠点を有していた。 In addition, single crystal substrates have many drawbacks, such as being extremely easily cracked and expensive, difficult to process, and unable to integrate photoelectric conversion devices and arrange a plurality of them in series or parallel.
本発明は非単結晶半導体中で電子・ホールを効
率よく発生させること、また更に半導体を非単結
晶として加工しやすくさせることを目的としてい
る。 The present invention aims to efficiently generate electrons and holes in a non-single-crystal semiconductor, and also to make it easier to process the semiconductor into a non-single-crystal semiconductor.
『問題点を解決する為の手段』
本発明は、透光性基板の光入射面に対して反対
面上に設けられた非単結晶半導体の少なくとも上
部にＰ型の領域とＮ型の領域とを選択的に光照射
面に対して平行に配したことを特徴とする光電変
換装置により、上記の目的を達成したものであ
る。"Means for Solving the Problems" The present invention provides a P-type region and an N-type region at least in the upper part of a non-single crystal semiconductor provided on a surface opposite to the light incident surface of a transparent substrate. The above object has been achieved by a photoelectric conversion device characterized by selectively disposing parallel to the light irradiation surface.
『作用』
上記のような構造、即ち同一光照射面より、Ｐ
型の領域、Ｎ型の領域をその半導体の深さ方向に
形成したことにより、Ｐ型の領域とＮ型の領域間
での電界方向での光強度が一定となる。またＰ型
の領域あるいはＮ型の領域と真性半導体層との接
合面を極めて狭くし、接合界面でのキヤリアの再
結合の割合を減らすことにより光電変換効率の向
上を計ろうとしたものである。``Action'' With the above structure, that is, from the same light irradiation surface, P
By forming the type region and the N type region in the depth direction of the semiconductor, the light intensity in the electric field direction between the P type region and the N type region becomes constant. Another attempt was made to improve the photoelectric conversion efficiency by making the junction surface between the P-type region or the N-type region and the intrinsic semiconductor layer extremely narrow and reducing the rate of carrier recombination at the junction interface.
以下に実施例に従い本発明を説明する。 The present invention will be described below with reference to Examples.
『実施例』
第１図は本発明の製作工程を示す縦断面図であ
る。第１図Ａにおいて、基板１は導電性または絶
縁性基板である。この基板は安価であり以降の被
膜形成工程に対し機械的強度並びに対熱性を有し
ていることがその要件である。この為本実施例に
おいては、ガラス基板を主として用いた。この基
板１の上面に室温〜500℃の温度にてプラズマ
CVD法により、SiH4：20SCCM、圧力：0.01〜
0.3TORRで約60分間Depoを行い、エネルギーバ
ンド巾約2.3eV、膜厚2500Åの第１の半導体４３
を形成した。この際原料ガスに必要に応じてＣ、
Ｏ、Ｎを５〜50atm％添加してエネルギーバンド
巾を変化させた。さらにこの第１の半導体４３上
に第２の半導体２を形成した。この際原料ガスに
必要に応じてＣ、Ｏ、Ｎを含むガスを添加してエ
ネルギーバンド巾を変化させ、エネルギーバンド
巾1.6ev、膜厚1μｍの第２の半導体を形成した。``Example'' FIG. 1 is a longitudinal sectional view showing the manufacturing process of the present invention. In FIG. 1A, substrate 1 is a conductive or insulating substrate. The requirements for this substrate are that it is inexpensive and has mechanical strength and heat resistance for the subsequent film forming process. Therefore, in this example, a glass substrate was mainly used. Plasma is applied to the upper surface of this substrate 1 at a temperature of room temperature to 500°C.
By CVD method, SiH4: 20SCCM, pressure: 0.01~
Deposition was performed for about 60 minutes at 0.3 TORR, and the first semiconductor 43 with an energy band width of about 2.3 eV and a film thickness of 2500 Å was deposited.
was formed. At this time, if necessary, add C to the raw material gas.
The energy band width was changed by adding 5 to 50 atm% of O and N. Furthermore, the second semiconductor 2 was formed on this first semiconductor 43. At this time, a gas containing C, O, and N was added to the raw material gas as necessary to change the energy band width, and a second semiconductor having an energy band width of 1.6 ev and a film thickness of 1 μm was formed.
さらに第２の半導体２上に、第３の半導体３を
第１の半導体４３と同じ作製条件で形成させた。 Furthermore, a third semiconductor 3 was formed on the second semiconductor 2 under the same manufacturing conditions as the first semiconductor 43.
これら第１の半導体、第２の半導体および第３
の半導体は、Ｐ型、Ｎ型のド−パントを添加しな
い限り実質的に真性の半導体であつた。 These first semiconductor, second semiconductor and third semiconductor
The semiconductor was essentially an intrinsic semiconductor unless P-type or N-type dopants were added.
次に、この半導体を光電変換装置に必要な部分
のみを残すようにエツチングを行つた後、半導体
層の上表面および側周辺に第３の半導体に対しマ
スク作用を有する絶縁膜として例えば酸化珪素ま
たは窒化珪素を500〜2000Åの厚さにプラズマ
CVD法により形成した。本実施例ではSiH4、
NH3を用いて窒化珪素被膜を形成した。 Next, after etching this semiconductor so as to leave only the portion necessary for the photoelectric conversion device, an insulating film having a masking effect on the third semiconductor is formed on the upper surface and around the sides of the semiconductor layer using, for example, silicon oxide or Plasma silicon nitride to a thickness of 500-2000Å
Formed by CVD method. In this example, SiH 4 ,
A silicon nitride film was formed using NH3 .
さらに第１図Ｂのように＋電極および−電極に
なる部分に対し開口７，８をフオトエツチング法
により絶縁膜４を選択的に除去して形成した。こ
の開口の巾は２〜20μｍ特に５〜7μｍと巾を狭く
して櫛型とし、開口７，８間の距離１１は第２の
半導体の膜厚とほぼ同一としたが、この距離は半
導体中の再励起によつて発生した電子・ホールの
拡散距離より短くその1/4〜1/2とするのが好まし
かつた。 Furthermore, as shown in FIG. 1B, openings 7 and 8 were formed by selectively removing the insulating film 4 in the portions that would become the + and - electrodes by photo-etching. The width of this opening was narrowed to 2 to 20 μm, especially 5 to 7 μm, and was shaped like a comb, and the distance 11 between the openings 7 and 8 was approximately the same as the film thickness of the second semiconductor. It is preferable that the diffusion length be 1/4 to 1/2 shorter than the diffusion distance of electrons and holes generated by re-excitation of the .
次に開口部７，８より、それぞれボロンＢ、フ
オスフインＰを拡散法、イオン注入法等によりド
ーパントを1018cm-3〜3mol％の濃度にドープし第
１図Ｃのように、Ｐ型の領域９、Ｎ型領域１０を
第３の半導体層中に形成した。 Next, dopants such as boron B and phosphine P are doped through the openings 7 and 8 to a concentration of 10 18 cm -3 to 3 mol % by diffusion, ion implantation, etc., as shown in Figure 1C. Region 9 and N-type region 10 were formed in the third semiconductor layer.
次ぎに第１図ＤのようにＰ型の領域９Ｎ型の領
域１０の各々の上面にアルミニウムを1μｍ蒸着
し、オーミツクコンタクト電極１４および、それ
より延在して基板上に外部接続端子１６，１７を
形成した。 Next, as shown in FIG. 1D, aluminum is vapor-deposited to a thickness of 1 μm on the upper surface of each of the P-type region 9 and the N-type region 10 to form an ohmic contact electrode 14 and an external connection terminal 16 extending therefrom on the substrate. 17 was formed.
第１図ＤのＡ−A′の破線に従つてそのエネル
ギーバンドダイヤグラムを考察するとその一例と
して第２図Ａを得た。＋電極１４、Ｐ型の領域９、
実質的に真性の第３の半導体２Ｎ型の領域１０、
−電極１５にそれぞれ対応して１４，９，２，１
０，１５が記されている。 When the energy band diagram is considered along the dashed line A-A' in FIG. 1D, FIG. 2A is obtained as an example thereof. + electrode 14, P-type region 9,
a substantially intrinsic third semiconductor 2N type region 10;
- 14, 9, 2, 1 corresponding to electrode 15, respectively;
0,15 are written.
この第２図Ａより明らかな如く、ホールは１４
へ、また電子は１５へと拡散して行き、もしホー
ルの一部が１０へと拡散した場合、撥ね返されて
しまい−電極近傍での再結合を禁止している。同
様なことが＋電極でも起こつている。 As is clear from this Figure 2 A, there are 14 holes.
The electrons also diffuse to 15, and if some of the holes diffuse to 10, they are repelled - prohibiting recombination near the electrode. A similar thing happens with the + electrode.
本発明において半導体材料としては、珪素を含
む半導体のみではなく−族、−族の化合
物半導体でもよく、その構造も非単結晶ならば、
いわゆるアモルフアス、セミアモルフアス、多結
晶でもよい、またその作製方法も公知の化学気相
反応法でよい。 In the present invention, the semiconductor material may be not only a silicon-containing semiconductor but also a - group or - group compound semiconductor, and if its structure is also non-single crystal,
It may be so-called amorphous, semi-amorphous, or polycrystalline, and its production method may be a known chemical vapor phase reaction method.
また本実施例においては、第３の半導体まで３
層積層させたが半導体層は１層あるいは２層とし
て実施しても良い。 In addition, in this embodiment, up to the third semiconductor
Although the layers are stacked, the semiconductor layer may be one or two layers.
『発明の効果』
本発明は代表的には第１図Ｄのような構造を持
つ光電変換装置であります。光照射面に対しＰ型
の領域のＮ型の領域間に発生する電界方向が平行
であり、Ｐ型あるいはＮ型の領域と真性半導体層
との接合面が狭いため接合界面でのキヤリアの再
結合を減らすことが可能となるため、高効率の光
電変換装置であつた。``Effects of the Invention'' The present invention is a photoelectric conversion device typically having a structure as shown in Figure 1D. The direction of the electric field generated between the P-type region and the N-type region is parallel to the light irradiation surface, and the junction surface between the P-type or N-type region and the intrinsic semiconductor layer is narrow, so carrier regeneration at the junction interface is prevented. Since it was possible to reduce coupling, it was a highly efficient photoelectric conversion device.
また半導体を非単結晶としたことにより、半導
体を加工しやすくなつた。 Also, by making the semiconductor non-single crystal, it has become easier to process the semiconductor.
その他の特徴としては、外部取り出し電極を基
板上に設けているため一基板上の光電変換装置を
複数個集積化して直、並列接続をすることがで
き、同一基板上に逆流防止ダイオードをも同一半
導体により作製できる。 Other features include the provision of external lead-out electrodes on the substrate, which allows multiple photoelectric conversion devices to be integrated on one substrate and connected in series or parallel, and backflow prevention diodes can also be connected on the same substrate. It can be made from semiconductors.
電極が一表面にのみ形成されている為、半導体
作製の際、その熱的ストレスを考慮する必要はな
い。 Since the electrode is formed only on one surface, there is no need to consider thermal stress during semiconductor manufacturing.
構造が極めて簡単であり、また半導体の上、側
周辺を窒化珪素膜により被覆してあるため外部汚
染に対する信頼性にすぐれている。 The structure is extremely simple, and since the top and sides of the semiconductor are covered with a silicon nitride film, it has excellent reliability against external contamination.
第１図は本発明による構造を有する光電変換装
置の作製工程を示す縦断面図である。第２図は第
１図Ｄのエネルギーバンド図である。
１……基板、２……第１の非単結晶半導体、３
……第２の非単結晶半導体、４……絶縁膜。
FIG. 1 is a longitudinal sectional view showing the manufacturing process of a photoelectric conversion device having a structure according to the present invention. FIG. 2 is an energy band diagram of FIG. 1D. DESCRIPTION OF SYMBOLS 1...Substrate, 2...First non-single crystal semiconductor, 3
...Second non-single crystal semiconductor, 4...Insulating film.
Claims (1)
半導体の一主面側にのみＰ型の半導体領域とＮ型
の半導体領域とを電子・ホールの拡散距離よりも
短くかつ互いに離間して配置せしめ、前記一主面
側とは反対側の他の主面側に光照射をして、前記
真性または実質的に真性の半導体で発生した電子
およびホールを前記ＮおよびＰ型の半導体領域に
集めることを特徴とする光電変換装置。1. An intrinsic or substantially intrinsic semiconductor is provided, and a P-type semiconductor region and an N-type semiconductor region are arranged only on one main surface side of the semiconductor so as to be shorter than the diffusion distance of electrons and holes and spaced apart from each other. , irradiating light onto the other main surface opposite to the one main surface to collect electrons and holes generated in the intrinsic or substantially intrinsic semiconductor in the N and P type semiconductor regions; A photoelectric conversion device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61315203A JPS62202568A (en) | 1986-12-26 | 1986-12-26 | Photoelectric conversion device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61315203A JPS62202568A (en) | 1986-12-26 | 1986-12-26 | Photoelectric conversion device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17147879A Division JPS5696879A (en) | 1979-12-30 | 1979-12-30 | Manufacture of photoelectric converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62202568A JPS62202568A (en) | 1987-09-07 |
| JPH0568866B2 true JPH0568866B2 (en) | 1993-09-29 |
Family
ID=18062645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61315203A Granted JPS62202568A (en) | 1986-12-26 | 1986-12-26 | Photoelectric conversion device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62202568A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53143180A (en) * | 1977-05-18 | 1978-12-13 | Energy Conversion Devices Inc | Amorphous semiconductor structure and method of producing same |
| JPS5463690A (en) * | 1978-05-22 | 1979-05-22 | Yamazaki Shunpei | Photovoltaic force generating semiconductor and method of producing same |
| JPS5477088A (en) * | 1977-12-01 | 1979-06-20 | Toshiba Corp | Semiconductor photo detector |
-
1986
- 1986-12-26 JP JP61315203A patent/JPS62202568A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53143180A (en) * | 1977-05-18 | 1978-12-13 | Energy Conversion Devices Inc | Amorphous semiconductor structure and method of producing same |
| JPS5477088A (en) * | 1977-12-01 | 1979-06-20 | Toshiba Corp | Semiconductor photo detector |
| JPS5463690A (en) * | 1978-05-22 | 1979-05-22 | Yamazaki Shunpei | Photovoltaic force generating semiconductor and method of producing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62202568A (en) | 1987-09-07 |
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