JPH056667Y2 - - Google Patents
Info
- Publication number
- JPH056667Y2 JPH056667Y2 JP16990685U JP16990685U JPH056667Y2 JP H056667 Y2 JPH056667 Y2 JP H056667Y2 JP 16990685 U JP16990685 U JP 16990685U JP 16990685 U JP16990685 U JP 16990685U JP H056667 Y2 JPH056667 Y2 JP H056667Y2
- Authority
- JP
- Japan
- Prior art keywords
- plate
- stud
- fin
- shaped
- semiconductor stack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 38
- 238000004080 punching Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Rectifiers (AREA)
Description
【考案の詳細な説明】
[産業上の利用分野]
この考案は、複数のスタツド形半導体素子を組
合せて単相全波整流ブリツジなどを形成する半導
体スタツクに関する。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a semiconductor stack in which a plurality of stud-type semiconductor elements are combined to form a single-phase full-wave rectifier bridge or the like.
[従来の技術]
第3図は従来のこの種の半導体スタツクの一例
を示す平面図である。[Prior Art] FIG. 3 is a plan view showing an example of a conventional semiconductor stack of this type.
図において、半導体スタツク1はスタンド2,
2間にスタツド3が挿通され、このスタツド3に
絶縁スペーサ4により所定の間隔を隔てて複数
の、図示では4枚の板状フイン5が配置されてい
る。それら各板状フイン5には、たとえばダイオ
ードのようなスタツド形半導体素子6が図示のよ
うな極性でねじ止めされ、スタツド形半導体素子
6のアノード端子6aには、リード線7の一端が
板状フイン5の透孔5aを通して接続され、他端
は共通端子8に接続されている。 In the figure, a semiconductor stack 1 is connected to a stand 2,
A stud 3 is inserted between the two, and a plurality of plate-shaped fins 5 (four in the figure) are arranged on the stud 3 at predetermined intervals with an insulating spacer 4. A stud-type semiconductor element 6, such as a diode, is screwed to each of the plate-shaped fins 5 with the polarity as shown in the figure, and one end of a lead wire 7 is connected to the anode terminal 6a of the stud-type semiconductor element 6. It is connected through the through hole 5a of the fin 5, and the other end is connected to the common terminal 8.
上記リード線7は第4図に示すように、より線
から構成され、その両端に圧着端子7a,7aを
有する構造となつている。 As shown in FIG. 4, the lead wire 7 is made of a stranded wire and has crimp terminals 7a, 7a at both ends thereof.
[考案が解決しようとする問題点]
上記にように構成された従来の半導体スタツク
は、配線用のリード線として、より線を使用して
いるために、半導体スタツク全体の製造原価が高
くなり、またリード線の両端をねじ止めしなけれ
ばならず、部品点数および組立工数がかかるなど
の問題点があつた。[Problems to be solved by the invention] The conventional semiconductor stack configured as described above uses stranded wires as lead wires for wiring, which increases the manufacturing cost of the entire semiconductor stack. Further, both ends of the lead wire had to be screwed, which caused problems such as the number of parts and the number of assembly steps required.
[考案の目的]
この考案は、上記のような問題点を解決するた
めになされたもので、部品点数および組立工数を
削減し、安価に製作し得る半導体スタツクを得る
ことを目的とするものである。[Purpose of the invention] This invention was made in order to solve the above-mentioned problems, and its purpose is to reduce the number of parts and assembly man-hours, and to obtain a semiconductor stack that can be manufactured at low cost. be.
[問題点を解決するための手段]
この考案にかかる半導体スタツクは、板状フイ
ンの同一平面内に、打抜き加工によつて突起部を
形成し、この突起部に、対向面の板状フインに取
付けた前記スタツド形半導体素子の外部端子の小
孔を引つ掛けて両者をはんだなどで固着し、電気
的に接続したものである。[Means for solving the problem] In the semiconductor stack according to this invention, a protrusion is formed in the same plane of the plate-like fin by punching, and the protrusion is attached to the plate-like fin on the opposite surface. The small holes of the external terminals of the attached stud-type semiconductor element are hooked together and the two are fixed with solder or the like to electrically connect them.
[作用]
この考案の半導体スタツクにおいては、板状フ
インに設けた突起部がスタツド形半導体素子の外
部端子と直接接続される端子の役割をする。[Function] In the semiconductor stack of this invention, the projections provided on the plate-like fins serve as terminals that are directly connected to external terminals of the stud-shaped semiconductor element.
[実施例]
以下に、この考案の実施例を第1図および第2
図を参照して説明する。[Example] Below, an example of this invention is shown in Figures 1 and 2.
This will be explained with reference to the figures.
第1図はこの考案の一実施例である半導体スタ
ツクの平面図、第2図は上記半導体スタツクに使
用する板状フインおよびスタツド形半導体素子の
組立部品図である。 FIG. 1 is a plan view of a semiconductor stack which is an embodiment of this invention, and FIG. 2 is an assembled parts diagram of a plate-shaped fin and a stud-shaped semiconductor element used in the semiconductor stack.
これらの図において、従来の半導体スタツクと
同一、または相当部分には同一符号が付してあ
る。 In these figures, parts that are the same as or corresponding to those of the conventional semiconductor stack are given the same reference numerals.
そこで、板状フイン5の片隅に、その同一平面
内に打抜き加工により突起部5bを形成する。5
cは打抜き加工によつて生じた打抜き部である。
前記の突起部5bの外径は、スタツド形半導体素
子6の外部端子6aの頭部に設けた小孔6bが入
る大きさとする。その他に突起部5bには、何等
の折曲げ加工を施さない。 Therefore, a protrusion 5b is formed at one corner of the plate-like fin 5 in the same plane by punching. 5
c is a punched portion produced by punching.
The outer diameter of the projection 5b is made large enough to accommodate the small hole 6b provided at the head of the external terminal 6a of the stud-shaped semiconductor element 6. Other than that, the protrusion 5b is not subjected to any bending process.
次に、上記板状フイン5を用いた半導体スタツ
クの組立手順を説明する。 Next, a procedure for assembling a semiconductor stack using the plate-like fins 5 will be explained.
まず、並設する板状フイン5の間隔Lを、スタ
ツド形半導体素子6の外部端子6aの頭部に設け
た小孔6bの中心から、スタツド形半導体素子6
のベース部6dの下面に到るまでの寸法Lに等し
くなるように、あらかじめ絶縁スペーサの長さを
決めておく。 First, the interval L between the parallel plate-like fins 5 is measured from the center of the small hole 6b provided in the head of the external terminal 6a of the stud-shaped semiconductor element 6.
The length of the insulating spacer is determined in advance so that it is equal to the dimension L up to the bottom surface of the base portion 6d.
次に、スタツド形半導体素子6のスタツド部6
cを板状フイン5に仮りねじ止めし、外部端子6
aの頭部の小孔6bを、隣接する板状フイン5の
突起部5bに引つ掛けた後、前記スタツド部6c
のねじを完全に締める。 Next, the stud portion 6 of the stud type semiconductor device 6
Temporarily screw c to the plate-like fin 5, and connect the external terminal 6.
After hooking the small hole 6b of the head part of a to the protrusion part 5b of the adjacent plate-like fin 5, the stud part 6c
Tighten the screws completely.
以上のようにしてスタツド形半導体素子6を、
必要な個数だけ板状フイン5に取付けた後、最後
に前記小孔6bと突起部5bの係合部分をはんだ
付けして半導体スタツクの組立を完了する。 As described above, the stud-type semiconductor device 6 is
After attaching the required number to the plate-like fin 5, the engagement portion between the small hole 6b and the protrusion 5b is finally soldered to complete the assembly of the semiconductor stack.
[考案の効果]
上記のようにこの考案は、板状フインの同一平
面内に、打抜き加工によつて突起部を形成し、こ
の突起部に、対向面の板状フインに取付けた前記
スタツド形半導体素子の外部端子の小孔を引つ掛
けて両者をはんだなどで固着し、電気的に接続す
る構成としたので、板状フインとスタツド形半導
体素子の外部端子との接続には、はんだなどの固
着剤以外、一切の接続のための部品を不要とし、
部品点数および組立工数の削減が図れ、また、接
続部品として高価な、より線を使用しないので、
この種の半導体スタツクを安価に製作できるなど
の優れた効果を奏する。[Effects of the invention] As described above, this invention forms a protrusion in the same plane of a plate-like fin by punching, and the stud-shaped stud is attached to this protrusion on the plate-like fin on the opposite surface. Since the configuration is such that the small hole of the external terminal of the semiconductor element is hooked and the two are fixed with solder or the like and electrically connected, the connection between the plate-shaped fin and the external terminal of the stud-shaped semiconductor element requires no solder or other suitable material. Eliminates the need for any connection parts other than the adhesive,
The number of parts and assembly man-hours can be reduced, and expensive stranded wires are not used as connection parts.
This type of semiconductor stack can be manufactured at a low cost, and has excellent effects.
第1図はこの考案の一実施例を示す半導体スタ
ツクの平面図、第2図は上記半導体スタツクに使
用する板状フインおよびスタツド形半導体素子の
組立部品図、第3図は従来の半導体スタツクの平
面図、第4図は上記従来の半導体スタツクに使用
する配線用より線の平面図である。
図において、1……半導体スタツク、5……板
状フイン、5b……突起部、6……スタツド形半
導体素子、6a……外部端子、6b……小孔であ
る。なお、各図中、同一符号は同一、または相当
部分を示す。
Fig. 1 is a plan view of a semiconductor stack showing an embodiment of this invention, Fig. 2 is an assembled parts diagram of a plate-like fin and a stud-shaped semiconductor element used in the semiconductor stack, and Fig. 3 is a diagram of a conventional semiconductor stack. FIG. 4 is a plan view of a stranded wire for wiring used in the conventional semiconductor stack described above. In the figure, 1... semiconductor stack, 5... plate-shaped fin, 5b... protrusion, 6... stud type semiconductor element, 6a... external terminal, 6b... small hole. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
対向面に、その頭部に小孔を有する外部端子を備
えた複数のスタツド形半導体素子を取付け、これ
らスタツド形半導体素子間を電気的に接続して回
路構成をなす半導体スタツクにおいて、前記板状
フインの同一平面内に、打抜き加工によつて突起
部を形成し、この突起部に、対向面の板状フイン
に取付けた前記スタツド形半導体素子の外部端子
の小孔を引つ掛けて固定し、両者を電気的に接続
したことを特徴とする半導体スタツク。 A plurality of plate-shaped fins are arranged in parallel, and a plurality of stud-shaped semiconductor elements each having an external terminal with a small hole in the head are attached to the opposing surfaces of the plate-shaped fins, and electrical connection is established between these stud-shaped semiconductor elements. In the semiconductor stack connected to the plate-like fin to form a circuit configuration, a protrusion is formed by punching in the same plane of the plate-like fin, and the stud-shaped plate attached to the plate-like fin on the opposite surface is attached to the protrusion. A semiconductor stack characterized in that a small hole in an external terminal of a semiconductor element is hooked and fixed to electrically connect the two.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16990685U JPH056667Y2 (en) | 1985-11-06 | 1985-11-06 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16990685U JPH056667Y2 (en) | 1985-11-06 | 1985-11-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6278763U JPS6278763U (en) | 1987-05-20 |
JPH056667Y2 true JPH056667Y2 (en) | 1993-02-19 |
Family
ID=31104140
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16990685U Expired - Lifetime JPH056667Y2 (en) | 1985-11-06 | 1985-11-06 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH056667Y2 (en) |
-
1985
- 1985-11-06 JP JP16990685U patent/JPH056667Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6278763U (en) | 1987-05-20 |
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