JPH0564498B2 - - Google Patents
Info
- Publication number
- JPH0564498B2 JPH0564498B2 JP59040860A JP4086084A JPH0564498B2 JP H0564498 B2 JPH0564498 B2 JP H0564498B2 JP 59040860 A JP59040860 A JP 59040860A JP 4086084 A JP4086084 A JP 4086084A JP H0564498 B2 JPH0564498 B2 JP H0564498B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- signal line
- short
- signal
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000005540 biological transmission Effects 0.000 claims description 29
- 238000001514 detection method Methods 0.000 claims description 20
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 101100172132 Mus musculus Eif3a gene Proteins 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/46—Monitoring; Testing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
Description
【発明の詳細な説明】
〔技術分野〕
本発明は端末器間で信号線を介してデータをベ
ースバンド伝送するようにした情報伝送装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an information transmission device that performs baseband transmission of data between terminal devices via a signal line.
従来、この種の情報伝送装置は第１図および第
２図に示すように構成されており、各端末器１は
１対の信号線２間に直流電圧Vccを印加するプル
アツプ抵抗３と、信号線２間を送信すべきデータ
に基いて短絡自在とするスイツチング用トランジ
スタQ0よりなる送信手段４と、信号線２間の電
圧が所定電圧以上かどうかを判別するインバータ
回路Ｉよりなるデータ受信手段５と、送信すべき
データを作成するとともに受信されたデータの信
号処理を行なうインターフエース用ロジツク回路
６とで構成されている。DOは送信データ出力端
子、DIは受信データ入力端子、７，８は信号線
接続端子であり、各端末器１間を接続する信号線
２として同軸ケーブルが用いられており、この信
号線２を介して各端末器１間でデータを送受信す
るようになつている。この場合、信号線２は各端
末器１にて共通利用されるバス方式となつてお
り、各端末器１間の送信データが干渉し合うのを
防止するためCSMA／CDのようなプロトコルが
用いられる。
Conventionally, this type of information transmission device has been configured as shown in FIGS. Transmitting means 4 consisting of a switching transistor Q0 that can be freely short-circuited between lines 2 based on data to be transmitted, and data receiving means consisting of an inverter circuit I that determines whether the voltage between signal lines 2 is higher than a predetermined voltage. 5, and an interface logic circuit 6 that creates data to be transmitted and performs signal processing of received data. DO is a transmission data output terminal, DI is a reception data input terminal, and 7 and 8 are signal line connection terminals.A coaxial cable is used as the signal line 2 that connects each terminal 1, and this signal line 2 Data is transmitted and received between each terminal device 1 via the terminal device 1. In this case, the signal line 2 is a bus that is commonly used by each terminal 1, and a protocol such as CSMA/CD is used to prevent data transmitted between each terminal 1 from interfering with each other. It will be done.
いま、一端末器１の送信手段４を構成するトラ
ンジスタQ0がオフされているとき、信号線２間
にはプルアツプ抵抗３を介して直流電圧Vccが印
加されており、各端末器１の受信手段５を構成す
るインバータ回路ＩにＨレベルが入力され、イン
バータ回路Ｉ出力はＬレベル（例えばデータ
「０」）となる。一方、送信データに基いてトラン
ジスタQ0がオンされると、信号線２間がトラン
ジスタQ0によつて短絡されてＬレベル（OV）と
なり、各端末器１のインバータ回路ＩにＬレベル
が入力されインバータ回路Ｉ出力はＨレベル（例
えばデータ「１」）となる。 Now, when the transistor Q0 constituting the transmitting means 4 of one terminal device 1 is turned off, a DC voltage Vcc is applied between the signal lines 2 via the pull-up resistor 3, and the reception of each terminal device 1 is The H level is input to the inverter circuit I constituting the means 5, and the output of the inverter circuit I becomes the L level (for example, data "0"). On the other hand, when the transistor Q 0 is turned on based on the transmitted data, the signal line 2 is short-circuited by the transistor Q 0 and becomes an L level (OV), and an L level is input to the inverter circuit I of each terminal device 1. As a result, the inverter circuit I output becomes H level (for example, data "1").
ところで、このような従来例において、何らか
の事故で信号線２間が短絡された場合、信号線２
間電圧が常にＬレベルとなつて信号線２を共用し
ているすべての端末器１間のデータ伝送が不可能
になつてしまうという問題があつた。 By the way, in such a conventional example, if the signal line 2 is short-circuited due to some accident, the signal line 2
There was a problem in that the voltage between terminals was always at L level, making it impossible to transmit data between all the terminal devices 1 sharing the signal line 2.
本発明は上記の点に鑑みて為されたものであ
り、その目的とするところは、信号線の短絡事故
発生時におけるデータの伝送不能範囲を最小限に
することができる情報伝送装置を提供することに
ある。
The present invention has been made in view of the above points, and its purpose is to provide an information transmission device that can minimize the range in which data cannot be transmitted when a short-circuit accident occurs in a signal line. There is a particular thing.
実施例
第３図乃至第５図は本発明一実施例を示すもの
で、従来と同様の情報伝送装置において、各端末
器１に設けられた複数の信号線接続端子７，８と
データ送信手段４およびデータ受信手段５との間
にリレーR1，R2の接点r1，r2よりなるスイツチ手
段１４を設け、信号線２間の信号レベルがＮビツ
ト分（実施例では９ビツト）以上連続してＬレベ
ルにならないような所定の伝送フオーマツトでデ
ータ伝送を行うとともにに、Ｎビツト分以上信号
線の信号レベルがＬレベルのとき短絡検出信号
Vsを出力する短絡検出回路１０出力に基いて上
記スイツチ手段１４を制御していずれかの接点
r1，r2をオフすることにより短絡されている信号
線２を切離すようにしてある。ここに、ロジツク
回路６は第４図に示すようにシリアルデータより
なる送信データ、受信データを送受信するシリア
ルインターフエース１１、短絡検出回路１０、信
号処理用CPU１２、リレー制御信号を出力端子
RC1，RC2に出力する出力ポート１３とで構成さ
れ、短絡検出回路１０は第５図に示すようにＤフ
リツプフロツプF1，F2，F4，F5、Ｓ−Ｒフリツ
プフロツプF3，F6およびアンド回路A1〜A3にて
形成されている。
Embodiment FIGS. 3 to 5 show an embodiment of the present invention, in which a plurality of signal line connection terminals 7 and 8 provided in each terminal 1 and a data transmission means are used in a conventional information transmission device. A switch means 14 consisting of contacts r 1 and r 2 of relays R 1 and R 2 is provided between the signal line 4 and the data receiving means 5, and the signal level between the signal lines 2 is equal to or more than N bits (9 bits in the embodiment). In addition to transmitting data in a predetermined transmission format that does not continuously go to L level, when the signal level of the signal line for N bits or more is L level, a short circuit detection signal is generated.
Based on the output of the short-circuit detection circuit 10 that outputs Vs, the switching means 14 is controlled so that one of the contacts
The short-circuited signal line 2 is disconnected by turning off r 1 and r 2 . As shown in FIG. 4, the logic circuit 6 includes a serial interface 11 for transmitting and receiving serial data and receiving data, a short circuit detection circuit 10, a signal processing CPU 12, and a relay control signal output terminal.
As shown in FIG . 5, the short circuit detection circuit 10 includes D flip-flops F 1 , F 2 , F 4 , F 5 and S-R flip-flops F 3 , F 5 . 6 and AND circuits A 1 to A 3 .
以下、実施例の動作について具体的に説明す
る。いま、信号線２の短絡事故が発生していない
場合において、リレーR1，R2の接点r1，r2は共に
オンされており、各端末器１間のデータ伝送は従
来例と全く同様に行なわれる。第６図は信号線２
を介して伝送されるデータ信号の一例を示すもの
で、スタートビツトSaのＬレベルに続いて８ビ
ツトのデータビツトD0〜D7が続き、ストツプビ
ツトSbのＨレベルが続くようになつている。次
に信号線２のいずれかの箇所で短絡事故が発生す
ると、信号線２間の電圧は常にＬレベルとなり、
全端末器１間のデータ伝送が不可能となる。この
場合、短絡検出回路１０では受信データ入力端子
DIに入力されるデータが一定期間（例えば９ビ
ツト）以上Ｈレベルのときすなわち信号線２間の
電圧がＬレベルのとき信号線２が短絡されている
ものと判定して短絡検出信号Vsを出力する。こ
こで、使用されるデータ伝送のフオーマツトは第
６図に示すようになつており、スタートビツト１
ビツト、データビツト８ビツト、パリテイビツト
なし、ストツプビツト１ビトとした場合、NRZ
符号を使用していればデータ０の場合が最もＬレ
ベルが長くなり、９ビツト分となる。したがつ
て、データ伝送が正常に行われている場合には、
９ビツト分より長いＬレベル期間が続くことがな
いため、９ビツト分以上Ｌレベルが続いたとき短
絡故障と判定できる。なお、短絡検出回路１０の
前半部１０ａはノイズ除去部を形成しており、短
かい周期のクロツクφ1を用いてクロツクφ1の周
期以下のパルス巾を有するノイズパルスを除去す
るようになつており、後半部１０ｂは受信データ
入力端子DIのＨレベル期間がクロツクφ2の周期
以上（例えばデータ信号の９ビツト以上）のとき
に短絡とみなして短絡検出信号Vsを出力する短
絡判別部である。ところで、短絡検出回路１０か
ら短絡検出信号Vsが出力されると、CPU１２で
は信号線接続端子７，８のうちいずれに接続され
ている信号線２が短絡されているかを判定し、短
絡されている方の接点r1あるいはr2をオフしてそ
の信号線２を切離すとともに他方をオンにする。
すなわち第３図において右側の信号線接続端子８
に接続されている信号線２に短絡事故が発生して
いる場合、接点r1がオンでr2がオフのときにデー
タ伝送が可能で，r1がオフでr2がオンのときにデ
ータ伝送が不可能となるので、右側の信号線２に
短絡事故が生じていると判断して出力ポート１３
からリレーR1，R2を制御するリレー制御信号を
出力し、リレーR1，R2を駆動して接点r2をオフ
にするとともに接点r1をオンにする。同様にして
各端末器１にて短絡検出および短絡されている側
の信号線２の切離しが行なわれ、信号線２の短絡
部分のみが伝送路から切離され、信号線２の残り
の部分を介して各端末器１間でデータの送受信が
行なわれる。なお、この場合、当然のことながら
信号線２の短絡部分を越えてデータ伝送を行なう
ことはできないが短絡部分の両側でそれぞれ独立
にデータ伝送が行なえることになる。したがつ
て、信号線２の短絡事故発生時におけるデータの
伝送不能範囲を最小限にすることができるように
なつている。 The operation of the embodiment will be specifically explained below. Now, when no short-circuit accident occurs in signal line 2, contacts r 1 and r 2 of relays R 1 and R 2 are both turned on, and data transmission between each terminal device 1 is exactly the same as in the conventional example. It will be held in Figure 6 shows signal line 2
This shows an example of a data signal transmitted via a start bit Sa at an L level, followed by 8 data bits D0 to D7 , and a stop bit Sb at an H level. Next, if a short circuit occurs at any point on signal line 2, the voltage between signal line 2 will always be at L level,
Data transmission between all terminal devices 1 becomes impossible. In this case, in the short circuit detection circuit 10, the reception data input terminal
When the data input to DI is at H level for a certain period of time (for example, 9 bits) or more, that is, when the voltage between signal line 2 is at L level, it is determined that signal line 2 is short-circuited and a short circuit detection signal Vs is output. do. The data transmission format used here is as shown in Figure 6, and the start bit is 1.
bit, 8 data bits, no parity bit, and 1 stop bit, NRZ
If a code is used, the L level will be the longest for data 0, which is 9 bits. Therefore, if data transmission is normal,
Since an L level period that is longer than 9 bits does not continue, a short-circuit failure can be determined when the L level continues for 9 bits or more. Note that the first half 10a of the short circuit detection circuit 10 forms a noise removal section, which uses the short cycle clock φ1 to remove noise pulses having a pulse width less than the cycle of the clock φ1 . The second half 10b is a short-circuit discriminating section that regards it as a short-circuit and outputs a short-circuit detection signal Vs when the H-level period of the received data input terminal DI is longer than the period of the clock φ2 (for example, 9 bits or more of the data signal). . By the way, when the short circuit detection signal Vs is output from the short circuit detection circuit 10, the CPU 12 determines which of the signal line connection terminals 7 and 8 the signal line 2 is connected to, and determines whether the signal line 2 is short-circuited. One contact r1 or r2 is turned off to disconnect the signal line 2, and the other is turned on.
In other words, the signal line connection terminal 8 on the right side in FIG.
If a short -circuit accident occurs in signal line 2 connected to Since transmission becomes impossible, it is determined that a short circuit has occurred in the right signal line 2, and the output port 13 is
outputs a relay control signal to control relays R 1 and R 2 , and drives relays R 1 and R 2 to turn off contact r 2 and turn on contact r 1 . In the same way, each terminal device 1 detects a short circuit and disconnects the signal line 2 on the short-circuited side, and only the short-circuited part of the signal line 2 is disconnected from the transmission path, and the remaining part of the signal line 2 is disconnected. Data is transmitted and received between each terminal device 1 via the terminal device 1. In this case, data cannot be transmitted across the short-circuited portion of the signal line 2, but data can be transmitted independently on both sides of the short-circuited portion. Therefore, the range in which data cannot be transmitted when a short-circuit accident occurs in the signal line 2 can be minimized.
ところで、実施例にあつては、各端末器１にて
信号線２の短絡部分の切離しを上述のようにして
行なうとともに、各端末器１に割当られた期間に
自己の固有アドレスを送信データとして送信する
ことにより、短絡発生箇所をすべての端末器１で
判別できるようにしてあり、以下短絡発生箇所の
判別動作について第７図を用いて概説する。い
ま、Ｘ点で短絡事故が発生して各端末器１の短絡
検出回路１０から短絡検出信号Vsが出力される
と、まず最初にすべての端末器１の接点r1，r2が
オフされ、続いて端末器１1，１2，１3，１4…１
Ｎのスイツチ手段１４が順次動作して各端末器１
１〜１Ｎの短絡されている側の信号線２を切離す。
この場合、各端末器１1〜１Ｎにおける短絡され
ている側の信号線２の検出およびスイツチ手段１
４の動作タイミングすなわち短絡されている信号
線２の切離し動作期間は適当に（ａ秒）設定され
ており、短絡検出信号Vsが出力された直後に端
の端末器１1から順に上記切離し動作を行なうよ
うになつており、ｎ番目の端末器１ｎではａ×ｎ
秒後に切離し動作が行なわれる。例えば、第７図
のように端末器１3と端末器１4との間で短絡事故
が発生している場合、第１、端末器１1および１2
においては両側の信号線１が共に短絡されていな
いので、接点r1，r2が順次オンされてゆく。一
方、端末器１3においては右側の信号線２に短絡
事故が発生しているので、接点r1がオンされるが
接点r2はオフされる。同様にして端末器１4にお
いては左側の信号線２に短絡事故が発生している
ので、接点r1がオフされ、接点r2がオンされる。
また、端末器１4〜１Ｎにおいては、両側の信号
線２が共に短絡されていないので、接点r1，r2が
順次オンされてゆく。ここに、各端末器１1〜１
Ｎにおいて、信号線２の選択接続動作の完了した
時点で自己の固有アドレスを送信データとして送
信するようになつている。したがつて、短絡事故
発生箇所（Ｘ点）の左側では端末器１1〜１3の固
有アドレスが順次伝送され、各端末器１1〜１3で
は最後に伝送された固有アドレスに基いて端末器
１3の右側の信号線２において短絡事故が発生し
たことを判別できるようになつている。一方、短
絡事故発生箇所の右側では端末器１4〜１Ｎの固
有アドレスが順次伝送され、各端末器１4〜１Ｎ
では最初に伝送された固有アドレスに基いて端末
器１4の左側の信号線２において短絡事故が発生
したことを判別できることになる。したがつて、
短絡事故により部分的にデータ伝送が不可能な部
分が生じても各端末器１1〜１Ｎではデータ伝送
が可能な範囲を常に認識してデータ伝送を行なう
ことができ、データの伝送ミスが発生しないよう
になつている。 By the way, in the embodiment, each terminal device 1 disconnects the short-circuited portion of the signal line 2 as described above, and also sends its own unique address as transmission data during the period assigned to each terminal device 1. By transmitting this information, all the terminal devices 1 can determine the location where a short circuit has occurred.The operation for determining the location where a short circuit has occurred will be outlined below using FIG. Now , when a short-circuit accident occurs at point Next, terminal devices 1 1 , 1 2 , 1 3 , 1 4 ...1
N switch means 14 operate in sequence to switch each terminal 1
1 to 1N, disconnect the short-circuited signal line 2.
In this case, the detection and switching means 1 of the signal line 2 on the short-circuited side in each terminal device 1 1 to 1N
The operation timing of step 4, that is, the disconnection operation period of the short-circuited signal line 2, is set appropriately (a second), and the disconnection operation is performed sequentially from the terminal device 1 at the end immediately after the short circuit detection signal Vs is output. In the n-th terminal device 1n, a×n
After a few seconds, the disconnection operation takes place. For example, if a short circuit occurs between terminal device 1 3 and terminal device 1 4 as shown in FIG .
Since the signal lines 1 on both sides are not short-circuited, the contacts r 1 and r 2 are turned on sequentially. On the other hand, in the terminal device 13 , a short circuit has occurred in the right signal line 2, so the contact r1 is turned on, but the contact r2 is turned off. Similarly, in the terminal device 14 , a short circuit has occurred in the left signal line 2, so the contact r1 is turned off and the contact r2 is turned on.
Further, in the terminal devices 1 4 to 1N, since the signal lines 2 on both sides are not short-circuited, the contacts r 1 and r 2 are sequentially turned on. Here, each terminal device 1 1 to 1
When the selective connection operation of the signal line 2 is completed, the device N transmits its own unique address as transmission data. Therefore , on the left side of the point where the short -circuit accident occurred ( point It can be determined that a short circuit has occurred in the signal line 2 on the right side of the device 13 . On the other hand, on the right side of the short-circuit accident location, the unique addresses of terminal devices 1 4 to 1N are transmitted sequentially, and each terminal device 1 4 to 1N
Then, based on the first transmitted unique address, it can be determined that a short-circuit accident has occurred in the left signal line 2 of the terminal device 14 . Therefore,
Even if there is a part where data transmission is impossible due to a short-circuit accident, each terminal device 11 to 1N can always recognize the range in which data transmission is possible and perform data transmission, and data transmission errors may occur. I've learned not to.
本発明は上述のように構成されており、端末器
間で信号線を介してデータをベースバンド伝送す
るようにした情報伝送装置において、各端末器設
けられた複数の信号線接続端子とデータ送信手段
およびデータ受信手段との間にスイツチ手段を設
け、信号線間の電圧が予め設定された時間以上Ｌ
レベルのとき短絡検出信号を出力する短絡検出回
路出力に基いて上記スイツチ手段を制御して短絡
されている側の信号線の切離すようにしたもので
あり、信号線の短絡事故発生を検出して信号線の
短絡発生部分を端末器の信号線接続端子から切離
すことにより、信号線の残りの部分にてデータ伝
送を行なえるようにしているので、信号線の短絡
事故発生時におけるデータの伝送不能範囲を最小
限にすることができるという効果がある。また、
信号線の信号レベルがＮビツト分以上連続してＬ
レベルにならないような所定の伝送フオーマツト
でデータ伝送を行うとともに、Ｎビツト分以上信
号線の信号レベルがＬレベルのとき短絡検出信号
を出力するように短絡検出回路を構成しており、
信号線上の信号のフオーマツトを変更することな
く簡単な構成で短絡検出が行えるという効果があ
る。
The present invention is configured as described above, and provides an information transmission device for baseband transmission of data via a signal line between terminals, in which a plurality of signal line connection terminals provided in each terminal and data transmission are provided. A switch means is provided between the means and the data receiving means, and the voltage between the signal lines is L for a preset time or more.
Based on the output of the short circuit detection circuit which outputs a short circuit detection signal when the level is high, the above-mentioned switch means is controlled to disconnect the signal line on the short-circuited side, and it is possible to detect the occurrence of a short-circuit accident in the signal line. By disconnecting the part of the signal line where a short circuit has occurred from the signal line connection terminal of the terminal device, data can be transmitted using the remaining part of the signal line. This has the effect of minimizing the range where transmission is impossible. Also,
The signal level of the signal line is continuously low for more than N bits.
The short circuit detection circuit is configured to transmit data in a predetermined transmission format such that the signal line does not reach the L level, and to output a short circuit detection signal when the signal level of the signal line for N bits or more is L level.
This has the advantage that short circuit detection can be performed with a simple configuration without changing the format of the signal on the signal line.
第１図は従来例の概略構成図、第２図は同上の
要部回路図、第３図乃至第５図は本発明一実施例
の要部回路図、第６図および第７図は同上の動作
説明図である。
１は端末器、２は信号線、３はプルアツプ抵
抗、４はデータ送信手段、５はデータ受信手段、
１０は短絡検出回路、１４はスイツチ手段であ
る。
FIG. 1 is a schematic configuration diagram of a conventional example, FIG. 2 is a circuit diagram of the same essential parts as above, FIGS. 3 to 5 are circuit diagrams of essential parts of an embodiment of the present invention, and FIGS. 6 and 7 are same as above. FIG. 1 is a terminal device, 2 is a signal line, 3 is a pull-up resistor, 4 is a data transmitting means, 5 is a data receiving means,
10 is a short circuit detection circuit, and 14 is a switch means.
Claims (1)
流電圧を印加し、信号線間を送信すべきデータに
基いて短絡自在としたデータ送信手段を設けると
ともに信号線間の電圧が所定電圧以上かどうかを
判別してデータを受信するデータ受信手段を設け
ることにより端末器を形成し、複数の端末器を同
一の信号線に接続して各端末器間でデータを送受
信せしめて成る情報伝送装置において、各端末器
に設けられた複数の信号線接続端子とデータ送信
手段およびデータ受信手段との間にそれぞれスイ
ツチ手段を設け、信号線の信号レベルがＮビツト
分以上連続してＬレベルにならないような所定の
伝送フオーマツトでデータ伝送を行うとともに、
Ｎビツト分以上信号線の信号レベルがＬレベルの
とき短絡検出信号を出力する短絡検出回路出力に
基いて上記スイツチ手段を制御して短絡されてい
る側の信号線を切離すようにしたことを特徴とす
る情報伝送装置。1. A data transmission means is provided in which a DC voltage is applied between a pair of signal lines via a pull-up resistor, and the signal lines can be freely shorted based on the data to be transmitted, and the voltage between the signal lines is set to a predetermined voltage or higher. In an information transmission device in which a terminal device is formed by providing a data receiving means for receiving data by determining whether the terminal device , switch means are provided between the plurality of signal line connection terminals provided in each terminal device and the data transmitting means and the data receiving means, respectively, so that the signal level of the signal line does not become L level continuously for more than N bits. In addition to transmitting data in a predetermined transmission format,
The switching means is controlled based on the output of a short-circuit detection circuit that outputs a short-circuit detection signal when the signal level of the signal line for N bits or more is at L level, and the signal line on the short-circuited side is disconnected. Characteristic information transmission device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59040860A JPS60185449A (en) | 1984-03-02 | 1984-03-02 | Information transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59040860A JPS60185449A (en) | 1984-03-02 | 1984-03-02 | Information transmitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60185449A JPS60185449A (en) | 1985-09-20 |
| JPH0564498B2 true JPH0564498B2 (en) | 1993-09-14 |
Family
ID=12592293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59040860A Granted JPS60185449A (en) | 1984-03-02 | 1984-03-02 | Information transmitter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60185449A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0659054B2 (en) * | 1987-07-17 | 1994-08-03 | 株式会社日立製作所 | Data transmission device |
| WO1993011620A1 (en) * | 1991-12-02 | 1993-06-10 | The Furukawa Electric Co., Ltd. | Method for recovering failured transmission line |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5628058A (en) * | 1979-08-16 | 1981-03-19 | Mazda Motor Corp | Tilt locking device for tiltable cabin car |
-
1984
- 1984-03-02 JP JP59040860A patent/JPS60185449A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5628058A (en) * | 1979-08-16 | 1981-03-19 | Mazda Motor Corp | Tilt locking device for tiltable cabin car |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60185449A (en) | 1985-09-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4009469A (en) | Loop communications system with method and apparatus for switch to secondary loop | |
| JP3631791B2 (en) | Device for serial transmission of data between at least two stations | |
| US5357518A (en) | Network interface | |
| EP2754057B1 (en) | Circuit and electronic module for automatic addressing | |
| JP2851124B2 (en) | Multiplex transmission method | |
| US5719509A (en) | Method of controlling transmission of binary pulses on a transmission line | |
| KR20000005107A (en) | Bus system for data transfer | |
| US6633935B1 (en) | Automatic bus termination readjustment | |
| US5436887A (en) | Digital full-duplex transceiver | |
| JPH0564498B2 (en) | ||
| US5034966A (en) | Redundant and fault tolerant communication link | |
| EP0199338B1 (en) | Repeater circuit | |
| JP3201666B2 (en) | Interface conversion circuit for half-duplex serial transmission | |
| EP0505306B1 (en) | Control circuit for half-duplex/simplex interface in communication system | |
| JPH09160690A (en) | Bus driver fault detection system | |
| JPS60117843A (en) | Signal output system of data transmission system | |
| JP3550442B2 (en) | Encoder signal communication method | |
| JP3506508B2 (en) | Data transmission method and data transmission system | |
| JPH09205358A (en) | Output circuit | |
| JPH023342B2 (en) | ||
| JP2005038026A (en) | Microcontroller including can controller | |
| JPS61267428A (en) | Information communication system | |
| JPH0691557B2 (en) | Information transmission device | |
| JP2655687B2 (en) | Line switching method | |
| JPH06181591A (en) | Multiplex transmitter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |