JPH0555207A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0555207A JPH0555207A JP3242415A JP24241591A JPH0555207A JP H0555207 A JPH0555207 A JP H0555207A JP 3242415 A JP3242415 A JP 3242415A JP 24241591 A JP24241591 A JP 24241591A JP H0555207 A JPH0555207 A JP H0555207A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- compound semiconductor
- refractive index
- nitride film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Ceramic Products (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、化合物半導体を用いた
半導体装置の半導体表面を保護する構造に関し、特に信
頼性の高い表面保護膜の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for protecting a semiconductor surface of a semiconductor device using a compound semiconductor, and more particularly to a structure of a highly reliable surface protective film.
【０００２】[0002]
【従来技術】従来、ショットキーバリア型の高周波Ｇａ
ＡｓＭＥＳＦＥＴなどの化合物半導体を用いた半導体装
置の保護膜としては、二酸化シリコン膜（ＳｉＯ2 ）、
窒化シリコン膜（Ｓｉ3Ｎ4）またはそれらの多層構造膜
等が用いられている。2. Description of the Related Art Conventionally, a Schottky barrier type high frequency Ga
As a protective film of a semiconductor device using a compound semiconductor such as AsMESFET, a silicon dioxide film (SiO 2 ),
A silicon nitride film (Si 3 N 4 ) or a multilayer structure film thereof is used.
【０００３】窒化シリコン膜を用いた場合、その屈折率
が２．０程度の膜が広く用いられている。これは、屈折
率が２．０程度で膜密度が最大となり、外部からの不純
物侵入に対して最も有効なためである。When a silicon nitride film is used, a film having a refractive index of about 2.0 is widely used. This is because the film density becomes maximum when the refractive index is about 2.0, and it is most effective for invading impurities from the outside.
【０００４】[0004]
【発明が解決しようとする課題】ＧａＡｓなどの化合物
半導体においては、元素半導体であるＳｉとＳｉＯ2 の
組み合わせのような良好な表面保護膜はまだ見いだされ
ていない。化合物半導体の表面保護膜としてＳｉＯ2 ま
たはＳｉ3Ｎ4等の絶縁膜のみを形成した従来の半導体装
置では、表面保護膜と化合物半導体との界面は不安定で
ある。In compound semiconductors such as GaAs, a good surface protective film such as a combination of elemental semiconductors Si and SiO 2 has not yet been found. In the conventional semiconductor device in which only the insulating film such as SiO 2 or Si 3 N 4 is formed as the surface protective film of the compound semiconductor, the interface between the surface protective film and the compound semiconductor is unstable.
【０００５】このため、表面保護膜と化合物半導体の界
面の不安定が原因となって電極間に不必要な電流が流
れ、半導体装置が劣化するという問題があった。特に、
ＧａＡｓＭＥＳＦＥＴでは、表面保護膜とＧａＡｓとの
界面の不安定が原因となり、長時間の動作によりゲート
・ソース電極間、または、ゲート・ドレイン電極間の耐
圧が劣化するという問題があった。Therefore, there is a problem in that an unnecessary current flows between the electrodes due to the instability of the interface between the surface protective film and the compound semiconductor, and the semiconductor device deteriorates. In particular,
The GaAs MESFET has a problem that the breakdown voltage between the gate and source electrodes or between the gate and drain electrodes deteriorates due to long-term operation due to instability at the interface between the surface protective film and GaAs.
【０００６】本発明は、このような表面保護膜とＧａＡ
ｓとの界面の不安定を生じない表面保護膜の構造を提供
するものである。The present invention is directed to such a surface protective film and GaA.
It is intended to provide a structure of a surface protective film which does not cause instability of the interface with s.
【０００７】[0007]
【課題を解決するための手段および作用】本発明による
半導体装置は、化合物半導体と、該化合物半導体の表面
に形成された複数の電極と、該複数の電極間における前
記化合物半導体の表面を被覆する屈折率２．２以上の窒
化シリコン膜と、該窒化シリコン膜を被覆する絶縁膜と
を有することを要旨とする。また、前記絶縁膜が屈折率
２．２未満の窒化シリコンからなるものである。A semiconductor device according to the present invention covers a compound semiconductor, a plurality of electrodes formed on the surface of the compound semiconductor, and the surface of the compound semiconductor between the plurality of electrodes. It is a gist to have a silicon nitride film having a refractive index of 2.2 or more and an insulating film which covers the silicon nitride film. Further, the insulating film is made of silicon nitride having a refractive index of less than 2.2.
【０００８】本発明によれば、化合物半導体と屈折率
２．２以上の窒化シリコン膜との界面は比較的安定とな
り、電極間の不要な電流が低減できる。同時に屈折率
２．２以上の窒化シリコン膜を被覆する絶縁膜により化
合物半導体の十分な保護が可能となる。また、前記絶縁
膜を屈折率２．２未満の窒化シリコンとすれば、窒化シ
リコン膜の作成条件を変えることにより前記界面の安定
化が可能となる。According to the present invention, the interface between the compound semiconductor and the silicon nitride film having a refractive index of 2.2 or more becomes relatively stable, and unnecessary current between the electrodes can be reduced. At the same time, the compound semiconductor can be sufficiently protected by the insulating film covering the silicon nitride film having a refractive index of 2.2 or more. Further, when the insulating film is made of silicon nitride having a refractive index of less than 2.2, the interface can be stabilized by changing the conditions for forming the silicon nitride film.
【０００９】[0009]
【実施例】本発明の一実施例であるＦＥＴ（電界効果ト
ランジスタ）の製造工程を、図１を用いて以下に説明す
る。EXAMPLE A manufacturing process of an FET (field effect transistor) which is an example of the present invention will be described below with reference to FIG.
【００１０】半絶縁性ＧａＡｓ基板１上に気相エピタキ
シャル成長法により、バッファー層としてノンドープＧ
ａＡｓ層２と動作層としてｎ型ＧａＡｓ層３を順次積層
する。ノンドープＧａＡｓ層２の厚さは約２μｍ、ｎ型
ＧａＡｓ層３はＳｉドープでキャリアー濃度３×１０17
／ｃｍ3、厚さ約０．１５μｍ程度に形成されている。
ｎ型ＧａＡｓ層３上にＡｕＧｅ／Ｎｉ／Ａｕの多層構造
からなるオーミック電極４、５を離間して形成する。こ
れらのオーミック電極の間のｎ型ＧａＡｓ層３の表面を
エッチング除去してリセスを形成する。このリセス位置
にｎ型ＧａＡｓ層３とショットキー接触するゲート電極
であるショットキー電極６を形成する。このショットキ
ー電極６は、Ｔｉ／Ａｌ／Ｔｉの積層構造からなり、真
空蒸着法で作成され、その大きさは、幅２８０μｍ、長
さ０．５μｍである。A non-doped G buffer layer is formed on the semi-insulating GaAs substrate 1 by a vapor phase epitaxial growth method.
An aAs layer 2 and an n-type GaAs layer 3 as an operating layer are sequentially laminated. The thickness of the non-doped GaAs layer 2 is about 2 μm, and the n-type GaAs layer 3 is Si-doped and has a carrier concentration of 3 × 10 17.
/ Cm 3 and the thickness is about 0.15 μm.
On the n-type GaAs layer 3, ohmic electrodes 4 and 5 having a multilayer structure of AuGe / Ni / Au are formed separately. The surface of the n-type GaAs layer 3 between these ohmic electrodes is removed by etching to form a recess. At this recessed position, a Schottky electrode 6 which is a gate electrode in Schottky contact with the n-type GaAs layer 3 is formed. The Schottky electrode 6 has a Ti / Al / Ti laminated structure and is formed by a vacuum deposition method, and has a size of 280 μm in width and 0.5 μm in length.
【００１１】このＦＥＴの表面に、屈折率２．２以上の
窒化シリコン膜７（厚さ：約１０ｎｍ）と屈折率２．０
の窒化シリコン膜８（厚さ：５０ｎｍ）を順次形成し、
２層構造の保護膜とする。この窒化シリコン膜７、８は
プラズマＣＶＤ法で形成され、屈折率は原料ガスである
シラン（ＳｉＨ4）ガスとアンモニア（ＮＨ3）ガスの組
成比を変えることで制御している。図２は窒化シリコン
膜の屈折率と原料ガスの組成比（Ｓｉ／Ｎ比）の関係を
示している。屈折率２．２以上の窒化シリコン膜７は、
Ｓｉ／Ｎ比を１．２以上として成膜し、引き続きＳｉ／
Ｎ比を１．０程度として屈折率２．０の窒化シリコン膜
８を成膜している。本実施例では、窒化シリコン膜７の
屈折率が、２．２および３．４のＦＥＴを作成した。A silicon nitride film 7 (thickness: about 10 nm) having a refractive index of 2.2 or more and a refractive index of 2.0 are formed on the surface of this FET.
Silicon nitride film 8 (thickness: 50 nm) is sequentially formed,
The protective film has a two-layer structure. The silicon nitride films 7 and 8 are formed by the plasma CVD method, and the refractive index is controlled by changing the composition ratio of silane (SiH 4 ) gas and ammonia (NH 3 ) gas, which are source gases. FIG. 2 shows the relationship between the refractive index of the silicon nitride film and the composition ratio (Si / N ratio) of the source gas. The silicon nitride film 7 having a refractive index of 2.2 or more is
The Si / N ratio is set to 1.2 or more, and the film is formed.
A silicon nitride film 8 having a refractive index of 2.0 is formed with an N ratio of about 1.0. In this example, FETs having the silicon nitride film 7 having a refractive index of 2.2 and 3.4 were produced.
【００１２】加速試験によるゲート・ドレイン電極間の
ブレークダウン耐圧の経時変化を図３に示す。加速試験
は、ゲート電極／ドレイン電極間に５００μＡ／ｍｍの
電流を流して劣化を加速し、この電極間に１０μＡの逆
電流を流すために必要な電圧をブレークダウン耐圧とし
て測定した。FIG. 3 shows changes with time in breakdown breakdown voltage between the gate and drain electrodes due to the acceleration test. In the acceleration test, a current of 500 μA / mm was passed between the gate electrode and the drain electrode to accelerate the deterioration, and a voltage required to pass a reverse current of 10 μA between the electrodes was measured as a breakdown breakdown voltage.
【００１３】図３において、ａおよびｂは、本実施例で
ある窒化シリコン膜７の屈折率がそれぞれ２．２および
３．４の場合のブレークダウン耐圧の経時変化を示し、
ｃは、比較例として窒化シリコン膜７の屈折率が窒化シ
リコン膜８と同じ２．０の場合の変化を示している。こ
の結果から明らかなように、比較例と比べて、本実施例
においては、ブレークダウン耐圧の経時変化が顕著に減
少している。なお、このような効果は、窒化シリコン膜
７の屈折率が２．０以上２．１以下では再現性が低下す
る。In FIG. 3, a and b show changes with time in breakdown breakdown voltage when the silicon nitride film 7 of this embodiment has a refractive index of 2.2 and 3.4, respectively.
As a comparative example, c shows a change when the refractive index of the silicon nitride film 7 is 2.0, which is the same as that of the silicon nitride film 8. As is clear from this result, in the present example, the change over time in the breakdown withstand voltage was significantly reduced as compared with the comparative example. In addition, such an effect is deteriorated in reproducibility when the refractive index of the silicon nitride film 7 is 2.0 or more and 2.1 or less.
【００１４】以上の実施例では、本発明をＦＥＴに応用
したが、ダイオード、ＬＥＤなどに利用することも可能
である。また、屈折率が２．２以上の窒化シリコン膜７
を被覆する窒化シリコン膜８の代わりに他の緻密な絶縁
膜を用いることもできる。Although the present invention is applied to the FET in the above embodiments, the present invention can be applied to a diode, an LED and the like. Further, the silicon nitride film 7 having a refractive index of 2.2 or more
Instead of the silicon nitride film 8 covering the film, another dense insulating film can be used.
【００１５】[0015]
【発明の効果】本発明による半導体装置は、化合物半導
体と、該化合物半導体の表面に形成された複数の電極
と、該複数の電極間における前記化合物半導体の表面を
被覆する屈折率２．２以上の窒化シリコン膜と、該窒化
シリコン膜を被覆する絶縁膜とを有することを要旨とす
るものである。The semiconductor device according to the present invention has a compound semiconductor, a plurality of electrodes formed on the surface of the compound semiconductor, and a refractive index of 2.2 or more for covering the surface of the compound semiconductor between the plurality of electrodes. The gist of the present invention is to have the silicon nitride film and the insulating film that covers the silicon nitride film.
【００１６】本発明により、化合物半導体と屈折率２．
２以上の窒化シリコン膜との界面が比較的安定となり、
電極間の不要な電流が低減できる。同時に該窒化シリコ
ン膜を被覆する絶縁膜により化合物半導体の十分な保護
が可能となる。したがって、半導体装置の信頼性を著し
く向上することができる。According to the present invention, a compound semiconductor and a refractive index of 2.
The interface with two or more silicon nitride films becomes relatively stable,
Unnecessary current between the electrodes can be reduced. At the same time, the insulating film covering the silicon nitride film enables sufficient protection of the compound semiconductor. Therefore, the reliability of the semiconductor device can be significantly improved.
【図１】本発明の一実施例であるＦＥＴを説明するため
の断面図。FIG. 1 is a cross-sectional view for explaining an FET that is an embodiment of the present invention.
【図２】窒化シリコン膜の屈折率と原料ガスの組成比
（Ｓｉ／Ｎ比）の関係を示す図。FIG. 2 is a diagram showing a relationship between a refractive index of a silicon nitride film and a composition ratio (Si / N ratio) of source gas.
【図３】加速試験によるブレークダウン耐圧の経時変化
を示す図。FIG. 3 is a diagram showing a change in breakdown withstand voltage over time by an acceleration test.
１ ‥‥ ＧａＡｓ基板 ２ ‥‥ ノンドープＧａＡｓ層 ３ ‥‥ ｎ型ＧａＡｓ層 ４、５‥ オーミック電極 ６ ‥‥ ショットキー電極 ７ ‥‥ 屈折率２．２以上の窒化シリコン膜 ８ ‥‥ 屈折率２．０の窒化シリコン膜（絶縁膜） 1 GaAs substrate 2 Undoped GaAs layer 3 n-type GaAs layer 4, 5 Ohmic electrode 6 Schottky electrode 7 Silicon nitride film with a refractive index of 2.2 or more 8 Refractive index 2. 0 silicon nitride film (insulating film)
Claims (2)
する屈折率２．２以上の窒化シリコン膜と、 該窒化シリコン膜を被覆する絶縁膜とを有することを特
徴とする半導体装置。1. A compound semiconductor, a plurality of electrodes formed on the surface of the compound semiconductor, a silicon nitride film having a refractive index of 2.2 or more and covering the surface of the compound semiconductor between the plurality of electrodes, A semiconductor device comprising: an insulating film covering a silicon nitride film.
リコンからなることを特徴とする請求項１記載の半導体
装置。2. The semiconductor device according to claim 1, wherein the insulating film is made of silicon nitride having a refractive index of less than 2.2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3242415A JPH0555207A (en) | 1991-08-29 | 1991-08-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3242415A JPH0555207A (en) | 1991-08-29 | 1991-08-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0555207A true JPH0555207A (en) | 1993-03-05 |
Family
ID=17088783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3242415A Pending JPH0555207A (en) | 1991-08-29 | 1991-08-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0555207A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005005280A (en) * | 2002-05-21 | 2005-01-06 | Otb Group Bv | Method for passivating semiconductor substrate |
| JP2008205392A (en) * | 2007-02-22 | 2008-09-04 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP2010232452A (en) * | 2009-03-27 | 2010-10-14 | Fujitsu Ltd | Compound semiconductor device and method of manufacturing the same |
| JP2010238982A (en) * | 2009-03-31 | 2010-10-21 | Fujitsu Ltd | Compound semiconductor device, and method of manufacturing the same |
-
1991
- 1991-08-29 JP JP3242415A patent/JPH0555207A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005005280A (en) * | 2002-05-21 | 2005-01-06 | Otb Group Bv | Method for passivating semiconductor substrate |
| JP2008205392A (en) * | 2007-02-22 | 2008-09-04 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| US8587092B2 (en) | 2007-02-22 | 2013-11-19 | Fujitsu Limited | Semiconductor device and manufacturing method of the same |
| US8980768B2 (en) | 2007-02-22 | 2015-03-17 | Fujitsu Limited | Semiconductor device and manufacturing method of the same |
| JP2010232452A (en) * | 2009-03-27 | 2010-10-14 | Fujitsu Ltd | Compound semiconductor device and method of manufacturing the same |
| JP2010238982A (en) * | 2009-03-31 | 2010-10-21 | Fujitsu Ltd | Compound semiconductor device, and method of manufacturing the same |
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