JPH0554298B2 - - Google Patents
Info
- Publication number
- JPH0554298B2 JPH0554298B2 JP58048250A JP4825083A JPH0554298B2 JP H0554298 B2 JPH0554298 B2 JP H0554298B2 JP 58048250 A JP58048250 A JP 58048250A JP 4825083 A JP4825083 A JP 4825083A JP H0554298 B2 JPH0554298 B2 JP H0554298B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- voltage
- value
- converter
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 2
- 238000011069 regeneration method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
- H04L27/06—Demodulator circuits; Receiver circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/067—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Manipulation Of Pulses (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Dc Digital Transmission (AREA)
Description
【発明の詳細な説明】
本発明は直流電圧制御回路、特に直流交振幅変
調波の復調装置等で位相検波後の復調信号を識別
再生する回路に用いられ、ドリフト等による直流
成分の変動を補償する直流電圧制御回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention is used in a DC voltage control circuit, particularly in a circuit that identifies and reproduces a demodulated signal after phase detection in a DC/AC amplitude modulated wave demodulator, etc., and compensates for fluctuations in DC components due to drift, etc. This invention relates to a DC voltage control circuit.
近年、マイクロ波などの搬送波を用いてデイジ
タル信号を伝送する場合、16値直交振幅変調（16
値QAMと略記）のような多値直交振幅変調方式
が、周波数帯域を有効に使用できる高能率な変調
方式として注目され、その開発が進められてい
る。このような高能率伝送方式を実現するうえ
で、各装置の回路各部で発生する不完全性は極力
除去する必要があり、復調装置の識別再生回路入
力に含まれる直流ドリフトもその一つである。 In recent years, when transmitting digital signals using carrier waves such as microwaves, 16-level quadrature amplitude modulation (16
Multilevel quadrature amplitude modulation (abbreviated as QAM) has attracted attention as a highly efficient modulation method that can effectively use frequency bands, and its development is progressing. In order to realize such a highly efficient transmission system, it is necessary to eliminate as much as possible the imperfections that occur in each part of the circuit of each device, and one of these is the DC drift included in the input of the identification and regeneration circuit of the demodulator. .
この直流ドリフト成分を補償する効果的で量産
にも適した回路が、特願昭56−200047号明細書に
提案されている。この回路は、位相検波された多
値復調信号の識別再生を行うアナログ・デイジタ
ル変換器（以下Ａ／Ｄ変換器と称す）の誤差出力
で入力側に重畳される直流電圧を制御するもの
で、連続運用時には良好に動作するが、後述する
ように一度入力信号が切れた後、再び入力が回復
した場合、その初期状態によつては異常引込みを
起こして誤つた直流値に制御される恐れがあり、
正常動作に復帰しないという欠点がある。 A circuit that is effective and suitable for mass production for compensating for this DC drift component is proposed in Japanese Patent Application No. 56-200047. This circuit controls the DC voltage that is superimposed on the input side with the error output of an analog-to-digital converter (hereinafter referred to as A/D converter) that performs discrimination and reproduction of a phase-detected multilevel demodulated signal. It works well during continuous operation, but as will be explained later, if the input signal is cut off and then restored again, depending on the initial state, there is a risk of abnormal pull-in and control to an incorrect DC value. can be,
The drawback is that normal operation cannot be restored.
本発明の目的は、上述の欠点を除去し、異常引
込みを起こさず、常に正常動作に復帰する直流電
圧制御回路を提供することである。 An object of the present invention is to provide a DC voltage control circuit that eliminates the above-mentioned drawbacks, does not cause abnormal pull-in, and always returns to normal operation.
本発明の直流電圧制御回路は、2n値（ｎは正の
整数）入力信号に直流制御電圧を逆極性で重畳し
て直流レベルが重畳された信号を出力する直流重
畳器と、前記直流レベルが重畳された信号を（ｎ
＋１）ビツトでアナログ・デイジタル変換し、上
位ｎビツトを再生出力信号として出力し、最上位
からｎ＋１番目を１ビツトの誤差信号として出力
するアナログ・デイジタル変換器と、前記誤差信
号を平滑して直流信号を生成する制御信号発生器
と、前記直流レベルの絶対値が一定値以下となる
ように前記直流信号を制限して前記直流制御電圧
を出力する制限器であり、前記一定値は前記（ｎ
＋１）ビツトのＡ／Ｄ変換器の2n+1−１個の闘値
の間隔の1/2以下である制限器とを備えて構成さ
れる。 The DC voltage control circuit of the present invention includes a DC superimposition device that superimposes a DC control voltage with opposite polarity on a 2 n value (n is a positive integer) input signal and outputs a signal with a DC level superimposed thereon; The signal on which is superimposed is (n
+1) An analog-to-digital converter that performs analog-to-digital conversion in bits, outputs the upper n bits as a reproduced output signal, and outputs the (n+1)th from the most significant as a 1-bit error signal, and smoothes the error signal and converts it into a DC signal. a control signal generator that generates a signal, and a limiter that limits the DC signal and outputs the DC control voltage so that the absolute value of the DC level is below a certain value, and the constant value is the (n
+1) a limiter whose interval is less than 1/2 of the interval between 2 n+1 -1 threshold values of the 2 n+1 -1 bit A/D converter.
次に図面を参照して本発明を詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図は特願昭56−200047号明細書記載の復調
装置のブロツク図であり、自動利得制御機能を有
する中間周波増幅器１と、その出力の16値QAM
波を復調し２列の４値デイジタル信号１００を出
力する復調器２と、その出力にそれぞれ直流電圧
を重畳する減算器３と、減算器３の出力を８値識
別して２ビツトの再生出力信号X1，X2及び１ビ
ツトの誤差信号X3を出力するＡ／Ｄ変換器４と、
誤差信号X3から低域フイルタにより高周波成分
を抑圧して制御用の直流電圧１０１を発生する制
御信号発生器５とから成つている。このブロツク
図において、減算器３，Ａ／Ｄ変換器４及び制御
信号発生器５は、Ａ／Ｄ変換器４が最適動作条件
で信号識別が行えるよう復調信号に含まれる直流
分を制御する直流電圧制御回路を構成している。
第２図は上述の直流電圧制御回路の動作を説明す
るためのＡ／Ｄ変換器の識別領域図で、Ａ／Ｄ変
換器の入力電圧（縦軸Ｖ）は３つの信号識別値Ｖ
＝０，Ｖ＝±2dと４つの誤差識別値Ｖ＝±ｄ，
Ｖ＝±3dとによつて８つの誤差領域+，-，
+，-，+，-，+，-に分割されてい
る。Ａ／Ｄ変換器４はその入力信号１０２が上述
のどの領域にあるかによつて、図に示す２値信号
X1，X2，X3を送出するように構成されている。
第１図の回路が最適動作状態にあるときは、入力
信号１０２の４つの信号レベルは各誤差識別値と
一致しA1〜A4で示される。入力の信号レベルが
直流ドリフトによつてこの値から（＋）方向に
ΔV変化してA1′〜A4′となると、誤差信号X3は
どの信号レベルに対してもすべて”１”となつて
制御信号発生器５の直流電圧１０１が増加する。
従つて、減算器３の出力１０２は（−）方向に変
化し、A1′〜A4′は矢印αの方向に制御される。
逆に入力信号レベルが直流ドリフトにより破線で
示すように（−）方向に変化すると、誤差信号
X3はすべて”０”となつて直流出力１０１が減
少し、減算器３の出力は（＋）方向に制御され
る。すなわち、復調器やベースベンド増幅器の直
流ドリフト等によつて入力信号１００の直流分が
変動しても、Ａ／Ｄ変換器４の入力１０２は常に
最適の動作状態A1〜A4となるように制御される。 FIG. 1 is a block diagram of the demodulator described in the specification of Japanese Patent Application No. 56-200047, which includes an intermediate frequency amplifier 1 having an automatic gain control function and a 16-value QAM of its output.
A demodulator 2 demodulates the wave and outputs two rows of four-value digital signals 100, a subtracter 3 superimposes a DC voltage on each output, and the output of the subtracter 3 is identified by eight values and output as a 2-bit reproduction output. an A/D converter 4 that outputs signals X 1 , X 2 and a 1-bit error signal X 3 ;
The control signal generator 5 generates a control DC voltage 101 by suppressing high frequency components from the error signal X 3 using a low-pass filter. In this block diagram, a subtracter 3, an A/D converter 4, and a control signal generator 5 are used to control the DC component included in the demodulated signal so that the A/D converter 4 can perform signal identification under optimal operating conditions. It constitutes a voltage control circuit.
FIG. 2 is a discrimination area diagram of the A/D converter for explaining the operation of the above-mentioned DC voltage control circuit, and the input voltage of the A/D converter (vertical axis V) is determined by three signal discrimination values
=0, V=±2d and four error identification values V=±d,
V=±3d and 8 error regions + , - ,
It is divided into + , - , + , - , + , - . The A/D converter 4 outputs the binary signal shown in the figure depending on which region the input signal 102 is in.
It is configured to send out X 1 , X 2 , and X 3 .
When the circuit of FIG. 1 is in optimal operating conditions, the four signal levels of input signal 102 correspond to respective error discrimination values and are designated A 1 -A 4 . When the input signal level changes by ΔV from this value in the (+) direction due to DC drift and becomes A 1 ′ to A 4 ′, the error signal X 3 becomes “1” regardless of the signal level. As a result, the DC voltage 101 of the control signal generator 5 increases.
Therefore, the output 102 of the subtracter 3 changes in the (-) direction, and A 1 ' to A 4 ' are controlled in the direction of the arrow α.
Conversely, when the input signal level changes in the (-) direction as shown by the broken line due to DC drift, the error signal
All X3 becomes "0", the DC output 101 decreases, and the output of the subtracter 3 is controlled in the (+) direction. In other words, even if the DC component of the input signal 100 fluctuates due to DC drift of the demodulator or base bend amplifier, the input 102 of the A/D converter 4 is always in the optimal operating state A 1 to A 4 . controlled by.
しかしながら、上述の従来方法では、入力信号
が一度断となつて再び印加された場合、初期状態
の直流分の偏移ΔV′が大きく、第２図B1〜B4の
ごとく識別値間隔ｄを越えてΔV′＞ｄとなると、
B1に対する誤差信号X3は”１”となるが、B2〜
B4に対する誤差信号X3はすべて”０”となつ
て、”０”出力の方が多くなるので制御信号発生
器５の直流出力１０１は減少し、減算器３の出力
は（＋）方向に制御され、B1〜B4は矢印γで示
す正常な制御方向とは反対の矢印β方向に制御さ
れ、B2→A1，B3→A2，B4→A3となつて異常引
込み現象が発生する。逆に直流分の偏移−ΔV′が
負側に大きくずれて−ｄを越えてB1′〜B4′とな
つた場合は、誤差信号X3は”１”出力が多くな
つてB1′〜B4′は正常な制御方法（矢印γ′）と逆
に矢印β′方向に制御されて異常引込みを生じ、信
号が正しく再生されず誤りが発生することとな
る。 However, in the conventional method described above, when the input signal is once interrupted and then applied again, the deviation ΔV' of the DC component in the initial state is large, and the discrimination value interval d is changed as shown in Fig. 2 B1 to B4 . When it exceeds ΔV′>d,
The error signal X 3 for B 1 is “1”, but B 2 ~
All error signals X 3 for B 4 become "0" and the number of "0" outputs increases, so the DC output 101 of the control signal generator 5 decreases and the output of the subtractor 3 moves in the (+) direction. B 1 to B 4 are controlled in the direction of arrow β, which is opposite to the normal control direction shown by arrow γ, and abnormal retraction occurs as B 2 →A 1 , B 3 →A 2 , B 4 →A 3 A phenomenon occurs. Conversely, if the DC component deviation -ΔV' largely deviates to the negative side and exceeds -d and becomes B 1 ' to B 4 ', the error signal ' to B 4 ' are controlled in the direction of arrow β', contrary to the normal control method (arrow γ'), resulting in abnormal pull-in, and the signal is not reproduced correctly and an error occurs.
上述の異常引込みを起こす初期状態は次のよう
な場合に発生すると考えられる。すなわち、４値
入力信号が断となると、その直後にＡ／Ｄ変換器
４の入力１０２はほぼ零電位となる。この時実際
には電源あるいは回路自体の雑音を受けて完全に
零電位ではなく、正あるいは負に若干ずれてい
る。正側にずれているとＡ／Ｄ変換器４の入力１
０２は制御ループによつて直流電圧１０１が重畳
されてA2に制御される。反対に入力１０２が負
側にずれているとA3に制御される。いま、A2に
制御されている状態で正負対称な４値の信号が入
力されると、その直後の４値信号は第２図におい
て＋4d，＋2d，０，−2d，に位置する。この時厳
密にその値ではなく、先に説明したように実際に
は雑音が重畳されており若干正または負にずれる
ことになる。この場合、負側にずれていると
A1′〜A4′となり正常引込みをするが、逆に正側
にずれていればB1〜B4となり異常引込みが発生
する。従つて、異常引込みは1/2の確率で発生す
る。従つて、異常引込みを防止する一つの方法
は、このような初期状態が発生しないように、減
算器３に加えられる直流電圧の範囲を制限し、直
流分がA2又はA3に達しないようにすることであ
る。 The initial state that causes the above-mentioned abnormal retraction is thought to occur in the following cases. That is, when the four-value input signal is cut off, immediately after that, the input 102 of the A/D converter 4 becomes almost zero potential. At this time, in reality, due to noise from the power supply or the circuit itself, the potential is not completely zero, but is slightly shifted to positive or negative. If it is shifted to the positive side, input 1 of A/D converter 4
02 is controlled to A 2 by superimposing the DC voltage 101 by the control loop. On the other hand, if the input 102 is shifted to the negative side, it is controlled to A3 . Now, when a 4-value signal with positive and negative symmetry is input under the control of A2 , the 4-value signal immediately after that is located at +4d, +2d, 0, and -2d in FIG. At this time, it is not strictly that value, but as explained earlier, noise is actually superimposed on it, so it will shift slightly to positive or negative. In this case, if it deviates to the negative side,
A 1 ' to A 4 ' and normal retraction occurs, but if it deviates to the positive side, B 1 to B 4 and abnormal retraction occurs. Therefore, abnormal entrainment occurs with a probability of 1/2. Therefore, one method for preventing abnormal pull-in is to limit the range of the DC voltage applied to the subtracter 3 so that such an initial state does not occur, and to prevent the DC component from reaching A 2 or A 3 . It is to do so.
第３図は上述の考えによる本発明の一実施例の
ブロツク図で、第１図と同様な減算器３，Ａ／Ｄ
変換器４、制御信号発生器５と、制御信号発生器
５の出力電圧範囲を制限する制限器６とから成
り、減算器３に重畳される直流電圧１０３の範囲
が±ｄ以内のあらかじめ定められた値±Ｌ第２図
に示すに制限されるように構成されている。従つ
て、入力が断となつて減算器３の入力１００が零
電位となつてもＡ／Ｄ変換器４の入力１０２は±
Ｌ又は−Ｌとなる。４値入力信号の直流分変動を
含む予想される最大の直流ドリフトを±Ｄとし
て、ｄ＞（Ｄ＋Ｌ）となるようにＬの値を選定し
ておけば、異常引込みを起こすような初期条件は
発生しないこととなる。制限器６は公知の方法で
簡単な回路により実現することができるので、そ
の出力範囲を正負それぞれ識別値間隔ｄ以下の上
述の条件を満たす値に制限すれば、異常引込みの
ない直流電圧制御回路を容易に実現することがで
きる。直流ドリフト成分±Ｄは正常動作時には重
畳される直流電圧１０３によつて補償されなけれ
ばならないので、当然ＬＤである必要があるか
ら、補償できる直流ドリフトの範囲を大きくする
ためにはＤ＝ＬとしてＤ＞ｄ／２となる。すなわ
ち、補償可能な直流ドリフトの許容範囲は正負そ
れぞれ識別値間隔の1/2より小さくなるが、予想
される直流ずれの大きさは一般的に識別幅より小
さいから、本願発明は実用上十分な効果を得るこ
とができる。 FIG. 3 is a block diagram of an embodiment of the present invention based on the above idea, in which a subtracter 3 and an A/D similar to those in FIG.
It consists of a converter 4, a control signal generator 5, and a limiter 6 that limits the output voltage range of the control signal generator 5. It is configured such that the value ±L shown in FIG. 2 is limited. Therefore, even if the input is cut off and the input 100 of the subtracter 3 becomes zero potential, the input 102 of the A/D converter 4 will be at ±
It becomes L or -L. If the expected maximum DC drift including the DC component fluctuation of the 4-value input signal is ±D, and the value of L is selected so that d>(D+L), the initial conditions that cause abnormal pull-in can be eliminated. This will not occur. Since the limiter 6 can be realized by a simple circuit using a known method, if the output range of the limiter 6 is limited to a value that satisfies the above-mentioned conditions below the discrimination value interval d for positive and negative values, a DC voltage control circuit that does not cause abnormal pull-in can be realized. can be easily realized. Since the DC drift component ±D must be compensated by the DC voltage 103 that is superimposed during normal operation, it naturally needs to be LD, so in order to widen the range of DC drift that can be compensated for, set D=L. D>d/2. That is, although the allowable range of DC drift that can be compensated for is smaller than 1/2 of the discrimination value interval for both positive and negative values, the expected magnitude of DC drift is generally smaller than the discrimination width, so the present invention is practically sufficient. effect can be obtained.
上述の説明では直流電圧を重畳するのに減算器
を用いているが、減算器の代りに加算器を用いて
も重畳する直流電圧の極性を反転すればよいこと
は言うまでもなく、又、正負対称な４値信号につ
いて説明したが４値以外の多値信号に対しても本
発明の技術思想は適用することができ、正負対称
な信号に限定されないことも明らかである。 In the above explanation, a subtracter is used to superimpose the DC voltage, but it goes without saying that an adder can be used instead of a subtracter as long as the polarity of the DC voltage to be superimposed can be reversed. Although a four-value signal has been described, it is clear that the technical idea of the present invention can also be applied to multi-value signals other than four-value signals, and is not limited to signals that are symmetrical in sign and negative.
以上詳細に説明したように、本発明の直流電圧
制御回路によれば、復調装置等に用いられ、異常
引込み現象の発生しない多値信号識別再生回路が
実現できる効果がある。 As described above in detail, the DC voltage control circuit of the present invention has the effect of realizing a multi-level signal identification and regeneration circuit that is used in demodulators and the like and does not cause abnormal pull-in phenomena.
第１図は従来の復調装置のブロツク図、第２図
はＡ／Ｄ変換器の識別領域図、第３図は本発明の
一実施例のブロツク図である。
１……中間周波増幅器、２……復調器、３……
減算器、４……Ａ／Ｄ変換器、５……制御信号発
生器、６……制限器。
FIG. 1 is a block diagram of a conventional demodulator, FIG. 2 is a diagram of an identification area of an A/D converter, and FIG. 3 is a block diagram of an embodiment of the present invention. 1... Intermediate frequency amplifier, 2... Demodulator, 3...
Subtractor, 4... A/D converter, 5... Control signal generator, 6... Limiter.
Claims (1)
大変動分が信号識別値間隔の1/4以下である直流
成分の変動分を補償する直流電圧制御回路におい
て、 入力信号に直流制御電圧を逆極性で重畳して直
流レベルが重畳された信号を出力する直流重畳器
と、 前記直流レベルが重畳された信号を（ｎ＋１）
ビツトでアナログ・デイジタル変換し、上位ｎビ
ツトを再生出力信号として出力し、最上位からｎ
＋１番目を１ビツトの誤差信号として出力するア
ナログ・デイジタル変換器と、 前記誤差信号を平滑して直流信号を生成する制
御信号発生器と、 前記直流レベルの絶対値が一定値以下となるよ
うに前記直流信号を制限して前記直流制御電圧を
出力する制限器であり、前記一定値は前記（ｎ＋
１）ビツトのＡ／Ｄ変換器の2n+1−１個の闘値の
間隔の1/2以下である制限器とを備えることを特
徴とする直流電圧制御回路。[Claims] In a DC voltage control circuit that compensates for fluctuations in a DC component in which the maximum fluctuation included in a 12 n- value (n is a positive integer) input signal is 1/4 or less of the signal identification value interval. , a DC superimposition device that superimposes a DC control voltage on an input signal with a reverse polarity and outputs a signal with a DC level superimposed thereon;
Analog-to-digital conversion is performed in bits, and the upper n bits are output as a playback output signal.
an analog-to-digital converter that outputs the +1st signal as a 1-bit error signal; a control signal generator that smooths the error signal to generate a DC signal; It is a limiter that limits the DC signal and outputs the DC control voltage, and the constant value is the (n+
1) A DC voltage control circuit comprising a limiter whose interval is less than 1/2 of the interval between 2 n+1 -1 threshold values of a bit A/D converter.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58048250A JPS59174059A (en) | 1983-03-23 | 1983-03-23 | Dc voltage control circuit |
| US06/591,752 US4544894A (en) | 1983-03-23 | 1984-03-21 | DC Voltage control circuits |
| CA000450157A CA1208708A (en) | 1983-03-23 | 1984-03-21 | Dc voltage control circuits |
| DE8484103181T DE3468800D1 (en) | 1983-03-23 | 1984-03-22 | Dc voltage control circuits |
| AU25994/84A AU557008B2 (en) | 1983-03-23 | 1984-03-22 | Demodulation control |
| EP84103181A EP0120474B1 (en) | 1983-03-23 | 1984-03-22 | Dc voltage control circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58048250A JPS59174059A (en) | 1983-03-23 | 1983-03-23 | Dc voltage control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59174059A JPS59174059A (en) | 1984-10-02 |
| JPH0554298B2 true JPH0554298B2 (en) | 1993-08-12 |
Family
ID=12798188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58048250A Granted JPS59174059A (en) | 1983-03-23 | 1983-03-23 | Dc voltage control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59174059A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61184023A (en) * | 1985-02-08 | 1986-08-16 | Nec Corp | Dc voltage control circuit |
| JP5172773B2 (en) * | 2009-04-27 | 2013-03-27 | 日本電信電話株式会社 | Signal detection apparatus, method, program, and recording medium thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58120351A (en) * | 1982-01-13 | 1983-07-18 | Fujitsu Ltd | Compensating system for direct current shift |
-
1983
- 1983-03-23 JP JP58048250A patent/JPS59174059A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58120351A (en) * | 1982-01-13 | 1983-07-18 | Fujitsu Ltd | Compensating system for direct current shift |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59174059A (en) | 1984-10-02 |
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