JPH0548102A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPH0548102A JPH0548102A JP23111191A JP23111191A JPH0548102A JP H0548102 A JPH0548102 A JP H0548102A JP 23111191 A JP23111191 A JP 23111191A JP 23111191 A JP23111191 A JP 23111191A JP H0548102 A JPH0548102 A JP H0548102A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- insulating film
- gate
- film
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は薄膜トランジスタの製造
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.
【０００２】[0002]
【従来の技術】薄膜トランジスタは、例えばアクティブ
マトリックス液晶表示素子の能動素子等に用いられてい
る。2. Description of the Related Art Thin film transistors are used, for example, as active elements of active matrix liquid crystal display elements.
【０００３】この薄膜トランジスタは、ガラス等からな
る絶縁性基板の上にゲート電極を形成し、その上にゲー
ト絶縁膜を形成するとともに、このゲート絶縁膜の上に
半導体層およびソース，ドレイン電極を形成する方法で
製造されている。In this thin film transistor, a gate electrode is formed on an insulating substrate made of glass or the like, a gate insulating film is formed thereon, and a semiconductor layer and source / drain electrodes are formed on this gate insulating film. Is manufactured by the method.
【０００４】[0004]
【発明が解決しようとする課題】ところで、上記薄膜ト
ランジスタのゲート絶縁膜は、一般にプラズマＣＶＤ法
によって成膜されているが、この場合、基板上にはゲー
ト電極が形成されているため、基板上へのゲート絶縁膜
の成膜に際して、その堆積厚さが基板とゲート電極との
間の段差部において極端に薄くなり、そのため、ゲート
電極の側縁付近におけるゲート絶縁膜の絶縁耐圧が悪く
なって、ゲート電極とソース，ドレイン電極との間に短
絡を発生するおそれがある。By the way, the gate insulating film of the above-mentioned thin film transistor is generally formed by the plasma CVD method. In this case, however, since the gate electrode is formed on the substrate, the gate insulating film is formed on the substrate. When the gate insulating film is formed, the deposited thickness becomes extremely thin in the step portion between the substrate and the gate electrode, so that the withstand voltage of the gate insulating film near the side edge of the gate electrode deteriorates, A short circuit may occur between the gate electrode and the source / drain electrodes.
【０００５】本発明の目的は、基板上にゲート電極を形
成した後のゲート絶縁膜の成膜に際してこのゲート絶縁
膜を均一な厚さに堆積させ、ゲート電極の側縁付近にお
けるゲート絶縁膜の絶縁耐圧も十分に確保して、ゲート
電極とソース，ドレイン電極との間の短絡発生を確実に
防ぐことができる薄膜トランジスタの製造方法を提供す
ることにある。An object of the present invention is to deposit the gate insulating film to a uniform thickness when forming the gate insulating film after forming the gate electrode on the substrate, and to form the gate insulating film near the side edges of the gate electrode. It is an object of the present invention to provide a method for manufacturing a thin film transistor, which can sufficiently secure the dielectric strength and can surely prevent a short circuit from occurring between the gate electrode and the source / drain electrodes.
【０００６】[0006]
【課題を解決するための手段】本発明の薄膜トランジス
タの製造方法は、絶縁性基板上にゲート電極形成領域を
除いて下地絶縁膜を形成した後、前記基板のゲート電極
形成領域の上に金属をメッキして前記下地絶縁膜の膜厚
より薄い厚さのゲート電極を形成するとともに、前記ゲ
ート電極の上面を陽極酸化して、このゲート電極の上
に、表面が前記下地絶縁膜の表面と面一になる厚さに酸
化絶縁層を生成させ、この後、前記酸化絶縁層および前
記下地絶縁膜の上にゲート絶縁膜を成膜し、その上に半
導体層およびソース，ドレイン電極を形成することを特
徴とするものである。According to a method of manufacturing a thin film transistor of the present invention, a base insulating film is formed on an insulating substrate except a gate electrode forming region, and then a metal is formed on the gate electrode forming region of the substrate. A gate electrode having a thickness smaller than that of the base insulating film is formed by plating, and the upper surface of the gate electrode is anodized, and the surface of the gate electrode is on the surface of the base insulating film. Forming an oxide insulating layer having a uniform thickness, forming a gate insulating film on the oxide insulating layer and the underlying insulating film, and forming a semiconductor layer and source / drain electrodes on the gate insulating film; It is characterized by.
【０００７】[0007]
【作用】すなわち、本発明は、基板上にゲート電極形成
領域を除いて下地絶縁膜を形成しておき、前記基板のゲ
ート電極形成領域の上に金属をメッキして形成したゲー
ト電極の上面を陽極酸化して酸化絶縁層を生成させるこ
とにより、ゲート電極の表面（酸化絶縁層の表面）を前
記下地絶縁膜の表面と面一にして、その上にゲート絶縁
膜を成膜するものであり、前記ゲート電極の上面を酸化
させると、このゲート電極の酸化領域の体積が増大して
酸化絶縁層を含むゲート電極の膜厚が厚くなるため、上
記ゲート電極を下地絶縁膜の膜厚より薄くメッキし、こ
のゲート電極の上面を、生成する酸化絶縁層の表面が下
地絶縁膜の表面と面一になるまで陽極酸化してやれば、
この後に成膜するゲート絶縁膜の成膜面が段差のない平
坦面になる。That is, according to the present invention, the base insulating film is formed on the substrate except the gate electrode forming region, and the upper surface of the gate electrode formed by plating metal on the gate electrode forming region of the substrate is formed. By forming an oxide insulating layer by anodizing, the surface of the gate electrode (the surface of the oxide insulating layer) is flush with the surface of the base insulating film, and the gate insulating film is formed thereon. When the upper surface of the gate electrode is oxidized, the volume of the oxidized region of the gate electrode increases and the thickness of the gate electrode including the oxide insulating layer increases, so that the gate electrode is thinner than the underlying insulating film. If plating is performed and the upper surface of this gate electrode is anodized until the surface of the resulting oxide insulating layer is flush with the surface of the underlying insulating film,
The film forming surface of the gate insulating film to be formed thereafter becomes a flat surface without steps.
【０００８】そして、このようにゲート絶縁膜の成膜面
が段差のない平坦面であれば、ゲート絶縁膜の成膜に際
して、このゲート絶縁膜が均一な厚さに堆積するため、
ゲート電極の側縁付近におけるゲート絶縁膜の絶縁耐圧
も十分である。If the surface on which the gate insulating film is formed is a flat surface without steps, the gate insulating film is deposited to a uniform thickness when forming the gate insulating film.
The withstand voltage of the gate insulating film near the side edge of the gate electrode is also sufficient.
【０００９】しかも、本発明によれば、ゲート電極の上
の絶縁層が、ゲート電極の上に生成させた酸化絶縁層
と、その上に成膜したゲート絶縁膜との二層膜になるた
め、ゲート電極とソース，ドレイン電極との間の絶縁耐
圧はさらに高くなる。Further, according to the present invention, the insulating layer on the gate electrode is a two-layer film including the oxide insulating layer formed on the gate electrode and the gate insulating film formed on the oxide insulating layer. The withstand voltage between the gate electrode and the source / drain electrodes is further increased.
【００１０】[0010]
【実施例】以下、本発明の一実施例を、アクティブマト
リックス液晶表示素子の能動素子である薄膜トランジス
タの製造を例にとって説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below by taking as an example the manufacture of a thin film transistor which is an active element of an active matrix liquid crystal display element.
【００１１】図１は薄膜トランジスタの製造工程図であ
り、ここでは逆スタガー型と呼ばれる薄膜トランジスタ
の製造工程を示している。この薄膜トランジスタは次の
ようにして製造する。FIG. 1 is a manufacturing process diagram of a thin film transistor, showing a manufacturing process of a thin film transistor called an inverted stagger type here. This thin film transistor is manufactured as follows.
【００１２】［工程１］まず、図１（ａ）に示すよう
に、ガラス等からなる透明な絶縁性基板１上のほぼ全面
に、Ｓi Ｎ（窒化シリコン）からなる下地絶縁膜２をプ
ラズマＣＶＤ法によって成膜する。この下地絶縁膜２
は、基板１上に形成するゲート電極の厚さより十分厚い
膜厚（例えば約５００ｎｍ）に成膜する。[Step 1] First, as shown in FIG. 1A, a base insulating film 2 made of Si N (silicon nitride) is plasma-enhanced on almost the entire surface of a transparent insulating substrate 1 made of glass or the like. The film is formed by the method. This base insulating film 2
Is formed with a film thickness (for example, about 500 nm) sufficiently thicker than the thickness of the gate electrode formed on the substrate 1.
【００１３】［工程２］次に、図１（ｂ）に示すよう
に、下地絶縁膜２の上に、ゲート電極形成領域（ゲート
電極およびその配線部の形成領域）Ａを除いて下地絶縁
膜２の表面全体を覆うレジストマスクＭを形成し、上記
下地絶縁膜２のゲート電極形成領域Ａ上の部分をエッチ
ングして除去する。[Step 2] Next, as shown in FIG. 1B, the base insulating film is formed on the base insulating film 2 except for the gate electrode formation region (the formation region of the gate electrode and its wiring portion) A. A resist mask M covering the entire surface of 2 is formed, and the portion of the base insulating film 2 on the gate electrode formation region A is etched and removed.
【００１４】［工程３］次に、図１（ｃ）に示すよう
に、下地絶縁膜２の上のレジストマスクＭを残したま
ま、基板１のゲート電極形成領域Ａの上にＣr 等の金属
を無電界メッキによってメッキし、基板１上にゲート電
極３およびその配線部を下地絶縁膜２の膜厚（約５００
ｎｍ）より若干薄い厚さ（約４００ｎｍ）に形成する。[Step 3] Next, as shown in FIG. 1C, a metal such as Cr is formed on the gate electrode forming region A of the substrate 1 while leaving the resist mask M on the underlying insulating film 2. Are plated by electroless plating, and the gate electrode 3 and its wiring portion are formed on the substrate 1 by the film thickness of the base insulating film 2 (about 500
nm) and a thickness (about 400 nm).
【００１５】［工程４］次に、上記ゲート電極３および
その配線部（以下、配線部も含めてゲート電極という）
の上面を陽極酸化し、図１（ｄ）に示すように、ゲート
電極３の上に酸化絶縁層３ａを生成させる。[Step 4] Next, the gate electrode 3 and its wiring portion (hereinafter, the wiring portion is also referred to as a gate electrode)
1 is anodized to form an oxide insulating layer 3a on the gate electrode 3 as shown in FIG.
【００１６】このゲート電極３の陽極酸化は、その配線
部の端部をクリップ型コネクタ等によって直流電源の陽
極に接続し、基板１を電解液中に浸漬してゲート電極３
を電解液中に配置した対向電極（陰極）と対向させ、ゲ
ート電極３と対向電極との間に電圧を印加して行なう。For the anodic oxidation of the gate electrode 3, the end of the wiring portion is connected to the anode of the DC power source by a clip-type connector or the like, and the substrate 1 is immersed in an electrolytic solution to form the gate electrode 3.
Is opposed to the counter electrode (cathode) arranged in the electrolytic solution, and a voltage is applied between the gate electrode 3 and the counter electrode.
【００１７】このように電解液中においてゲート電極３
と対向電極との間に電圧を印加すると、陽極であるゲー
ト電極３が電解液で化成反応を起してその表面側から陽
極酸化されて行き、これにともなって、ゲート電極３の
酸化領域の体積が増大して酸化絶縁層３ａを含むゲート
電極３の膜厚が厚くなって行く。In this way, in the electrolytic solution, the gate electrode 3
When a voltage is applied between the gate electrode 3 and the counter electrode, the gate electrode 3, which is an anode, undergoes a chemical conversion reaction with the electrolyte solution and is anodized from the surface side thereof. The volume increases, and the film thickness of the gate electrode 3 including the oxide insulating layer 3a increases.
【００１８】このゲート電極３の陽極酸化は、その上に
生成する酸化絶縁層３ａの表面が下地絶縁膜２の表面と
面一になるまで行なう。なお、酸化絶縁層３ａの生成厚
さは、印加電圧によって決まるため、あらかじめ酸化試
験を行なって適正な印加電圧値を求めておき、この値に
印加電圧を制御すれば、ゲート電極３の上に、表面が下
地絶縁膜２の表面と面一になる厚さに酸化絶縁層３ａを
生成させることができる。このように上記ゲート電極３
の上面を陽極酸化してやれば、このゲート電極３の上の
酸化絶縁層３ａの表面と下地絶縁膜２の表面とが段差の
ない平坦面になる。The anodic oxidation of the gate electrode 3 is performed until the surface of the oxide insulating layer 3a formed thereon is flush with the surface of the base insulating film 2. Since the thickness of the oxide insulating layer 3a is determined by the applied voltage, an oxidation test is performed in advance to find an appropriate applied voltage value, and if the applied voltage is controlled to this value, the gate electrode 3 will be covered. The oxide insulating layer 3a can be formed to a thickness such that the surface thereof is flush with the surface of the base insulating film 2. Thus, the gate electrode 3
If the upper surface of the above is anodized, the surface of the oxide insulating layer 3a on the gate electrode 3 and the surface of the base insulating film 2 become a flat surface with no step.
【００１９】［工程５］次に、下地絶縁膜２の上のレジ
ストマスクＭを除去し、この後、図１（ｅ）に示すよう
に、上記酸化絶縁層３ａおよび下地絶縁膜２の上に、Ｓ
i Ｎからなるゲート絶縁膜４を成膜し、その上にａ−Ｓ
i （アモルファスシリコン）からなるｉ型半導体層５を
形成するとともに、このｉ型半導体層５のチャンネル領
域の上にＳi Ｎからなるブロッキング絶縁膜６を形成
し、さらに前記ｉ型半導体層５の両側部の上に、不純物
をドープしたａ−Ｓi からなるｎ型半導体層７を介して
ソース電極８とドレイン電極９およびその配線部を形成
して、薄膜トランジスタを完成する。[Step 5] Next, the resist mask M on the base insulating film 2 is removed, and thereafter, as shown in FIG. 1 (e), the oxide insulating layer 3a and the base insulating film 2 are formed. , S
A gate insulating film 4 made of iN is formed, and aS is formed on the gate insulating film 4.
An i-type semiconductor layer 5 made of i (amorphous silicon) is formed, a blocking insulating film 6 made of Si 2 N is formed on the channel region of the i-type semiconductor layer 5, and both sides of the i-type semiconductor layer 5 are formed. A source electrode 8 and a drain electrode 9 and wiring portions thereof are formed on the portion via an n-type semiconductor layer 7 made of a-Si doped with impurities to complete a thin film transistor.
【００２０】なお、これらは、ゲート絶縁膜４とｉ型半
導体層５とブロッキング絶縁膜６とをプラズマＣＶＤ法
により連続して成膜し、ブロッキング絶縁膜６とｉ型半
導体層５とを順次パターニングした後、ｎ型半導体層７
をプラズマＣＶＤ法により成膜するとともに、その上に
金属膜（例えばＣr 膜等）をスパッタリング法により成
膜し、この金属膜とその下のｎ型半導体層７とをソー
ス，ドレイン電極８，９の形状にパターニングする方法
で形成する。Incidentally, in these, the gate insulating film 4, the i-type semiconductor layer 5 and the blocking insulating film 6 are continuously formed by the plasma CVD method, and the blocking insulating film 6 and the i-type semiconductor layer 5 are sequentially patterned. After that, the n-type semiconductor layer 7
Is formed by a plasma CVD method, and a metal film (for example, a Cr film) is formed thereon by a sputtering method. The metal film and the n-type semiconductor layer 7 thereunder are formed as source and drain electrodes 8 and 9. It is formed by a method of patterning in the shape of.
【００２１】また、図１（ｅ）において、１０は上記ゲ
ート絶縁膜４の上に形成した画素電極であり、この画素
電極１０は上記薄膜トランジスタのソース電極８に接続
されている。なお、この画素電極１０は、ＩＴＯ等の透
明導電膜を成膜し、この透明導電膜をパターニングして
形成する。Further, in FIG. 1 (e), 10 is a pixel electrode formed on the gate insulating film 4, and the pixel electrode 10 is connected to the source electrode 8 of the thin film transistor. The pixel electrode 10 is formed by forming a transparent conductive film such as ITO and patterning the transparent conductive film.
【００２２】上記薄膜トランジスタの製造方法によれ
ば、基板１上にゲート電極３を形成した後のゲート絶縁
膜４の成膜に際して、このゲート絶縁膜４を均一な厚さ
に堆積させることができる。According to the method of manufacturing a thin film transistor, when forming the gate insulating film 4 after forming the gate electrode 3 on the substrate 1, the gate insulating film 4 can be deposited to a uniform thickness.
【００２３】すなわち、上記製造方法は、基板１上にゲ
ート電極形成領域Ａを除いて下地絶縁膜２を形成してお
き、基板１のゲート電極形成領域Ａの上に金属をメッキ
して形成したゲート電極３の上面を陽極酸化して酸化絶
縁層３ａを生成させることにより、ゲート電極の表面
（酸化絶縁層３ａの表面）を前記下地絶縁膜２の表面と
面一にして、その上にゲート絶縁膜４を成膜するもので
あり、前記ゲート電極３の上面を酸化させると、このゲ
ート電極３の酸化領域の体積が増大して酸化絶縁層３ａ
を含むゲート電極３の膜厚が厚くなるため、上記ゲート
電極３を下地絶縁膜２の膜厚より薄くメッキし、このゲ
ート電極３の上面を、生成する酸化絶縁層３ａの表面が
下地絶縁膜２の表面と面一になるまで陽極酸化してやれ
ば、この後に成膜するゲート絶縁膜４の成膜面が段差の
ない平坦面になる。That is, in the above manufacturing method, the base insulating film 2 is formed on the substrate 1 except the gate electrode forming region A, and the gate electrode forming region A of the substrate 1 is plated with a metal. The surface of the gate electrode (the surface of the oxide insulating layer 3a) is made flush with the surface of the base insulating film 2 by anodizing the upper surface of the gate electrode 3 to generate the oxide insulating layer 3a, and the gate is formed on the surface. The insulating film 4 is formed, and when the upper surface of the gate electrode 3 is oxidized, the volume of the oxidized region of the gate electrode 3 increases and the oxide insulating layer 3a is formed.
Since the film thickness of the gate electrode 3 including is thicker than the film thickness of the base insulating film 2, the gate electrode 3 is plated to a thickness smaller than that of the base insulating film 2, and the surface of the oxide insulating layer 3a to be formed is the base insulating film. If the anodic oxidation is performed so as to be flush with the surface of No. 2, the film forming surface of the gate insulating film 4 to be formed thereafter becomes a flat surface without steps.
【００２４】そして、このようにゲート絶縁膜４の成膜
面が段差のない平坦面であれば、ゲート絶縁膜４の成膜
に際して、このゲート絶縁膜４が均一な厚さに堆積する
ため、ゲート電極３の側縁付近におけるゲート絶縁膜４
の絶縁耐圧も十分になる。If the gate insulating film 4 has a flat surface without steps, the gate insulating film 4 is deposited to a uniform thickness when the gate insulating film 4 is formed. Gate insulating film 4 near the side edge of the gate electrode 3
Also has a sufficient withstand voltage.
【００２５】しかも、上記製造方法で薄膜トランジスタ
を製造すると、ゲート電極３の上の絶縁層が、ゲート電
極３の上に生成させた酸化絶縁層３ａと、その上に成膜
したゲート絶縁膜４との二層膜になるため、ゲート電極
３とソース，ドレイン電極８，９との間の絶縁耐圧はさ
らに高くなる。Moreover, when a thin film transistor is manufactured by the above manufacturing method, the insulating layer on the gate electrode 3 includes the oxide insulating layer 3a formed on the gate electrode 3 and the gate insulating film 4 formed thereon. Since it is a two-layer film, the withstand voltage between the gate electrode 3 and the source / drain electrodes 8 and 9 is further increased.
【００２６】したがって、上記製造方法によれば、ゲー
ト電極３の側縁付近におけるゲート絶縁膜４の絶縁耐圧
も十分に確保して、ゲート電極３とソース，ドレイン電
極８，９との間の短絡発生を確実に防ぎ、信頼性の高い
薄膜トランジスタを製造することができる。Therefore, according to the above-mentioned manufacturing method, the dielectric strength of the gate insulating film 4 near the side edge of the gate electrode 3 is sufficiently ensured, and the gate electrode 3 and the source / drain electrodes 8 and 9 are short-circuited. It is possible to reliably prevent the generation of the thin film transistor and to manufacture a highly reliable thin film transistor.
【００２７】なお、上記実施例では、逆スタガー型薄膜
トランジスタの製造について説明したが、本発明は、ソ
ース，ドレイン電極をゲート絶縁膜とｉ型半導体層との
間に形成した逆コプラナー型薄膜トランジスタの製造に
も適用することができる。In addition, although the manufacture of the inverted stagger type thin film transistor has been described in the above embodiment, the present invention manufactures the inverted coplanar type thin film transistor in which the source and drain electrodes are formed between the gate insulating film and the i type semiconductor layer. Can also be applied to.
【００２８】[0028]
【発明の効果】本発明によれば、基板上にゲート電極を
形成した後のゲート絶縁膜の成膜に際してこのゲート絶
縁膜を均一な厚さに堆積させ、ゲート電極の側縁付近に
おけるゲート絶縁膜の絶縁耐圧も十分に確保して、ゲー
ト電極とソース，ドレイン電極との間の短絡発生を確実
に防ぐことができる。According to the present invention, when the gate insulating film is formed after the gate electrode is formed on the substrate, the gate insulating film is deposited to a uniform thickness so that the gate insulating film near the side edge of the gate electrode is formed. The dielectric strength of the film can be sufficiently ensured, and the occurrence of a short circuit between the gate electrode and the source / drain electrodes can be reliably prevented.
【図１】本発明の一実施例を示す薄膜トランジスタの製
造工程図。FIG. 1 is a manufacturing process diagram of a thin film transistor showing an embodiment of the present invention.
１…基板、Ａ…ゲート電極形成領域、２…下地絶縁膜、
３…ゲート電極、３ａ…酸化絶縁層、４…ゲート絶縁
膜、５…ｉ型半導体層、６…ブロッキング絶縁膜、７…
ｎ型半導体層、８…ソース電極、９…ドレイン電極、１
０…画素電極、Ｍ…レジストマスク。1 ... Substrate, A ... Gate electrode forming region, 2 ... Base insulating film,
3 ... Gate electrode, 3a ... Oxidation insulating layer, 4 ... Gate insulating film, 5 ... i-type semiconductor layer, 6 ... Blocking insulating film, 7 ...
n-type semiconductor layer, 8 ... Source electrode, 9 ... Drain electrode, 1
0 ... Pixel electrode, M ... Resist mask.
Claims (1)
て下地絶縁膜を形成した後、前記基板のゲート電極形成
領域の上に金属をメッキして前記下地絶縁膜の膜厚より
薄い厚さのゲート電極を形成するとともに、前記ゲート
電極の上面を陽極酸化して、このゲート電極の上に、表
面が前記下地絶縁膜の表面と面一になる厚さに酸化絶縁
層を生成させ、この後、前記酸化絶縁層および前記下地
絶縁膜の上にゲート絶縁膜を成膜し、その上に半導体層
およびソース，ドレイン電極を形成することを特徴とす
る薄膜トランジスタの製造方法。1. A thin film having a thickness smaller than that of the base insulating film is formed by forming a base insulating film on the insulating substrate except the gate electrode forming region and then plating a metal on the gate electrode forming region of the substrate. A gate electrode is formed, and the upper surface of the gate electrode is anodized to form an oxide insulating layer on the gate electrode to a thickness such that the surface is flush with the surface of the base insulating film, After that, a gate insulating film is formed on the oxide insulating layer and the base insulating film, and a semiconductor layer and source / drain electrodes are formed on the gate insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23111191A JPH0548102A (en) | 1991-08-20 | 1991-08-20 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23111191A JPH0548102A (en) | 1991-08-20 | 1991-08-20 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0548102A true JPH0548102A (en) | 1993-02-26 |
Family
ID=16918474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23111191A Pending JPH0548102A (en) | 1991-08-20 | 1991-08-20 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0548102A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8054147B2 (en) | 2009-04-01 | 2011-11-08 | General Electric Company | High voltage switch and method of making |
-
1991
- 1991-08-20 JP JP23111191A patent/JPH0548102A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8054147B2 (en) | 2009-04-01 | 2011-11-08 | General Electric Company | High voltage switch and method of making |
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