JPH0547848A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0547848A
JPH0547848A JP3200721A JP20072191A JPH0547848A JP H0547848 A JPH0547848 A JP H0547848A JP 3200721 A JP3200721 A JP 3200721A JP 20072191 A JP20072191 A JP 20072191A JP H0547848 A JPH0547848 A JP H0547848A
Authority
JP
Japan
Prior art keywords
bumps
polyimide
tape
ics
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3200721A
Other languages
Japanese (ja)
Inventor
Masami Uchida
将巳 内田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP3200721A priority Critical patent/JPH0547848A/en
Publication of JPH0547848A publication Critical patent/JPH0547848A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor device, which has a fine pattern but has sufficient strength of leads, by using a flexible substrate of polyimide with bumps on both sides. CONSTITUTION:A conducting pattern in a polyimide base film 1 includes electrodes. The base film is laser-machined to open holes, though which gold plating is applied to the nickel-plated pattern, and then bumps 3 are formed. The tape thus prepared has bumps on both sides, and it is used to mount ICs. The bumps protrude about 10 microns above the surfaces of the tape. The bumps are gold-plated so that it may easily form a eutectic with aluminum pads of ICs. When ICs having the aluminum pads of a fine pitch are mounted by thermocompression bonding, heat and pressure are carried through the bumps to the other side of the ICs. This minimizes damage due to the heat and pressure involved in the bonding. In addition, leads are protected in the polyimide film and their strength is maintained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はＩＣチップを実装する半
導体装置に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting an IC chip.

【０００２】[0002]

【従来の技術】従来のＩＣチップ実装に用いられるフレ
キシブル基板としては、ポリイミド上の接着層に銅箔を
張り合わせた、通常３−Ｌａｙｅｒと呼ばれるテープの
銅箔にエッチングによりパターニングしたもの、あるい
は、図３に示すようにＴＡＢ実装で用いられるポリイミ
ドをＩＣ外形寸法よりやや大きめにオーバーハングさせ
て、インナーリード７をエッチングにより形成したも
の、あるいは図４のようにインナーリード７に突起部１
０をエッチングにより形成したもの、あるいは通常２−
Ｌａｙｅｒと呼ばれる３−Ｌａｙｅｒテープにおいて接
着層がなく直接銅箔とポリイミドが接合されたテープを
用い前述３−Ｌａｙｅｒと同様にパターニング形成され
たものが使われていた。2. Description of the Related Art As a conventional flexible substrate used for mounting IC chips, a copper foil of a tape usually called 3-Layer, which is obtained by laminating a copper foil on an adhesive layer on polyimide, or is patterned by etching. As shown in FIG. 3, the inner lead 7 is formed by etching by overhanging the polyimide used for TAB mounting to be slightly larger than the outer dimensions of the IC, or the protrusion 1 is formed on the inner lead 7 as shown in FIG.
0 formed by etching, or usually 2-
A 3-Layer tape called a Layer, which is a tape formed by directly bonding a copper foil and a polyimide without an adhesive layer and patterned similarly to the above-mentioned 3-Layer, has been used.

【０００３】[0003]

【発明が解決しようとする課題】従来のようにＩＣチッ
プを実装するフレキシブル基板は、銅箔をエッチングし
てＩＣ実装用インナーリードを形成するためＩＣのパッ
ドが細密化されるにしたがい同然インナーリードも細密
化しなければならない。これにより、リード強度は弱く
なり、またポリイミドとの密着面積も少なくなるため密
着力も不足し、実装時リードが切れたりあるいはリード
がはがれるといった初期不良が生じた、さらに温度サイ
クルや通電耐湿と言った信頼性試験においても同様の問
題が生じている。In the conventional flexible substrate on which the IC chip is mounted, the inner lead is almost the same as the pad of the IC is made fine because the inner lead for mounting the IC is formed by etching the copper foil. Must also be refined. As a result, the lead strength was weakened, and the adhesion area with the polyimide was also small, resulting in insufficient adhesion, resulting in initial defects such as breakage of the leads or peeling of the leads during mounting. Similar problems occur in reliability tests.

【０００４】[0004]

【課題を解決するための手段】前述の課題に対して、本
発明は、最近テープメーカーより細密プロービング用に
開発されたものである。導体を中間層に持つポリイミド
テープを、エッチングあるいはレーザー加工によりポリ
イミドの上下に穴をあけ、この穴にポリイミド内部に形
成された導体パターンをメッキ電極として、ポリイミド
表面より数十ミクロン凸状になるようにバンプを形成し
た両面バンプ付きポリイミドテープをＩＣチップの実装
用フレキシブル基板に使用することで、前述課題を解決
するものである。SUMMARY OF THE INVENTION With respect to the above-mentioned problems, the present invention has been recently developed by a tape manufacturer for fine probing. A polyimide tape having a conductor as an intermediate layer is formed by etching or laser processing on the upper and lower sides of the polyimide, and the conductor pattern formed inside the polyimide is used as a plating electrode in this hole so that it protrudes several tens of microns from the polyimide surface. The above problem is solved by using a double-sided bumped polyimide tape having bumps formed on a flexible substrate for mounting an IC chip.

【０００５】[0005]

【実施例】図１は本発明の一実施例を示すものである。FIG. 1 shows an embodiment of the present invention.

【０００６】図１において、１のポリイミドのベースフ
ィルム内に形成された導体パターン２を電極とし、レー
ザーあるいはエッチング加工により５０μｍの穴をあけ
そこにニッケルメッキ上に約５〜６μｍの金メッキを
し、バンプ３を形成させた両面バンプテープをＩＣ実装
に応用した例である。バンプ３はポリイミド表面から約
１０μｍ出ている。バンプ３の表面を金メッキすること
で、ＩＣのＡｌパッドとの共晶合金を作り易くした。細
密ピッチＩＣ５（以下単にＩＣと呼ぶ）のアルミパッド
４とバンプ３を熱圧着により実装する際、ＩＣと反対側
にあるバンプをＩＣ側のバンプに相対する位置かあるい
は近傍に形成することで、ボンディング時直接ポリイミ
ドにボンディングツールがあたるのを防ぐようにした。
すなわちＩＣと反対側のバンプを通してボンディング時
の熱や圧力を伝達させた。このようにすることでボンデ
ィング時の熱や圧力によるダメージをほとんどなくすこ
とが可能となるのである。このように両面バンプ付きポ
リイミドテープを細密ピッチＩＣ実装に応用することで
リードはポリイミドで保護されて強度劣化することな
く、またバンプ３の表面に約５〜６μｍ金メッキをする
ことで、ＴＡＢのような金バンプ付きＩＣを使用せず
に、通常のアルミパッドのＩＣで接合することが可能と
なるためコストメリット及び汎用性が従来のＴＡＢに比
べ数段向上することになる。さらにバンプ３はＩＣの能
動面上にも形成が容易に出来るため、ＩＣの多ピン化に
必要なＩＣ能動面に形成されたアルミパッドに対しても
実装を容易に行なうことができる。In FIG. 1, a conductor pattern 2 formed in a polyimide base film 1 is used as an electrode, a hole of 50 μm is opened by laser or etching, and a nickel plating of about 5 to 6 μm is formed on the hole. This is an example in which a double-sided bump tape having bumps 3 formed thereon is applied to IC mounting. The bump 3 is projected about 10 μm from the polyimide surface. The surface of the bump 3 was plated with gold to facilitate the formation of a eutectic alloy with the Al pad of the IC. When the aluminum pads 4 and the bumps 3 of the fine pitch IC 5 (hereinafter simply referred to as IC) are mounted by thermocompression bonding, the bumps on the side opposite to the ICs are formed at or near the bumps on the IC side. The bonding tool was prevented from hitting the polyimide directly during bonding.
That is, heat and pressure at the time of bonding were transmitted through the bump on the side opposite to the IC. By doing so, it is possible to almost eliminate damage due to heat and pressure during bonding. By applying the double-sided bumped polyimide tape to the fine pitch IC mounting, the leads are protected by the polyimide and the strength is not deteriorated. Since it is possible to join with an IC having a normal aluminum pad without using an IC with a gold bump, cost merit and versatility are improved several steps as compared with the conventional TAB. Further, since the bumps 3 can be easily formed on the active surface of the IC, it is possible to easily mount the aluminum pads formed on the active surface of the IC, which is necessary for increasing the number of pins of the IC.

【０００７】図２は、図１の１つの応用例であるが、Ｉ
Ｃ実装後の総厚を薄くするために、ＩＣの外形サイズよ
りやや大きめに、ハーフエッチングによりデバイスホー
ル６をあけたテープについて、図１と同様にニッケルメ
ッキ上に約５〜６μｍの金メッキを施したバンプ３を形
成したＩＣのデバイスホールを持つ両面バンプ付きテー
プをＩＣの実装に応用したものである。このようにハー
フエッチングすることで、ＩＣの実装後、ＩＣの周辺部
を液状モールドでモールドする時、このハーフエッチン
グがモールドの流れ止めにも作用するため、薄型でかつ
モールド形状の整った液状モールドパッケージを作るこ
とが出来るのである。FIG. 2 shows one application example of FIG.
In order to reduce the total thickness after C mounting, a tape having a device hole 6 formed by half etching, which is slightly larger than the external size of the IC, is plated with gold of about 5 to 6 μm on nickel plating as in FIG. The tape with the double-sided bump having the IC device hole in which the bump 3 is formed is applied to the mounting of the IC. By half-etching as described above, when the peripheral portion of the IC is molded with the liquid mold after mounting the IC, the half etching also acts as a flow stop for the mold, so that the liquid mold is thin and has a well-shaped mold. You can make a package.

【０００８】[0008]

【発明の効果】本発明によれば、現在ポリイミドの加工
は３０〜４０μｍピッチまで可能であり、今後のＩＣ細
密化には従来のポリイミドテープでは不可能な領域まで
可能となるのである。さらに両面にバンプを形成するこ
とが可能であり、このバンプを利用することでギャング
ボンディングのようにツール加熱によりボンディングす
る場合に、直接ポリイミドにツールが当たらないで済む
ため熱によるポリイミドへの変形も少なくなる。また、
このバンプを利用して、ポリイミドをＩＣ外形状に切断
し、接着剤を利用して、基板等へのフリップチップ実装
と同等の実装も可能となる。さらに、従来のようなポリ
イミドテープではＩＣの細密化によりインナーリード幅
が狭くなりリード強度が著しく劣化するが、本発明にお
けるバンプ付ポリイミドテープにおいては、リードがポ
リイミド内に形成されているため細密化に共うリード強
度の劣化も問題とならず、今後の細密多ピンＩＣ実装に
は必ず必要となる技術である。According to the present invention, it is possible to process polyimide at a pitch of 30 to 40 .mu.m at present, and it becomes possible to make the IC finer in the future in a region that cannot be achieved by the conventional polyimide tape. Furthermore, it is possible to form bumps on both sides.By using these bumps, when bonding with tool heating such as gang bonding, the tool does not have to hit the polyimide directly, so deformation to polyimide due to heat is also possible. Less. Also,
The bumps can be used to cut the polyimide into an IC external shape, and an adhesive can be used to perform mounting equivalent to flip-chip mounting on a substrate or the like. Further, in the conventional polyimide tape, the inner lead width is narrowed and the lead strength is remarkably deteriorated due to the miniaturization of the IC. However, in the bumped polyimide tape of the present invention, since the leads are formed in the polyimide, the miniaturization is made. Degradation of the lead strength due to the above does not pose a problem, and is a technology that is indispensable for future fine multi-pin IC mounting.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の実施例図である。FIG. 1 is a diagram illustrating an embodiment of the present invention.

【図２】 本発明の実施例図である。FIG. 2 is a diagram illustrating an embodiment of the present invention.

【図３】 従来の断面図である。FIG. 3 is a conventional cross-sectional view.

【図４】 従来の断面図である。FIG. 4 is a conventional cross-sectional view.

【符号の説明】[Explanation of symbols]

１ ポリイミド ２ 中間層の導体パターン ３ メッキバンプ ４ 細密ピッチＩＣのアルミパッド ５ 細密ピッチＩＣチップ ６ ポリイミドのハーフエッチング部 ７ インナーリード ８ ポリイミド ９ ＩＣの金バンプ １０ インナーリードの突起部 1 Polyimide 2 Conductor pattern of intermediate layer 3 Plating bump 4 Aluminum pad of fine pitch IC 5 Fine pitch IC chip 6 Half etching part of polyimide 7 Inner lead 8 Polyimide 9 Gold bump of IC 10 Protrusion part of inner lead

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 導体パターンを中間層に持つポリイミド
テープで、当該導体パターンを挟むように当該ポリイミ
ドテープ両面に開けられた穴に当該導体パターンを電極
としメッキにより導体バンプを形成した両面バンプ付き
ポリイミドテープにおいて、前記両面バンプ付きポリイ
ミドテープをＩＣチップの実装用フレキシブル基板とし
て用いることを特徴とする半導体装置。1. A polyimide tape with double-sided bumps, comprising a polyimide tape having a conductor pattern as an intermediate layer, wherein conductor holes are formed in both sides of the polyimide tape so as to sandwich the conductor pattern, and the conductor pattern is used as an electrode to form conductor bumps by plating. A semiconductor device, characterized in that the polyimide tape with double-sided bumps is used as a flexible substrate for mounting an IC chip in a tape. 【請求項２】 ＩＣの外形寸法よりやや大きめにポリイ
ミドをハーフエッチングし、当該ハーフエッチング部に
請求項１記載と同じ両面導体バンプを形成したハーフエ
ッチング部を持つ両面バンプ付きポリイミドテープをＩ
Ｃチップの実装用フレキシブル基板としたことを特徴と
する請求項１記載の半導体装置。2. A polyimide tape with double-sided bumps, which has a half-etched portion in which polyimide is half-etched to a size slightly larger than the external dimensions of the IC, and the same double-sided conductor bump as in claim 1 is formed in the half-etched portion.
The semiconductor device according to claim 1, wherein the semiconductor device is a flexible substrate for mounting a C chip. 【請求項３】 導体バンプとして、ニッケルメッキ上に
金メッキにより形成することを特徴とする請求項１記載
の半導体装置。3. The semiconductor device according to claim 1, wherein the conductor bump is formed by gold plating on nickel plating.
JP3200721A 1991-08-09 1991-08-09 Semiconductor device Pending JPH0547848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3200721A JPH0547848A (en) 1991-08-09 1991-08-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3200721A JPH0547848A (en) 1991-08-09 1991-08-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0547848A true JPH0547848A (en) 1993-02-26

Family

ID=16429099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3200721A Pending JPH0547848A (en) 1991-08-09 1991-08-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0547848A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020065705A (en) * 2001-02-07 2002-08-14 삼성전자 주식회사 Tape circuit substrate and manufacturing method thereof and semiconductor chip package using thereof
US7457648B2 (en) 2003-02-10 2008-11-25 Fujitsu Limited Screw cap for electronic apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020065705A (en) * 2001-02-07 2002-08-14 삼성전자 주식회사 Tape circuit substrate and manufacturing method thereof and semiconductor chip package using thereof
US7457648B2 (en) 2003-02-10 2008-11-25 Fujitsu Limited Screw cap for electronic apparatus

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