JPH0546091B2 - - Google Patents
Info
- Publication number
- JPH0546091B2 JPH0546091B2 JP58128912A JP12891283A JPH0546091B2 JP H0546091 B2 JPH0546091 B2 JP H0546091B2 JP 58128912 A JP58128912 A JP 58128912A JP 12891283 A JP12891283 A JP 12891283A JP H0546091 B2 JPH0546091 B2 JP H0546091B2
- Authority
- JP
- Japan
- Prior art keywords
- resist
- cooling
- baking
- temperature
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001816 cooling Methods 0.000 claims description 72
- 239000000758 substrate Substances 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 37
- 238000011161 development Methods 0.000 claims description 9
- 239000002245 particle Substances 0.000 claims description 7
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 230000035945 sensitivity Effects 0.000 description 20
- 238000012545 processing Methods 0.000 description 14
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 9
- 230000018109 developmental process Effects 0.000 description 8
- 238000009826 distribution Methods 0.000 description 8
- 238000010894 electron beam technology Methods 0.000 description 7
- 239000002904 solvent Substances 0.000 description 6
- 238000011282 treatment Methods 0.000 description 6
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 4
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000003507 refrigerant Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 230000009477 glass transition Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000009529 body temperature measurement Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- -1 poly(2,2,2-trifluoroethyl-α-chloroacrylate) Polymers 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000001356 surgical procedure Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
- G03F7/168—Finishing the coated layer, e.g. drying, baking, soaking
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、高精度のレジストパターンを形成す
る方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of forming a highly accurate resist pattern.
超LSIを初めとして、半導体素子の集積度が高
まるにつれて、微細にして且つ高精度のパターン
形成技術が要求されている。このため、許容され
る寸法精度は非常に厳しいものとなり、最先端分
野で６インチ□マスク或いは５インチ径ウエハ内
で3σ0.1〔μｍ〕（但し、σはウエハの平均寸法
値に対するばらつきを示す）の寸法精度が要求さ
れている。また、量産ラインで使用されるために
はマスク間或いはウエハ間での寸法変動を3σ
0.15〔μｍ〕に抑えることが必要であり、一方量
産効果を高めるために、レジストの感度としては
高いものが要求されている。しかし、一般に高感
度のレジストは解像性が劣るため所望のパターン
寸法精度を得ることが困難であり、逆に高解像性
を有するレジストは低感度であるために量産ライ
ンにおいて高スループツトが得られない等の問題
があつた。
As the degree of integration of semiconductor devices, including VLSIs, increases, finer and more precise pattern forming techniques are required. For this reason, the permissible dimensional accuracy is extremely strict, and in the cutting-edge field, it is 3σ0.1 [μm] within a 6-inch mask or a 5-inch diameter wafer (where σ indicates the variation with respect to the average dimensional value of the wafer. ) dimensional accuracy is required. In addition, in order to be used on a mass production line, dimensional variations between masks or wafers must be reduced to 3σ.
It is necessary to suppress the thickness to 0.15 [μm], and on the other hand, in order to increase the effectiveness of mass production, high sensitivity of the resist is required. However, in general, high-sensitivity resists have poor resolution, making it difficult to obtain the desired pattern dimensional accuracy; conversely, high-resolution resists have low sensitivity, making it difficult to achieve high throughput on mass production lines. There were problems such as not being able to do it.
第１図は従来技術によるレジストパターン形成
プロセスを示すフローチヤートである。まず、被
処理基板上に周知の回転塗布法により所定の膜厚
にレジストを塗布する。次いで、塗布溶媒の除去
並びにレジストと基板との密着性を向上させるた
めに、オーブン等を用いレジストに応じた所定の
温度Tbでレジストのベーク（プリベーク）を行
なう。この後、オーブンから取り出されたレジス
ト膜付被処理基板を大気中で支持台にて自然放冷
することにより、室温まで20〜30分かけて冷却す
る。冷却の完了したレジスト膜付被処理基板に対
して、レジストの種類に応じた所定の照射量で所
定波長域の電磁波、冷えば紫外線或いは所定エネ
ルギーの粒子線、例えば電子線を選択的に照射す
る。その後、現像・リンス処理工程を経て所望の
レジストパターンが形成されることになる。 FIG. 1 is a flowchart showing a resist pattern forming process according to the prior art. First, a resist is applied to a predetermined thickness on a substrate to be processed by a well-known spin coating method. Next, in order to remove the coating solvent and improve the adhesion between the resist and the substrate, the resist is baked (prebaked) using an oven or the like at a predetermined temperature T b depending on the resist. Thereafter, the resist film-coated substrate to be processed taken out from the oven is allowed to cool naturally on a support stand in the atmosphere, thereby cooling to room temperature over 20 to 30 minutes. The cooled resist film-coated substrate to be processed is selectively irradiated with electromagnetic waves in a predetermined wavelength range, ultraviolet rays when cooled, or particle beams with a predetermined energy, such as electron beams, at a predetermined dose depending on the type of resist. . Thereafter, a desired resist pattern is formed through a development and rinsing process.
ところで、上述した自然放冷中の被処理基板上
のレジスト膜について、ある時点における膜面全
体の温度分布を赤外線放射温度計によつて本発明
者等が調べたところ、第２図に示すような結果が
得られた。なお、この場合の自然冷却に先立つベ
ーク時の温度Tbは〜160〔℃〕であつた。第２図
において、レジスト膜付被処理基板２１の中央部
上方（Ａ点）では温度が高く（冷却され方が遅
く）、中心領域（Ｂ点）を経て下方（Ｃ点）に進
むにつれて温度が低く（冷却され方が速く）なつ
ている。なお、図中の各曲線は等温線である。第
３図は第２図のＡ，Ｂ，Ｃ各点における時間に対
する温度変化を示したもので、曲線３１，３２，
３３は夫々Ａ，Ｂ，Ｃ点に対応する冷却特性であ
る。Ａ点とＢ点の最大温度差は15〔℃〕程度、Ａ
点とＣ点の最大温度差は30〔℃〕程度であつた。
これらの温度測定はレジスト膜上の被測定部分に
熱電対を接飾させて行なつた。このような温度分
布（冷却速度むら）が生じる原因としては、自然
放冷中被処理基板が支持台等の上に立てられてい
るために、熱放散による雰囲気の自然対流が基板
面に沿つて上向きに起り易いこと、及び基板下方
部が支持台により熱を奪われ易いこと等が考えら
れる。また、本発明者等は上記レジスト膜付被処
理基板の冷却時の温度分布と照射・現像処理後の
レジストパターンの寸法精度との関係について着
目し、第２図の温度測定点Ａ，Ｂ，Ｃ領域におけ
る形成パターンの寸法を測定したところ、本来例
えば２〔μｍ〕の同寸法であるべきパターンにＢ
点において0.1〔μｍ〕、Ｃ点において0.2〔μｍ〕
程度の誤差が生じており、レジスト膜付基板の冷
却時の温度分布と形成されるレジストパターンの
寸法分布とが、レジストの感度分布を通して完全
に対応していることを確認した。したがつて、パ
ターン寸法むらのない高精度のレジストパターン
を得るには、レジストベーク後基板面内で温度分
布を生ぜしめない様な均一な冷却が不可欠である
ことが判つた。 By the way, when the present inventors investigated the temperature distribution of the entire film surface at a certain point in time using an infrared radiation thermometer for the resist film on the substrate to be processed during the natural cooling described above, the results were as shown in Fig. 2. The results were obtained. In this case, the temperature T b during baking prior to natural cooling was ~160 [°C]. In FIG. 2, the temperature is high (cooling is slow) at the upper center of the substrate 21 to be processed with a resist film (point A), and the temperature increases as it moves downward (point C) through the center region (point B). The temperature is low (it cools down quickly). Note that each curve in the figure is an isothermal line. Figure 3 shows the temperature changes over time at points A, B, and C in Figure 2, with curves 31, 32,
33 are cooling characteristics corresponding to points A, B, and C, respectively. The maximum temperature difference between point A and point B is about 15 [℃], A
The maximum temperature difference between point and point C was about 30 [°C].
These temperature measurements were carried out by attaching a thermocouple to the portion to be measured on the resist film. The reason for this temperature distribution (uneven cooling rate) is that during natural cooling, the substrate to be processed is placed on a support stand, etc., and the natural convection of the atmosphere due to heat dissipation occurs along the substrate surface. Possible reasons include that it tends to occur upward, and that heat is easily removed from the lower part of the substrate by the support. In addition, the present inventors focused on the relationship between the temperature distribution during cooling of the substrate to be processed with a resist film and the dimensional accuracy of the resist pattern after irradiation and development processing. When we measured the dimensions of the formed pattern in area C, we found that B
0.1 [μm] at point, 0.2 [μm] at point C
It was confirmed that the temperature distribution during cooling of the resist film coated substrate and the size distribution of the formed resist pattern completely corresponded to each other through the sensitivity distribution of the resist. Therefore, it has been found that in order to obtain a highly accurate resist pattern with uniform pattern dimensions, uniform cooling that does not cause temperature distribution within the substrate surface after resist baking is essential.
一方、発明者等がベーク後のレジストの冷却速
度とレジスト感度との関係に着目し種々実験・研
究を重ねた結果、従来のプロセスにより長時間か
けて冷却されたレジストの感度は低いが、レジス
トをベークしたのち急速に冷却した場合のレジス
トの感度は飛躍的に高まることを見出した。さら
に、ベーク後のレジスト膜の冷却過程を制御する
ことにより、レジストの感度を再現性良く任意の
値に変化させ得ることも見出した。そして、これ
らのプロセスを経たレジストの解像性は、レジス
ト本来のパターン解像性に比べて、いささかも劣
化していないことも確認している。また、従来の
レジストベークは大気中に行つていたので、ベー
クの主目的であるレジスト溶媒の蒸発に長時間を
要することが判明した。 On the other hand, the inventors focused on the relationship between the cooling rate of the resist after baking and the resist sensitivity, and as a result of various experiments and research, they found that the sensitivity of the resist cooled over a long time by the conventional process is low, but the resist It was discovered that the sensitivity of the resist increases dramatically when it is rapidly cooled after baking. Furthermore, we have also discovered that by controlling the cooling process of the resist film after baking, it is possible to change the sensitivity of the resist to any desired value with good reproducibility. It has also been confirmed that the resolution of resists that have gone through these processes has not deteriorated in the slightest compared to the original pattern resolution of the resists. Furthermore, since conventional resist baking was performed in the atmosphere, it was found that it took a long time to evaporate the resist solvent, which is the main purpose of baking.
本発明の目的は、高精度のレジストパターンを
効率良く且つ迅速に形成することができ、パター
ン形成のスループツト向上等に寄与し得るレジス
トパターン形成方法を提供することにある。
An object of the present invention is to provide a resist pattern forming method that can efficiently and quickly form a highly accurate resist pattern and can contribute to improving the throughput of pattern formation.
本発明の骨子は、レジストのベーク及び冷却の
少くとも一方を常圧より低い圧力下（１気圧未
満）で行うことにある。
The gist of the present invention is to perform at least one of baking and cooling the resist under a pressure lower than normal pressure (less than 1 atmosphere).
本発明によるレジストパターン形成の基本的プ
ロセスの概要を第４図に示す。まず、被処理基板
上にレジスト膜を塗布形成する。次いで、このレ
ジスト膜付基板を１気圧より低い圧力下の減圧容
器中に収納し、所定の温度Tbにて所定の時間レ
ジストベークを行う。次いで、上記減圧容器内で
冷却時間若しくは冷却速度を制御しながら最終冷
却温度Tcまでのレジスト膜全体に亘る均一な冷
却を行う。しかるのち、このレジストに対し所定
波長の電磁波若しくは所定エネルギの粒子線を選
択的に照射し、これを現像・リンス処理すること
によりレジストパターンを形成する。 FIG. 4 shows an outline of the basic process of forming a resist pattern according to the present invention. First, a resist film is applied and formed on a substrate to be processed. Next, this resist film coated substrate is placed in a reduced pressure container under a pressure lower than 1 atmosphere, and resist baking is performed at a predetermined temperature T b for a predetermined time. Next, uniform cooling is performed over the entire resist film to the final cooling temperature Tc while controlling the cooling time or cooling rate in the vacuum container. Thereafter, this resist is selectively irradiated with electromagnetic waves of a predetermined wavelength or particle beams of a predetermined energy, and is developed and rinsed to form a resist pattern.
すなわち本発明は、被処理基板上にレジストを
塗布し、ベークしたのち冷却し、さらに所定波長
の電磁波若しくは所定エネルギの粒子線を該レジ
ストに選択的に照射し、現像処理を施すことによ
りレジストパターンを形成する方法において、上
記レジストのベーク及び冷却の少くとも一方を常
圧より低い圧力下で行うようにした方法である。 That is, in the present invention, a resist pattern is formed by applying a resist onto a substrate to be processed, baking it, cooling it, selectively irradiating the resist with an electromagnetic wave of a predetermined wavelength or a particle beam of a predetermined energy, and performing a development process. In this method, at least one of baking and cooling the resist is performed under a pressure lower than normal pressure.
本発明によれば、レジストのベークを減圧下で
行うことにより、レジスト溶媒の蒸発を促進させ
ることができ、これによりレジストベークに要す
る時間の大幅な短縮をはかり得る。また、レジス
トの冷却を減圧下で行うことにより、雰囲気の自
然対流に起因する冷却速度むら発生を著しく低減
することができ、これによりレジストパターンの
高精度化をはかり得る。さらに、レジストのベー
ク及び冷却を減圧下で行うことにより、レジスト
膜面へのダスト付着が低減され、その結果所望の
レジストパターンが高歩留りで得られる。
According to the present invention, by baking the resist under reduced pressure, evaporation of the resist solvent can be promoted, thereby significantly reducing the time required for resist baking. Furthermore, by cooling the resist under reduced pressure, it is possible to significantly reduce the occurrence of cooling rate unevenness due to natural convection in the atmosphere, thereby making it possible to improve the precision of the resist pattern. Furthermore, by baking and cooling the resist under reduced pressure, dust adhesion to the resist film surface is reduced, and as a result, a desired resist pattern can be obtained with a high yield.
また、冷却時間若しくは冷却速度を制御しなが
ら、ベーク温度Tbから最終冷却温度Tcまでのレ
ジスト冷却を均一に行うことにより、レジストの
電磁波若しくは粒子線照射に対する感度を、その
解像性を劣化させることなく、大幅に高めること
ができる。したがつて、低感度のレジストでも本
発明の方法によつて解像性を劣化させることなく
高感度化され、電磁波若しくは粒子線による照射
処理時間を短縮することができる。しかも、本発
明によれば、ベーク後のレジスト膜が膜全体にわ
たつて均一に冷却されるほか、レジスト膜面が粗
面化することもないので、被処理基板上全体に亘
つて寸法ばらつきの少ない極めて高精度のレジス
トパターンを形成することができる。 In addition, by uniformly cooling the resist from the bake temperature T b to the final cooling temperature T c while controlling the cooling time or cooling rate, it is possible to reduce the sensitivity of the resist to electromagnetic waves or particle beam irradiation and reduce its resolution. It can be significantly increased without causing any damage. Therefore, even a low-sensitivity resist can be made highly sensitive by the method of the present invention without deteriorating its resolution, and the time for irradiation treatment with electromagnetic waves or particle beams can be shortened. Moreover, according to the present invention, the resist film after baking is cooled uniformly over the entire film, and the resist film surface is not roughened, so that dimensional variations can be reduced over the entire substrate to be processed. It is possible to form a resist pattern with a small number of extremely high precision.
実施例 １
本実施例でポリ（２，２，２−トリフルオロエ
チル−α−クロロアクリレート）よりなるポジ型
電子線感応レジストを用いた場合のレジストパタ
ーン形成方法について述べる。まず、上記レジス
トを周知の回転塗布法により被処理基板上に塗布
する。このとき、塗布膜厚は0.3〜１〔μｍ〕程度
でよいが、ここでは0.8〔μｍ〕とした。被処理基
板としては、半導体ウエハやガラス基板等種々あ
るが、ここでは金属膜付ガラス基板を用いた。次
に、後術するようなレジスト処理装置を用いて、
レジスト膜のベーク、冷却処理を行なつた。ベー
ク温度Tbは、上記レジストのガラス移転温度Tg
（〜133℃）を越える140〜190〔℃〕程度でよいが、
ここでは180〔℃〕とした。また、ベーク時のレジ
スト膜付被処理基板を取り巻く圧力は約0.1気圧
とし、この状態でのレジストベークを約10分間行
なつた。ベーク時間は更に短縮できるが、本実施
例では取り敢えず10分間とした。次いで、ベーク
温度Tbから最終冷却温度Tcまでの冷却を冷却時
間（冷却速度）を変えて行つた。本実施例では上
記温度Tcを室温とした。ベーク温度Tbから室温
Tcまでの冷却時間は、例えば30分、５分、
１分、10秒、５秒となるように冷却処理を
操作した。第５図はこれらの冷却処理時における
基板温度変化について示したものである。いずれ
の冷却処理においても、レジスト膜の冷却は膜面
全体に亘つて均一になされた。なお、冷却時のレ
ジスト膜付基板を取り巻く周囲の圧力は0.0001気
圧とした。これらのベク・冷却プロセスを経た
夫々のレジスト試料について電子線感度特性を調
べた結果、第６図に示す夫々に対応する感度曲線
が得られた。第６図の特性は、前記夫々のベー
ク、冷却プロセスを経たレジスト膜に加速電圧20
〔keV〕の電子線を照射後、室温でメチルイソブ
チルケトン（MIBK）：イソプロピルアルコール
（IPA）＝７：３現像液で10分間の現像処理、次い
でIPA液にて30秒のリンス処理を施こして得られ
たものである。Tcが〜の夫々のベーク、冷
却プロセスに対応するレジスト感度（膜厚残存率
ゼロとなる場合の電子性照射量）は４×10-6
〔Ｃ／cm2〕、２×10-6〔Ｃ／cm2〕、９×10-7
〔Ｃ／cm2〕、５×10-6〔Ｃ／cm2〕、３×10-7
〔Ｃ／cm2〕であつた。なお、従来のベーク（180
℃）→自然放冷（室温まで）プロセスを経て、上
記同様の電子線照射、現像、リンス処理を施こし
た場合の上記レジストの感度は〜４×10-6〔Ｃ／
cm2〕である。
Example 1 In this example, a method for forming a resist pattern using a positive electron beam sensitive resist made of poly(2,2,2-trifluoroethyl-α-chloroacrylate) will be described. First, the resist described above is applied onto a substrate to be processed by a well-known spin coating method. At this time, the coating film thickness may be about 0.3 to 1 [μm], but here it was set to 0.8 [μm]. Although there are various types of substrates to be processed, such as semiconductor wafers and glass substrates, a glass substrate with a metal film was used here. Next, using a resist processing device similar to that used for post-surgery,
The resist film was baked and cooled. The bake temperature T b is the glass transition temperature T g of the above resist.
(140-190 [℃] exceeding (~133℃) is sufficient, but
Here, the temperature was set to 180 [℃]. Further, the pressure surrounding the resist film-coated substrate to be processed during baking was approximately 0.1 atm, and resist baking was performed in this state for approximately 10 minutes. Although the baking time can be further shortened, it was set to 10 minutes in this example. Next, cooling was performed from the baking temperature T b to the final cooling temperature T c while changing the cooling time (cooling rate). In this example, the temperature T c was set to room temperature. Bake temperature T b to room temperature
Cooling time to T c is, for example, 30 minutes, 5 minutes,
The cooling treatment was operated for 1 minute, 10 seconds, and 5 seconds. FIG. 5 shows changes in substrate temperature during these cooling treatments. In both cooling treatments, the resist film was cooled uniformly over the entire film surface. Note that the pressure surrounding the resist film-coated substrate during cooling was 0.0001 atm. As a result of examining the electron beam sensitivity characteristics of each of the resist samples subjected to these vector cooling processes, sensitivity curves corresponding to each of them as shown in FIG. 6 were obtained. The characteristics shown in Figure 6 are the acceleration voltage of 20
After irradiation with an electron beam of [keV], the film was developed at room temperature with a 7:3 developer solution of methyl isobutyl ketone (MIBK):isopropyl alcohol (IPA) for 10 minutes, and then rinsed with an IPA solution for 30 seconds. This is what was obtained. The resist sensitivity (electronic irradiation dose when the film thickness residual rate is zero) corresponding to each baking and cooling process with T c is 4 × 10 -6
[C/cm 2 ], 2×10 -6 [C/cm 2 ], 9×10 -7
[C/cm 2 ], 5×10 -6 [C/cm 2 ], 3×10 -7
[C/cm 2 ]. In addition, conventional bake (180
℃)→ Natural cooling (to room temperature) process, followed by electron beam irradiation, development, and rinsing treatment as above, the sensitivity of the above resist is ~4 × 10 -6 [C/
cm2 ].
一方、上記したプロセスと同様の減圧ベーク、
減圧冷却を程こしたレジスト膜付基板（金属膜付
６インチ□ガラス基板）の周辺部分を除く全面
へ、20〔keV〕電子線描画装置を用いて上記〜
の場合の夫々に対応する照射量で選択的パター
ン照射を行ない、室温におけるBIBK／IPA
（７／３）現像、IPAリンス処理の行なつてレジ
ストパターンを形成した。これ等レジストパター
ンの解像性はすべて良好であつた。また、冷えば
線幅0.5〜2.0〔μｍ〕の範囲のレジストパターン
の寸法制度を測定評価した結果、いずれかの場合
のレジストパターンもすべて高精度で基盤面内の
寸法変動誤差3σ＜0.1〔μｍ〕を十分に満足するも
のであつた。 On the other hand, vacuum baking similar to the process described above,
Using a 20 [keV] electron beam lithography system, the above~
BIBK/IPA at room temperature was selectively irradiated with a dose corresponding to each case.
(7/3) Development and IPA rinsing were performed to form a resist pattern. The resolution of these resist patterns was all good. In addition, as a result of measuring and evaluating the dimensional accuracy of resist patterns with a line width in the range of 0.5 to 2.0 [μm] after cooling, all resist patterns in either case were highly accurate and the dimensional variation error within the substrate surface was 3σ < 0.1 [μm]. ] was fully satisfied.
実施例 ２
本実施例では、レジストとしてポリメチルメタ
スリレートを用いた。その他の条件は先に説明し
た実施例１と略同じである。ベーク温度Tbは、
本レジストのガラス転移温度Tg〜110〔℃〕を越
えた180〔℃〕に設定した。レジストベーク時の基
板周囲の圧力は0.3気圧とし、レジストベーク時
間は10分間とした。レジスト膜冷却時の基板周囲
の圧力は約0.0002気圧で、冷却は実施例１と同様
に、Tb→Tcに至る冷却時間として30分、５
分、１分、10秒、５秒を選んだ。これらの
レジスト試料に加速電圧20〔keV〕電子線照射後、
室温で13分間のMIBK現像、30秒間のIPAリンス
を行なつて、夫々の感度特性を調べた。その結
果、冷却プロセスに対応するレジスト感度は夫々
９×10-6〔Ｃ／cm2〕、6.5×10-6〔Ｃ／cm2〕、
５×10-6〔Ｃ／cm2〕、3.5×10-6〔Ｃ／cm2〕、2.5
×10-6〔Ｃ／cm2〕であつた。なお、従来のベーク
（160℃）→自然放冷（室温まで）を経て、上記と
同じ照射、現像、リンス効果を施こした場合の上
記レジストの感度は〜１×10-5〔Ｃ／cm2〕程度で
ある。Example 2 In this example, polymethyl methacrylate was used as the resist. Other conditions are substantially the same as in Example 1 described above. The baking temperature T b is
The glass transition temperature T g of this resist was set at 180 [°C], which exceeded 110 [°C]. The pressure around the substrate during resist baking was 0.3 atm, and the resist baking time was 10 minutes. The pressure around the substrate during cooling of the resist film was approximately 0.0002 atm, and the cooling time from T b to T c was 30 minutes and 55 minutes, as in Example 1.
I chose minutes, 1 minute, 10 seconds, and 5 seconds. After irradiating these resist samples with electron beams at an accelerating voltage of 20 [keV],
MIBK development for 13 minutes and IPA rinsing for 30 seconds were performed at room temperature, and the sensitivity characteristics of each were investigated. As a result, the resist sensitivities corresponding to the cooling process were 9×10 -6 [C/cm 2 ], 6.5×10 -6 [C/cm 2 ], and 6.5×10 -6 [C/cm 2 ], respectively.
5×10 -6 [C/cm 2 ], 3.5×10 -6 [C/cm 2 ], 2.5
×10 -6 [C/cm 2 ]. Furthermore, the sensitivity of the above resist when subjected to the same irradiation, development, and rinsing effects as above after going through conventional baking (160°C) → natural cooling (to room temperature) is ~1 × 10 -5 [C/cm 2 ].
一方、上記したプロセスと同様の減圧ベーク、
減圧冷却を施こしたレジスト膜付基板（金属膜付
６インチ□ガラス基板）の周辺部分を除く全面
へ、20〔keV〕電子線描画装置を用いて、上記
〜の場合の夫々に対応する照射量で選択的パタ
ーン照射を行ない、室温におけるMIBK現像、
IPAリンス処理を施こしてレジストパターンを形
成した。すべて基板上全体に亘り、レジストパタ
ーンの解像性は良好であつた。また、実施例１と
同様に線幅0.5〜2.0〔μｍ〕の範囲のレジストパ
ターンの寸法精度を測定評価した結果、何れの場
合のレジストパターンもすべて高精度で、基板面
内の寸法変動誤差はすべて3σ＜0.1〔μｍ〕であつ
た。 On the other hand, vacuum baking similar to the process described above,
Using a 20 [keV] electron beam lithography system, irradiation corresponding to each of the above cases is applied to the entire surface of a substrate with a resist film (a 6-inch □ glass substrate with a metal film) excluding the peripheral area that has been cooled under reduced pressure. Performs selective pattern irradiation at room temperature, MIBK development at room temperature,
A resist pattern was formed by performing IPA rinsing treatment. The resolution of the resist pattern was good over the entire substrate. In addition, as in Example 1, the dimensional accuracy of resist patterns with line widths in the range of 0.5 to 2.0 [μm] was measured and evaluated, and the results showed that all resist patterns in any case were highly accurate, with no dimensional fluctuation error within the substrate surface. All values were 3σ<0.1 [μm].
なお、本発明の主眼は、レジスト膜のベーク温
度Tbから室温付近までの冷却時間（冷却速度）
を均一に制御することもさることながら、ベー
ク・冷却の少くとも一方を減圧下で行うことにあ
る。レジストのベーク・冷却プロセスを減圧下で
行う理由は、基板へのダスト付着を極力抑制させ
ることもさることながら、ベーク時のレジスト溶
媒の迅速蒸発や、ベーク・冷却時の熱対流に起因
するレジスト膜面の温度分布むらの発生を抑えて
膜面全体に亘つてベーク・冷却を均一になさんが
ためである。 The main focus of the present invention is the cooling time (cooling rate) from the bake temperature T b of the resist film to around room temperature.
In addition to controlling the temperature uniformly, at least one of baking and cooling is performed under reduced pressure. The reason why the resist baking and cooling process is carried out under reduced pressure is to suppress dust adhesion to the substrate as much as possible, as well as to prevent the rapid evaporation of the resist solvent during baking and the resist resistance caused by thermal convection during baking and cooling. This is to prevent uneven temperature distribution on the film surface and to perform baking and cooling uniformly over the entire film surface.
また、上記実施例方法を用いれば、例えば種種
のレジスト照射（露光）装置の性能に適合するよ
うに、レジストの感度を任意に且つ均一に設定す
ることができる。本発明者等の研究結果による
と、ベーク温度Tbから室温付近までの冷却時間
を短く（冷却速度を大きく）すればするほどレジ
ストの感度は向上することが判つている。逆に、
冷却時間を述ばす（冷却速度を小さくする）とレ
ジストの感度は下がることが判つている。したが
つて、情況に応じて、上記実施例とは異なる冷却
時間（冷却速度）を設定して、レジストの感度を
所望の値に設定できることは云うまでもない。ま
た、上記実施例では二種類のレジストに関しての
レジストパターン形成例について述べたが、レジ
ストの種類、レジスト膜が被着される基板材料、
レジストの溶媒、現像液、さらにはベーク温度等
についても上述した実施例に限定されるものでは
なく、公知の種種の材料、現像液及びベーク温度
についても本発明の効果が達成されることを確認
している。また、レジストの露光方法について
も、上述した電子線以外に光線、Ｘ線、イオンビ
ーム等の所定波長域の電磁波や所定エネルギーの
粒子線を用いても本発明の意図する効果が得られ
る。また、ベーク・冷却時の基板を取り巻く周囲
圧力の設定についても上述の実施例で述べた値に
限定されるものではない。ベーク時の圧力はレジ
スト中の溶媒がベーク時に突沸若しくは突出しな
い範囲で可及的に小さく設定すえばよく、冷却時
の圧力は更に小さくする方が処理容器内の残留ガ
スに因る熱対流を抑制する上で望ましい。 Further, by using the method of the above embodiment, the sensitivity of the resist can be arbitrarily and uniformly set to match the performance of various types of resist irradiation (exposure) devices, for example. According to the research results of the present inventors, it has been found that the shorter the cooling time from the bake temperature T b to around room temperature (the higher the cooling rate), the more the sensitivity of the resist improves. vice versa,
It is known that the sensitivity of the resist decreases when the cooling time is increased (the cooling rate is decreased). Therefore, it goes without saying that depending on the situation, the sensitivity of the resist can be set to a desired value by setting a cooling time (cooling rate) different from that of the above embodiment. In addition, in the above embodiment, an example of resist pattern formation using two types of resists was described, but the type of resist, the substrate material to which the resist film is attached,
The resist solvent, developer, baking temperature, etc. are not limited to the above-mentioned examples, and it has been confirmed that the effects of the present invention can be achieved with various known materials, developing solutions, and baking temperatures. are doing. Furthermore, as for the resist exposure method, in addition to the above-mentioned electron beam, electromagnetic waves in a predetermined wavelength range such as light beams, X-rays, and ion beams, or particle beams with a predetermined energy can be used to obtain the effects intended by the present invention. Furthermore, the setting of the ambient pressure surrounding the substrate during baking and cooling is not limited to the values described in the above embodiments. The pressure during baking should be set as low as possible so that the solvent in the resist does not bump or protrude during baking, and the pressure during cooling should be set even lower to prevent thermal convection caused by residual gas in the processing container. Desirable for suppression.
実施例 ３
次に、本発明方法を実施するのに適合するレジ
スト処理装置の一例について第７図を参照して説
明する。第７図の装置は、例えば基板に対するレ
ジスト塗布から露光前までの一連の工程を全自動
処理する装置の一部で、レジストのベーク・冷却
を担うものである。図中７１はベーク・冷却処理
容器で、この容器７１の対向する側壁には開閉バ
ルブ７２ａ，７２ｂがそれぞれ設けられている。
処理容器７１を底部には支持台７３が設けられ、
この支持台７３上にレジスト膜７４付基板７５が
載置されるものとなつている。支持台７３の内部
には複数の冷却用冷媒通孔７６が画一的に設けら
れており、支持台７３の上方には加熱ヒータ７７
が載置されている。また、処理容器７１の上壁部
には圧力制御用管７７が設けられている。Embodiment 3 Next, an example of a resist processing apparatus suitable for carrying out the method of the present invention will be described with reference to FIG. The device shown in FIG. 7 is a part of a device that fully automatically processes a series of steps from, for example, resist application to a substrate to before exposure, and is responsible for baking and cooling the resist. In the figure, 71 is a baking/cooling processing container, and opening/closing valves 72a and 72b are provided on opposing side walls of this container 71, respectively.
A support stand 73 is provided at the bottom of the processing container 71,
A substrate 75 with a resist film 74 is placed on this support stand 73. A plurality of cooling refrigerant holes 76 are uniformly provided inside the support base 73, and a heater 77 is provided above the support base 73.
is placed. Further, a pressure control pipe 77 is provided on the upper wall of the processing container 71 .
前工程でレジスト膜７４が塗布形成された被処
理基板７５は、開閉バルブ７２ａを介して容器７
１内の支持台７３上に載置される。次いで、圧力
制御用管７８を通して容器７１内の圧力を１気圧
より低い所定の圧力に設定し、ヒータ７７により
所定温度Tbにて所定時間レジストのベークを行
う。ベーク後、容器７１内の圧力を更に下げ、冷
媒通孔７６に流量及び温度等が制御された冷媒を
循環させて、支持台７３上の基板７５をその下面
から均一に冷却する。この場合、基板７５と支持
台７３とが良好な熱接触をなしていることが必要
である。冷却処理終了後、容器７１内の圧力を大
気圧に戻し、開閉バルブ７２ｂを介して基板７５
を容器７１内に取り出す。この後、基板７５は次
工程の処理部へ搬送される。 The substrate 75 to be processed, on which the resist film 74 has been applied in the previous step, is transferred to the container 7 via the opening/closing valve 72a.
It is placed on a support stand 73 in 1. Next, the pressure inside the container 71 is set to a predetermined pressure lower than 1 atmosphere through the pressure control pipe 78, and the resist is baked at a predetermined temperature Tb for a predetermined time using the heater 77. After baking, the pressure inside the container 71 is further lowered, and a refrigerant whose flow rate, temperature, etc. are controlled is circulated through the refrigerant passage hole 76 to uniformly cool the substrate 75 on the support table 73 from its lower surface. In this case, it is necessary that the substrate 75 and the support base 73 have good thermal contact. After the cooling process is completed, the pressure inside the container 71 is returned to atmospheric pressure, and the substrate 75 is opened via the on-off valve 72b.
is taken out into the container 71. Thereafter, the substrate 75 is transported to a processing section for the next step.
なお、本装置は枚葉式の処理方法を採用してい
るので、状況によつては減圧ベーク・昇圧冷却器
の部分における処理時間が長くなつて、他の部分
との処理時間のバランスを崩し、高スループツト
化がはかれない場合も生じ得る。このような場合
には、該減圧ベーク・昇圧冷却器を冷えばサーク
ル状若しくは並列状に複数個配置し、他の処理時
間及びベーク・冷却処理時間を考慮した適正な遅
延時間を設定して、サークル的若しくは並列的に
ベーク・冷却処理を行なうことにより、装置全体
としての高スループツト化をはかることが可能で
ある。さらには、減圧ベーク・昇圧冷却器を所定
許容範囲内で大型化し、該部分だけをバツチ処理
方式にすることもできる。また、レジスト膜ベー
ク後の冷却手段として、レジスト膜面全体に温度
及び流量が均一制御された冷風を吹き付けるよう
にしてもよい。この場合の冷却は、減圧状態の容
器７１内の圧力を大気に戻すプロセスと併用させ
ることができる。 Please note that this equipment uses a single-wafer processing method, so depending on the situation, the processing time for the vacuum baking/boosting cooler section may take longer, which may upset the balance of processing time with other sections. However, there may be cases where high throughput cannot be achieved. In such a case, a plurality of the vacuum baking/boosting coolers are arranged in a circle or in parallel, and an appropriate delay time is set in consideration of other processing times and baking/cooling processing times. By performing the baking and cooling processes in a circular manner or in parallel, it is possible to increase the throughput of the entire apparatus. Furthermore, it is also possible to increase the size of the vacuum baking/boosting cooler within a predetermined tolerance range and to use a batch processing method for only that portion. Further, as a cooling means after baking the resist film, cold air whose temperature and flow rate are uniformly controlled may be blown onto the entire surface of the resist film. Cooling in this case can be combined with a process in which the pressure inside the reduced pressure container 71 is returned to the atmosphere.
その他、本発明の要旨を逸脱しない範囲で、
種々変形して実施することができる。 In addition, without departing from the gist of the present invention,
Various modifications can be made.
第１図は従来のレジストパターン形成工程を概
略的に示す流れ作業図、第２図は従来工程におけ
るレジストベーク後の被処理基板の各点の温度変
化の様子を等温曲線で示す模式図、第３図は前記
温度変化の様子を時間対温度曲線で示す特性図、
第４図は本発明によるレジストパターン形成工程
を概略的に示す流れ作業図、第５図はレジスト冷
却速度を示す特性図、第６図はレジスト感度を示
す特性図、第７図は本発明方法に適合するレジス
ト処理装置の一例を示す断面図である。
７１……処理容器、７２ａ，７２ｂ……開閉バ
ルブ、７３……支持台、７４……レジスト膜、７
５……基板、７６……冷媒通孔、７７……ヒー
タ、７８……圧力制御用管。
Figure 1 is a flowchart schematically showing a conventional resist pattern forming process, Figure 2 is a schematic diagram showing isothermal curves of temperature changes at various points on the substrate after resist baking in the conventional process; Figure 3 is a characteristic diagram showing the state of the temperature change as a time vs. temperature curve;
FIG. 4 is a flow chart schematically showing the resist pattern forming process according to the present invention, FIG. 5 is a characteristic diagram showing the resist cooling rate, FIG. 6 is a characteristic diagram showing resist sensitivity, and FIG. 7 is a method of the present invention. 1 is a cross-sectional view showing an example of a resist processing apparatus suitable for the. 71...Processing container, 72a, 72b...Opening/closing valve, 73...Support stand, 74...Resist film, 7
5... Board, 76... Refrigerant hole, 77... Heater, 78... Pressure control tube.
Claims (1)
たのち冷却し、さらに所定波長の電磁波或いは所
定エネルギの粒子線を上記レジストに選択的に照
射し、現像処理を施すことによりレジストパター
ンを形成する方法において、前記レジストのベー
ク及び冷却の少くとも一方を常圧より低い圧力下
で行うことを特徴とするレジストパターン形成方
法。 ２ 前記レジストの冷却として、冷却時間若しく
は冷却速度を制御しながら、ベーク温度Tbから
最終冷却温度Tcまで均一に行うことを特徴とす
る特許請求の範囲第１項記載のレジストパターン
形成方法。 ３ 前記レジストの冷却を急冷により行なうこと
を特徴とする特許請求の範囲第１項記載のレジス
トパターン形成方法。[Claims] 1. By applying a resist onto a substrate to be processed, baking it, cooling it, and selectively irradiating the resist with an electromagnetic wave of a predetermined wavelength or a particle beam of a predetermined energy, and performing a development process. A method for forming a resist pattern, characterized in that at least one of baking and cooling the resist is performed under a pressure lower than normal pressure. 2. The resist pattern forming method according to claim 1, wherein the resist is cooled uniformly from a bake temperature Tb to a final cooling temperature Tc while controlling a cooling time or a cooling rate. 3. The resist pattern forming method according to claim 1, wherein the resist is cooled by rapid cooling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58128912A JPS6021522A (en) | 1983-07-15 | 1983-07-15 | Formation of resist pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58128912A JPS6021522A (en) | 1983-07-15 | 1983-07-15 | Formation of resist pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6021522A JPS6021522A (en) | 1985-02-02 |
| JPH0546091B2 true JPH0546091B2 (en) | 1993-07-13 |
Family
ID=14996435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58128912A Granted JPS6021522A (en) | 1983-07-15 | 1983-07-15 | Formation of resist pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6021522A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR860002082B1 (en) * | 1983-01-19 | 1986-11-24 | 가부시기가이샤 도시바 | Forming method and apparatus of resistor pattern |
| DE3689606T2 (en) * | 1985-10-22 | 1994-05-19 | Kuraray Co | Manufacturing method for composite pattern refraction type phase gratings. |
| JPS63107116A (en) * | 1986-10-24 | 1988-05-12 | Fujitsu Ltd | Resist baking method |
| JPS63161803U (en) * | 1987-04-10 | 1988-10-21 | ||
| JPS63259559A (en) * | 1987-04-16 | 1988-10-26 | Hitachi Condenser Co Ltd | Pattern forming method for printed circuit board |
| JPH01133621U (en) * | 1988-02-29 | 1989-09-12 | ||
| CA2183163C (en) * | 1994-12-28 | 2006-08-08 | Yoshiyuki Kitamura | Coating method and coating apparatus |
| EP1592053B1 (en) | 2003-02-05 | 2011-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Wiring fabricating method |
| JP5767991B2 (en) * | 2012-03-23 | 2015-08-26 | カヤバ工業株式会社 | Fluid pressure cylinder |
-
1983
- 1983-07-15 JP JP58128912A patent/JPS6021522A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6021522A (en) | 1985-02-02 |
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