JPH0536856A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0536856A JPH0536856A JP19047391A JP19047391A JPH0536856A JP H0536856 A JPH0536856 A JP H0536856A JP 19047391 A JP19047391 A JP 19047391A JP 19047391 A JP19047391 A JP 19047391A JP H0536856 A JPH0536856 A JP H0536856A
- Authority
- JP
- Japan
- Prior art keywords
- package
- socket
- recess
- semiconductor device
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Connecting Device With Holders (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
半導体集積回路パッケージと半導体集積回路用ソケット
にて構成される半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device composed of a semiconductor integrated circuit package and a semiconductor integrated circuit socket.
【０００２】[0002]
【従来の技術】従来の半導体装置はＰｉｎ Ｇｒｉｄ
Ａｒｒａｙ（以下ＰＧＡと記す）式のパッケージでは、
図６に示すように、半導体集積回路パッケージ（以下Ｉ
Ｃパッケージと記す）を中心にして非点対称な位置に誤
挿入防止ピン６を設けることによって、物理的に装着作
業者の誤挿入を防いでいるが、他の方式のＩＣパッケー
ジでは、図７に示すように、ＩＣパッケージ２１の向き
を示す標識７を設けるのみであった。2. Description of the Related Art A conventional semiconductor device is a Pin Grid.
Array (hereinafter referred to as PGA) type package,
As shown in FIG. 6, a semiconductor integrated circuit package (hereinafter referred to as I
The erroneous insertion prevention pin 6 is provided at a position asymmetric with respect to the C package) to physically prevent erroneous insertion by the mounting operator. As shown in FIG. 5, only the mark 7 indicating the orientation of the IC package 21 was provided.
【０００３】[0003]
【発明が解決しようとする課題】従来のＩＣパッケージ
を半導体集積回路用ソケット（以下ＩＣソケットと記
す）に装着する際、ＩＣパッケージの向きを示す標識
は、ＩＣパッケージに具備されているが、ＰＧＡ式パッ
ケージ以外のＩＣパッケージは、物理的に誤挿入を防止
するものは備えていなかった。このため、作業者の人為
的なミスによる誤挿入の危険性が残されており、動作不
良やシステム破壊などの原因になるという欠点がある。When a conventional IC package is mounted in a semiconductor integrated circuit socket (hereinafter referred to as an IC socket), the IC package has a mark indicating the orientation of the IC package. The IC packages other than the formula package did not have a physical one for preventing erroneous insertion. Therefore, there is a risk of incorrect insertion due to an operator's human error, and there is a drawback that it may cause a malfunction or a system breakdown.
【０００４】本発明の目的は、誤挿入を防止し、動作不
良やシステム破壊のないＩＣパッケージとＩＣソケット
によって構成される半導体装置を提供することにある。It is an object of the present invention to provide a semiconductor device which is configured by an IC package and an IC socket, which prevents erroneous insertion and is free from malfunction and system destruction.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
裏面の所定の位置に少くとも１個の所定の形状の凹部を
形成した半導体集積回路パッケージと、前記裏面と対向
する面の前記凹部と対応する位置に前記凹部と嵌合する
凸部を設けた半導体集積回路用ソケットとを有する。The semiconductor device of the present invention comprises:
A semiconductor integrated circuit package in which at least one recess having a predetermined shape is formed at a predetermined position on the back surface, and a projection which fits the recess is provided at a position corresponding to the recess on the surface facing the back surface. And a semiconductor integrated circuit socket.
【０００６】[0006]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００７】図１は本発明の第１の実施例のＩＣパッケ
ージをＩＣソケットへ装着する方法を説明する斜視図、
図２は本発明の第１の実施例の断面図である。ＩＣパッ
ケージ１は裏面，ＩＣソケット２は上面が見えている状
態を示している。FIG. 1 is a perspective view for explaining a method of mounting the IC package of the first embodiment of the present invention on an IC socket,
FIG. 2 is a sectional view of the first embodiment of the present invention. The back surface of the IC package 1 and the top surface of the IC socket 2 are shown.
【０００８】第１の実施例は、図１に示すように、ＩＣ
パッケージ１に具備されている凹部３は、ＩＣパッケー
ジ１の中心以外の位置に配置されており、ＩＣソケット
２に具備されている凸部４は、ＩＣパッケージ１の凹部
３と対応する位置に嵌合するように配置されている。従
って、この向きにＩＣパッケージ１をＩＣソケット２に
装着する場合、図２に示すように、ＩＣパッケージ１の
凹部３がＩＣソケット２の凸部に嵌合するが、逆向きに
ＩＣパッケージ１をＩＣソケット２に装着しようとした
場合、凸部４が装着を物理的に防止することにより装着
作業者のミスを防ぐことができる。In the first embodiment, as shown in FIG.
The recess 3 provided in the package 1 is arranged at a position other than the center of the IC package 1, and the projection 4 provided in the IC socket 2 is fitted in a position corresponding to the recess 3 of the IC package 1. It is arranged to meet. Therefore, when the IC package 1 is mounted in the IC socket 2 in this direction, the recess 3 of the IC package 1 fits into the projection of the IC socket 2 as shown in FIG. 2, but the IC package 1 is mounted in the opposite direction. When the IC socket 2 is to be mounted, the convex portion 4 physically prevents the mounting, so that the mounting operator's mistake can be prevented.
【０００９】図３は本発明の第２の実施例のＩＣパッケ
ージ本体の斜視図である。FIG. 3 is a perspective view of an IC package body according to the second embodiment of the present invention.
【００１０】第２の実施例は、図３に示すように、三角
形状の凹部３ａを設けた例である。三角形状の凹部３ａ
がＩＣパッケージ本体５の所定の位置にあっても、形状
が非点対称であれば、第１の実施例と同様な効果が得ら
れることは明らかである。The second embodiment is an example in which a triangular recess 3a is provided as shown in FIG. Triangular recess 3a
It is clear that, even if is in a predetermined position of the IC package body 5, if the shape is non-point symmetric, the same effect as that of the first embodiment can be obtained.
【００１１】図４は本発明の第３の実施例のＩＣパッケ
ージ本体の斜視図、図５は本発明の第４の実施例のＩＣ
パッケージ本体の斜視図である。FIG. 4 is a perspective view of an IC package body according to the third embodiment of the present invention, and FIG. 5 is an IC according to the fourth embodiment of the present invention.
It is a perspective view of a package body.
【００１２】これまでに述べた実施例は、凹部が１つの
みであったが、図４に示すように凹部３ｂ，３ｃ，３ｄ
がＩＣパッケージ本体５の裏面中心に対し非点対称な位
置に、２つ以上の所定の数を配置しても、また、図５に
示すように所定の位置に二種類以上の大きさまたは形状
の違う凹部３ｅ，３ｆを備えても、同様の効果が得られ
ることは明らかである。Although the embodiment described so far has only one recess, as shown in FIG. 4, the recesses 3b, 3c and 3d are provided.
Even if a predetermined number of two or more are arranged in a position that is not point-symmetrical with respect to the center of the back surface of the IC package body 5, as shown in FIG. It is obvious that the same effect can be obtained even if the concave portions 3e and 3f having different shapes are provided.
【００１３】更に、非点対称な形状の凹部が、２つ以上
の数で位置する場合も、同様の効果が得られることは明
らかである。Further, it is obvious that the same effect can be obtained when the non-point-symmetrical recesses are located by two or more.
【００１４】以上のように、ＩＣパッケージの凹部につ
いてのみ述べたが、貫通孔にしても同様の効果が得られ
ることは明らかである。As described above, only the concave portion of the IC package has been described, but it is clear that the same effect can be obtained by using the through hole.
【００１５】また、これまではＤｕａｌ Ｉｎｌｉｎｅ
Ｐａｃｋａｇｅ（ＤＩＰ）式パッケージについてのみ
述べたが、ＱＵＩＰ等他方式のパッケージでも同様の効
果が得られることは明らかである。Until now, the Dual Inline has been used.
Although only the Package (DIP) type package has been described, it is clear that the same effect can be obtained with a package of another method such as QUIIP.
【００１６】[0016]
【発明の効果】以上の説明で明らかな如く、本発明の半
導体装置は、ＩＣパッケージの裏面に、所定の形状の凹
部または貫通孔を所定の位置に少なくとも１つ以上の所
定の数を具備し、ＩＣソケットには、前記パッケージの
凹部または貫通孔と対応する位置に嵌合する形状の凸部
を具備することにより、物理的に誤挿入を防止すること
ができるという効果を有する。As is clear from the above description, the semiconductor device of the present invention has a predetermined number of at least one recessed portion or through hole at a predetermined position on the back surface of the IC package. By providing the IC socket with a protrusion having a shape that fits in a position corresponding to the recess or the through hole of the package, it is possible to physically prevent erroneous insertion.
【図１】本発明の第１の実施例のＩＣパッケージをＩＣ
ソケットへ装着する方法を説明する斜視図である。FIG. 1 is an IC package of a first embodiment of the present invention.
It is a perspective view explaining the method of attaching to a socket.
【図２】本発明の第１の実施例の断面図である。FIG. 2 is a sectional view of the first embodiment of the present invention.
【図３】本発明の第２の実施例のＩＣパッケージ本体の
斜視図である。FIG. 3 is a perspective view of an IC package body according to a second embodiment of the present invention.
【図４】本発明の第３の実施例のＩＣパッケージ本体の
斜視図である。FIG. 4 is a perspective view of an IC package body according to a third embodiment of the present invention.
【図５】本発明の第４の実施例のＩＣパッケージ本体の
斜視図である。FIG. 5 is a perspective view of an IC package body according to a fourth embodiment of the present invention.
【図６】従来の半導体装置のＩＣパッケージの一例の斜
視図である。FIG. 6 is a perspective view of an example of an IC package of a conventional semiconductor device.
【図７】従来の半導体装置のＩＣパッケージの他の例の
斜視図である。FIG. 7 is a perspective view of another example of an IC package of a conventional semiconductor device.
１，１１，２１ ＩＣパッケージ ２ ＩＣソケット ３，３ａ，３ｂ，３ｃ，３ｅ，３ｆ 凹部 ４ 凸部 ５ ＩＣパッケージ本体 ６ 誤挿入防止ピン ７ 標識 1,11,21 IC package 2 IC socket 3,3a, 3b, 3c, 3e, 3f Recess 4 convex 5 IC package body 6 Incorrect insertion prevention pin 7 signs
Claims (2)
の形状の凹部を形成した半導体集積回路パッケージと、
前記裏面と対向する面の前記凹部と対応する位置に前記
凹部と嵌合する凸部を設けた半導体集積回路用ソケット
とを有することを特徴とする半導体装置。1. A semiconductor integrated circuit package in which at least one recess having a predetermined shape is formed at a predetermined position on the back surface.
A semiconductor device comprising: a semiconductor integrated circuit socket provided with a convex portion that fits into the concave portion at a position corresponding to the concave portion on a surface facing the back surface.
る請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the recess is a through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19047391A JPH0536856A (en) | 1991-07-31 | 1991-07-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19047391A JPH0536856A (en) | 1991-07-31 | 1991-07-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0536856A true JPH0536856A (en) | 1993-02-12 |
Family
ID=16258700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19047391A Pending JPH0536856A (en) | 1991-07-31 | 1991-07-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0536856A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6624508B2 (en) * | 2000-01-03 | 2003-09-23 | Sophia Wireless, Inc. | High frequency, low cost package for semiconductor devices |
-
1991
- 1991-07-31 JP JP19047391A patent/JPH0536856A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6624508B2 (en) * | 2000-01-03 | 2003-09-23 | Sophia Wireless, Inc. | High frequency, low cost package for semiconductor devices |
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