JPH0535824A - Inter-layer orthogonal wiring inspection system - Google Patents
Inter-layer orthogonal wiring inspection systemInfo
- Publication number
- JPH0535824A JPH0535824A JP3189666A JP18966691A JPH0535824A JP H0535824 A JPH0535824 A JP H0535824A JP 3189666 A JP3189666 A JP 3189666A JP 18966691 A JP18966691 A JP 18966691A JP H0535824 A JPH0535824 A JP H0535824A
- Authority
- JP
- Japan
- Prior art keywords
- noise
- line
- parasitic capacitance
- net
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はプリント基板の配線設計
における層間直交配線検査方式に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-layer orthogonal wiring inspection method in printed wiring board design.
【０００２】[0002]
【従来の技術】従来、この種の層間直交配線検査方式
は、被雑音ネットに対して同時に寄生容量を与える雑音
線群のみを見つけ、その雑音線群が被雑音ネットに与え
る寄生容量の合計が許容値を超えるか否か判断してい
た。2. Description of the Related Art Conventionally, this type of inter-layer orthogonal wiring inspection method finds only a noise line group which simultaneously gives a parasitic capacitance to a noise net, and the total parasitic capacitance given to the noise net by the noise line group is It was determined whether or not the allowable value was exceeded.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の送還直
交配線検査方式では、被雑音ネットに与える寄生容量の
合計が許容値を超えるか否か判断しており、同時に寄生
容量を与えるとみなされる雑音線群を考慮しないため、
正確な検査対象の寄生容量の合計を得ることができず、
検査の正確さに欠けていた。In the above-mentioned conventional transmission orthogonal wiring inspection method, it is judged whether or not the total parasitic capacitance given to the noise net exceeds an allowable value, and it is considered that the parasitic capacitance is given at the same time. Since the noise line group is not considered,
It is not possible to obtain the accurate total parasitic capacitance of the test target,
The inspection was lacking in accuracy.
【０００４】[0004]
【課題を解決するための手段】本発明の層間直交配線検
査方式は、複数のネットが互いに影響を与える層間直交
配線の検査方式であって、雑音線ネット（雑音を与える
ネット）中の配線（雑音線）の直交一箇所当りの寄生要
領、直交して配線された前記雑音線の制限本数、前記寄
生容量の許容値を入力する雑音線情報入力手段と、被雑
音線ネット（雑音を受けるネット）に他線で直交する前
記雑音線の総数を求める雑音線本数算出手段と、前記直
交する雑音線の総数が制限本数を超えたネットについて
被雑音線（前記被雑音線ネット中の配線）の全ロードピ
ンに対し各雑音線から寄生容量を受けるタイミングを求
めるタイミング算出手段と、前記各雑音線について前記
被雑音線ネットに同時に前記寄生容量を与えるとみなさ
れる前記タイミングの範囲を設定するタイミング範囲設
定手段と、このタイミング範囲設定手段により設定され
た範囲で同時に前記寄生容量を与えるとみなされる雑音
線群を発見する雑音線群発見手段と、前記雑音線群が前
記被雑音線ネット内の前記全ロードピンに与える寄生容
量の合計について前記同時に寄生容量を与えるとみなさ
れるタイミングの範囲を考慮して算出する寄生容量算出
手段と、この寄生容量算出手段により算出された前記寄
生容量の合計値が許容量を超えているか否か判断する許
容量検査手段と、前記寄生容量の合計値が許容量を超え
ているネットについてエラー情報を出力するエラー情報
出力手段とを備えている。An inter-layer orthogonal wiring inspection system of the present invention is an inter-layer orthogonal wiring inspection system in which a plurality of nets influence each other, and a wiring in a noise line net (noise-providing net) ( (Noise line) Parasitic procedure per one point, noise line information input means for inputting the limit number of the noise lines wired in the orthogonal direction, and the allowable value of the parasitic capacitance, and the noisy line net (the net that receives noise) ) To calculate the total number of noise lines that are orthogonal to another line, and for a net in which the total number of orthogonal noise lines exceeds the limit number of noise-free lines (wiring in the noise-free line net) Timing calculating means for determining the timing of receiving parasitic capacitance from each noise line with respect to all load pins, and the timing which is considered to simultaneously give the parasitic capacitance to the noise-free line net for each noise line. And a noise line group finding means for finding a noise line group considered to give the parasitic capacitance at the same time in the range set by the timing range setting means, and the noise line group is Parasitic capacitance calculating means for calculating the total of parasitic capacitances to be applied to all the load pins in the noise-free line net in consideration of the range of timings at which the parasitic capacitances are simultaneously given, and the parasitic capacitance calculating means for calculating the parasitic capacitances. And a tolerance inspection unit for determining whether or not the total value of the parasitic capacitances exceeds the allowable amount, and an error information output unit for outputting error information for a net in which the total value of the parasitic capacitances exceeds the allowable amount. There is.
【０００５】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【０００６】図１は本発明の層間直交配線検査方式の一
実施例を実現する流れ図である。FIG. 1 is a flow chart for realizing an embodiment of an inter-layer orthogonal wiring inspection system of the present invention.
【０００７】処理ボックス１０１では、雑音線ネット中
の雑音線の直交１箇所当りの寄生容量を直交して配線さ
れた雑音線の制限本数及び寄生容量の許容値を入力す
る。In the processing box 101, the parasitic capacitance per orthogonal position of the noise line in the noise line net is input with the limit number of noise lines wired orthogonally and the allowable value of the parasitic capacitance.
【０００８】処理ボックス１０２では、検査対象のネッ
トを被雑音ネットとして１つ取り出す。In the processing box 102, one net to be inspected is taken out as a noise-free net.
【０００９】判断ボックス１０３では、全ネットについ
て被雑音ネットとして検査を行ったか否か判断し、全ネ
っトについて検査を行った場合には、処理を終了する。
また、検査を行っていないネットが存在する場合には、
処理ボックス１０４へ移行する。In the judgment box 103, it is judged whether or not all nets have been inspected as noise-free nets, and if all nets have been inspected, the process is terminated.
Also, if there is a net that has not been inspected,
The process moves to the processing box 104.
【００１０】処理ボックス１０４では、被雑音ネット中
の任意の配線経路に同一ペア層内多層で直交する全ての
雑音線の総数とネット名を求める。In the processing box 104, the total number and net names of all noise lines that are orthogonal to each other in an arbitrary wiring path in the noise-free net in the same pair layer are obtained.
【００１１】判断ボックス１０５では、処理ボックス１
０４で求めた雑音数の総数が制限値を超えているか否か
判断し、制限値を超えていないときは、処理ボックス１
１２へ移行し処理を繰り返す。制限値を超えているとき
は、処理ボックス１０６へ移行する。In the judgment box 105, the processing box 1
It is judged whether or not the total number of noises obtained in 04 exceeds the limit value, and if it does not exceed the limit value, the processing box 1
The process moves to 12 and the process is repeated. If the limit value is exceeded, the process box 106 is entered.
【００１２】処理ボックス１０６では、直交する雑音線
の総数が制限値を超えたネットについて、被雑音線の全
ロードピンに対し各雑音線から寄生容量を受けるタイミ
ングを算出する。In the processing box 106, for a net in which the total number of orthogonal noise lines exceeds the limit value, the timing of receiving parasitic capacitance from each noise line with respect to all load pins of the noise receiving line is calculated.
【００１３】処理ボックス１０７では、各雑音線からの
寄生容量が乗るタイミングについて、同一タイミングと
みなされる時間幅を設定する。In the processing box 107, the time width considered to be the same timing is set for the timing at which the parasitic capacitance from each noise line is added.
【００１４】処理ボックス１０８では、処理ボックス１
０７で設定された時間幅内の雑音線群を発見する。In the processing box 108, the processing box 1
A noise line group within the time width set in 07 is found.
【００１５】処理ボックス１０９では、処理ボックス１
０８で発見した雑音線群から任意の時間ｔｍに対し、ｔ
ｍ±△Ｔ（△Ｔは同一タイミングとみなされる時間幅）
の範囲内で被雑音ネット内の全ロードピンが受ける寄生
容量の合計を、例えば、次式を用いて算出する。In the processing box 109, the processing box 1
From the noise line group found in 08, t
m ± ΔT (ΔT is the time width considered to be the same timing)
The total parasitic capacitance received by all the load pins in the noise net within the range is calculated using, for example, the following formula.
【００１６】 [0016]
【００１７】ここで、Ｖは１個所の直交で受ける寄生容
量、ｔｉは任意の時間ｔｍ±△Ｔの範囲内にある時間を
それぞれ示す。Here, V represents a parasitic capacitance received at one orthogonal position, and ti represents a time within an arbitrary time tm ± ΔT.
【００１８】判断ボックス１１０では、処理ボックス１
０９で求めた被雑音ネット内の全ロードピンの受ける寄
生容量の合計が、寄生容量の許容値を超えているか否か
判断し、許容値を超えていないときは、処理ボックス１
１２へ移行し処理を繰り返す。また、許容値を超えたと
きは、処理ボックス１１１へ移行する。In the judgment box 110, the processing box 1
It is determined whether or not the total parasitic capacitance received by all load pins in the noisy net in step 09 exceeds the allowable value of the parasitic capacitance. If not, the processing box 1
The process moves to 12 and the process is repeated. If the allowable value is exceeded, the process box 111 is entered.
【００１９】処理ボックス１１１では、ネット毎に信号
種別，直交セグメント数，制限値，寄生容量および寄生
容量の許容値等の検査結果を出力する。The processing box 111 outputs the inspection result such as the signal type, the number of orthogonal segments, the limit value, the parasitic capacitance and the allowable value of the parasitic capacitance for each net.
【００２０】処理ボックス１１２では、処理ボックス１
１１と同様に、検査に要した各情報を出力する。In the processing box 112, the processing box 1
Similar to 11, each information required for the inspection is output.
【００２１】図２は寄生容量を受けるタイミングの算出
を説明する概念図である。FIG. 2 is a conceptual diagram for explaining the calculation of the timing of receiving the parasitic capacitance.
【００２２】雑音線２２のソースピンＳ2 からの信号が
被雑音線２１との交点で雑音線２１にノイズとして移
り、被雑音線２１のロードピンＬ1まで到達したときの
配線長をａ1 ＋ｂ1 、雑音線２２のソースピンＳ2 から
の信号が被雑音線２１との交点と通過し、雑音線２２の
ロードピンＬ2 で反射した後、交点で被雑音線２１にノ
イズとして移り、被雑音線２１のロードピンＬ1 まで到
達したときの配線町をａ1 ＋ｂ1 ，ａ1 ＋ｂ1 ＋２
ｃ1 ，ａ2 ＋ｂ2 ，ａ2 ＋ｂ2 ＋２ｃ2 に単位線長当た
りの遅延時間を考え合せた４種類のタイミングを被雑音
線２１は寄生容量を受けると考えられ、図３を参照して
寄生容量の算出を説明する。The signal length from the source pin S 2 of the noise line 22 moves to the noise line 21 as noise at the intersection with the noise line 21 and reaches the load pin L 1 of the noise line 21 when the wiring length is a 1 + b. 1. The signal from the source pin S 2 of the noise wire 22 passes through the intersection with the noise-bearing wire 21 and is reflected by the load pin L 2 of the noise wire 22 and then moves to the noise-bearing wire 21 as noise at the intersection, The wiring towns when reaching the load pin L 1 of the line 21 are a 1 + b 1 , a 1 + b 1 +2
It is considered that the noise sensitive line 21 receives the parasitic capacitance at four types of timings in which c 1 , a 2 + b 2 , a 2 + b 2 + 2c 2 are combined with the delay time per unit line length, and referring to FIG. The calculation of the parasitic capacitance will be described.
【００２３】時間ｔｓからｔｇ（ｔｍ±△Ｔ）の各々の
タイミングで受ける寄生容量の各々Each parasitic capacitance received at each timing from time ts to tg (tm ± ΔT)
【００２４】 [0024]
【００２５】に△Ｔを考慮して算出した寄生容量Parasitic capacitance calculated in consideration of ΔT
【００２６】 [0026]
【００２７】が寄生容量の許容値を超えている場合には
エラーとして出力する。When exceeds the allowable value of the parasitic capacitance, an error is output.
【００２８】[0028]
【発明の効果】以上説明したように本発明は、被雑音線
の全ロードピンに対し、各雑音線からの寄生容量が乗る
タイミングを求め、同時に寄生容量が乗るとみなされる
タイミングの範囲を考慮し、かつ同時に寄生容量を与え
るとみなされる雑音線群を考慮しているため、より正確
な検査対象の寄生容量を得ることができ、正確な検査が
できるという効果がある。As described above, according to the present invention, the timing at which the parasitic capacitance from each noise line gets on all the load pins of the noise receiving line is obtained, and the range of the timing at which the parasitic capacitance is considered to get on at the same time is considered. Since the noise line group that is considered to give the parasitic capacitance at the same time is taken into consideration, there is an effect that a more accurate parasitic capacitance of the inspection target can be obtained and an accurate inspection can be performed.
【図１】本発明の層間直交配線検査方式の一実施例を実
現する流れ図である。FIG. 1 is a flow chart for realizing an embodiment of an inter-layer orthogonal wiring inspection system of the present invention.
【図２】寄生容量を受けるタイミングの算出を説明する
概念図である。FIG. 2 is a conceptual diagram illustrating calculation of a timing of receiving a parasitic capacitance.
【図３】各タイミングで被雑音ネットが受ける寄生容量
を示す図である。FIG. 3 is a diagram showing a parasitic capacitance received by a noise net at each timing.
２１ 被雑音線 ２２，２３ 雑音線 Ｓ1 〜Ｓ3 ソースピン Ｌ1 〜Ｌ3 ロードピン ａ1 ，ａ2 被雑音線と雑音線との交点からソースピ
ンまでの配線長 ｂ1 ，ｂ2 交点から被雑音線のロードピンまでの配
線長 ｃ1 ，ｃ2 交点から雑音線のロードピンまでの配線
長21 Noisy line 22,23 Noise line S 1 to S 3 Source pin L 1 to L 3 Load pin a 1 and a 2 Wiring length from the intersection of the noise sensitive line and the noise line to the source pin b 1 and b 2 From the intersection the wiring length of the wiring length c 1, c 2 intersections up to the load pin of the noise line to load pin of the noise line
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/00 Ｄ 6921−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05K 3/00 D 6921-4E
Claims (1)
直交配線の検査方式であって、雑音線ネット（雑音を与
えるネット）中の配線（雑音線）の直交一箇所当りの寄
生要領、直交して配線された前記雑音線の制限本数、前
記寄生容量の許容値を入力する雑音線情報入力手段と、
被雑音線ネット（雑音を受けるネット）に他線で直交す
る前記雑音線の総数を求める雑音線本数算出手段と、前
記直交する雑音線の総数が制限本数を超えたネットにつ
いて被雑音線（前記被雑音線ネット中の配線）の全ロー
ドピンに対し各雑音線から寄生容量を受けるタイミング
を求めるタイミング算出手段と、前記各雑音線について
前記被雑音線ネットに同時に前記寄生容量を与えるとみ
なされる前記タイミングの範囲を設定するタイミング範
囲設定手段と、このタイミング範囲設定手段により設定
された範囲で同時に前記寄生容量を与えるとみなされる
雑音線群を発見する雑音線群発見手段と、前記雑音線群
が前記被雑音線ネット内の前記全ロードピンに与える寄
生容量の合計について前記同時に寄生容量を与えるとみ
なされるタイミングの範囲を考慮して算出する寄生容量
算出手段と、この寄生容量算出手段により算出された前
記寄生容量の合計値が許容量を超えているか否か判断す
る許容量検査手段と、前記寄生容量の合計値が許容量を
超えているネットについてエラー情報を出力するエラー
情報出力手段とを備えることを特徴とする層間直交配線
検査方式。Claim: What is claimed is: 1. An inspection method of an inter-layer orthogonal wiring in which a plurality of nets influence each other, and a wiring (noise line) in a noise line net (noise-providing net) is per orthogonal position. Parasitic points, noise line information input means for inputting the limit number of the noise lines wired orthogonally, and the allowable value of the parasitic capacitance,
Noise line number calculation means for obtaining the total number of the noise lines orthogonal to the noise-received line net (net that receives noise) by another line, and noise-sensitive lines (for the net where the total number of the orthogonal noise lines exceeds the limit number) Timing calculating means for determining the timing of receiving the parasitic capacitance from each noise line for all load pins of (the wiring in the noise-bearing line net); A timing range setting means for setting a timing range; a noise line group finding means for finding a noise line group considered to give the parasitic capacitance at the same time in the range set by the timing range setting means; The timing of the total parasitic capacitance given to all the load pins in the noise net is considered to give the parasitic capacitance at the same time. Of the parasitic capacitance calculation means for calculating in consideration of the range of, the allowable amount inspection means for determining whether the total value of the parasitic capacitance calculated by the parasitic capacitance calculation means exceeds the allowable amount, An inter-layer orthogonal wiring inspection method, comprising: error information output means for outputting error information for a net whose total value exceeds an allowable amount.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3189666A JPH0535824A (en) | 1991-07-30 | 1991-07-30 | Inter-layer orthogonal wiring inspection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3189666A JPH0535824A (en) | 1991-07-30 | 1991-07-30 | Inter-layer orthogonal wiring inspection system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0535824A true JPH0535824A (en) | 1993-02-12 |
Family
ID=16245146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3189666A Pending JPH0535824A (en) | 1991-07-30 | 1991-07-30 | Inter-layer orthogonal wiring inspection system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0535824A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001082145A1 (en) * | 2000-04-21 | 2001-11-01 | Hitachi, Ltd. | Crosstalk analysis method, method for designing/manufacturing electronic circuit device by using the same, and recorded medium of electronic circuit library therefor |
-
1991
- 1991-07-30 JP JP3189666A patent/JPH0535824A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001082145A1 (en) * | 2000-04-21 | 2001-11-01 | Hitachi, Ltd. | Crosstalk analysis method, method for designing/manufacturing electronic circuit device by using the same, and recorded medium of electronic circuit library therefor |
| US6772403B1 (en) | 2000-04-21 | 2004-08-03 | Hitachi, Ltd. | Crosstalk analysis method, method for designing/manufacturing electronic circuit device by using the same, and recorded medium of electronic circuit library therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5027353A (en) | Method for testing interconnections | |
| US5751597A (en) | CAD apparatus for LSI or printed circuit board | |
| US5912985A (en) | Pattern detection method | |
| JPH0535824A (en) | Inter-layer orthogonal wiring inspection system | |
| EP1643356A1 (en) | Parallel processing device and parallel processing method | |
| US20180321792A1 (en) | Compensation method for an induced amount in a touch sensor and touch panel thereof | |
| JP2987565B2 (en) | Pattern inspection method and pattern inspection device | |
| JP2868009B1 (en) | Delay calculation device, delay calculation method, and recording medium storing delay calculation program | |
| US5353905A (en) | Coin sorting device | |
| JP3076227B2 (en) | Crosstalk error detector | |
| JPH09258840A (en) | Clock distributing circuit | |
| JPH07159344A (en) | Inspection device for periodic pattern | |
| JP2006323638A (en) | Circuit arrangement device, circuit arrangement method and program executing it | |
| JP2003288381A (en) | Method and device for verifying crosstalk noise quantity | |
| JPS6359442B2 (en) | ||
| JPH06243197A (en) | Cad system for lsi printed circuit board | |
| JP3134838B2 (en) | Wiring device between blocks | |
| JP3087319B2 (en) | Timing verification system | |
| JPH08221460A (en) | Circuit simulation method and inter-wiring capacity extraction device | |
| JP2551319B2 (en) | Video processing method | |
| JPH04279976A (en) | Interactive layout correcting system | |
| JP2853660B2 (en) | Wiring processing equipment | |
| JPH0619219Y2 (en) | Programmable delay circuit | |
| JP4008643B2 (en) | Method of operating printed circuit board design apparatus | |
| JP3171914B2 (en) | IC test equipment |