JPH05343606A - Multi chip module - Google Patents
Multi chip moduleInfo
- Publication number
- JPH05343606A JPH05343606A JP4147023A JP14702392A JPH05343606A JP H05343606 A JPH05343606 A JP H05343606A JP 4147023 A JP4147023 A JP 4147023A JP 14702392 A JP14702392 A JP 14702392A JP H05343606 A JPH05343606 A JP H05343606A
- Authority
- JP
- Japan
- Prior art keywords
- wafer substrate
- chip
- chip module
- silicone wafer
- bare
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、コンピュータ装置、高
速伝送装置などにおいて用いられるＬＳＩなどの集積回
路の実装に適用されるマルチチップモジュールの構造に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a multi-chip module applied to mounting an integrated circuit such as an LSI used in a computer device, a high speed transmission device and the like.
【０００２】[0002]
【従来の技術】従来、この種のマルチチップ実装構造で
は、ガラス−エポキシンに代表されるプリント回路基板
に樹脂モールドＬＳＩあるいはセラミック等に封止され
たセラミックパッケージが複数個搭載される構造となっ
ている。2. Description of the Related Art Conventionally, a multi-chip mounting structure of this type has a structure in which a plurality of ceramic packages sealed with resin-molded LSI or ceramics are mounted on a printed circuit board typified by glass-epoxy. There is.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の実装構
造では、プリント回路基板の微細化加工に限界があるこ
と、およびＬＳＩが各々専用のパッケージに封止された
状態でプリント回路基板上に搭載されるためモジュール
の高密度化ができない。In the above-mentioned conventional mounting structure, there is a limit to the miniaturization processing of the printed circuit board, and the LSI is mounted on the printed circuit board in a sealed package. Therefore, it is impossible to increase the module density.
【０００４】このために高速処理が要求される装置、例
えば高速コンピュータのＥＰＵ、ＲＩＳＣチップモジュ
ールあるいは画像処理装置など処理速度が５０ＭＨｚ以
上のものには適用不可となるという欠点があった。For this reason, there is a drawback in that it cannot be applied to devices requiring high-speed processing, such as EPUs of high-speed computers, RISC chip modules or image processing devices having a processing speed of 50 MHz or more.
【０００５】[0005]
【課題を解決するための手段】本発明のマルチチップモ
ジュールは、金属導体と有機絶縁層が形成されているシ
リコーンウエハー基板の表面にＴＡＢフリップチップあ
るいはワイヤーボンディングにより複数個のベアチップ
がボンディングされ、さらにこのシリコーンウエハー基
板がセラミックパッケージに実装され、さらに複数個の
ベアチップに接着し、これらをすべて封止するキャップ
とからなる構造を有する。In the multi-chip module of the present invention, a plurality of bare chips are bonded by TAB flip chip or wire bonding to the surface of a silicone wafer substrate on which a metal conductor and an organic insulating layer are formed. This silicone wafer substrate is mounted on a ceramic package and further has a structure including a cap that adheres to a plurality of bare chips and seals all of them.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例のマルチチップモジュール
の断面図である。The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a multichip module according to an embodiment of the present invention.
【０００７】図１において、シリコーンウエハー基板１
は表面に金属導体層と有機絶縁層とが必要回数交互に繰
り返し、多層化された構造となっている。図２にこの部
分の拡大図を示す。図２は金属導体３層、絶縁層２層の
例を示す。同図において、金属導体層１２は銅、金、あ
るいはアルミニウムなどが用いられ後述する有機絶縁層
とのあい性などより適宜選択される。シリコーンウエハ
ー基板１をベースにしているため平坦性に優れ、微細配
線が可能となる。スパッタリング、蒸着あるいは電解メ
ッキ法が一般的に用いられ、この場合ライン／スペース
は１０μ／１０μ以下の微細配線が実現できる。In FIG. 1, a silicone wafer substrate 1
Has a multilayered structure in which a metal conductor layer and an organic insulating layer are alternately repeated on the surface a required number of times. FIG. 2 shows an enlarged view of this portion. FIG. 2 shows an example of three layers of metal conductors and two layers of insulating layers. In the figure, the metal conductor layer 12 is made of copper, gold, aluminum or the like, and is appropriately selected depending on the compatibility with an organic insulating layer described later. Since the silicone wafer substrate 1 is used as a base, it has excellent flatness and enables fine wiring. Sputtering, vapor deposition or electroplating is generally used, in which case fine wiring with a line / space of 10 μ / 10 μ or less can be realized.
【０００８】さらに、有機絶縁層１３はポリイミドある
いはベンゾシクロブテンあるいはフッ素系樹脂などの誘
電率が３０以下のものが選択される。高速コンピュータ
あるいは画像処理装置など処理スピードが要求されるも
のに対して、低誘電率材料は不可欠でありこの構成を採
ることで十分対応できる。すなわち、シリコーンウエハ
ー基板１を用いることは大きく以下の２つの利点があ
る。一つは、平坦性に優れていること。二つ目は、スピ
ンコート法など半導体関連装置が流用でき、生産性が良
いことなどか挙げられる。Further, the organic insulating layer 13 is selected from those having a dielectric constant of 30 or less, such as polyimide, benzocyclobutene or fluorine resin. A low dielectric constant material is indispensable for high-speed computers or image processing devices that require high processing speed, and this structure can be sufficiently applied. That is, the use of the silicone wafer substrate 1 has the following two advantages. One is that it has excellent flatness. The second is that semiconductor-related devices such as the spin coating method can be used and the productivity is good.
【０００９】図１において、図２で詳細に説明したシリ
コーンウエハー基板１の表面にベアＬＳＩチップ２が複
数個実装される構成をとる。図１では、ワイヤーボンデ
ィング３の接続を示す。図３、図４には、ベアチップ２
の形態がそれぞれＴＡＢの場合およびフリップチップの
場合を示す。図３においてはＴＡＢリード３’、図４に
おいてははんだバンプ３”での接続を示す。これら３つ
の実装形態は、電気的検査性および生産性などから適宜
選択される。In FIG. 1, a plurality of bare LSI chips 2 are mounted on the surface of the silicone wafer substrate 1 described in detail with reference to FIG. In FIG. 1, the connection of the wire bonding 3 is shown. The bare chip 2 is shown in FIGS.
Shows the case of TAB and the case of flip chip. 3 shows the connection with the TAB lead 3 ′, and FIG. 4 shows the connection with the solder bump 3 ″. These three mounting forms are appropriately selected in view of electrical testability and productivity.
【００１０】図１において、シリコーンウエハー基板１
とベアＬＳＩ２とはＡｇエポキシ接着剤４などで機械的
に保持される。In FIG. 1, a silicone wafer substrate 1
The bare LSI 2 and the bare LSI 2 are mechanically held by an Ag epoxy adhesive 4 or the like.
【００１１】また、ベアＬＳＩチップ２は従来形態のよ
うな樹脂モールドあるいはセラミックパッケージされる
ことなく、ペレットのままで直接搭載されるため高密度
実装が可能となる。これによりＬＳＩ間の距離に比例す
る信号伝搬遅延時間が小さく設計でき、高速処理に適す
ることになる。我々の試作では、シリコーンウエハー基
板１に占めるベアＬＳＩ２の占有面積は６０％以上のも
のが得られている。Further, since the bare LSI chip 2 is directly mounted as pellets without being resin-molded or ceramic-packaged as in the conventional form, high-density mounting is possible. As a result, the signal propagation delay time proportional to the distance between the LSIs can be designed to be small, which is suitable for high-speed processing. In our trial production, the occupied area of the bare LSI 2 in the silicone wafer substrate 1 is 60% or more.
【００１２】さらに、ベアチップ２が複数個搭載された
シリコーンウエハー基板１がアルミナあるいはＡｌＮな
どのセラミックパッケージ５にＡｇエポキシ接着剤６に
より接着され、同時にシリコーンウエハー基板１とセラ
ミックパッケージ５とがワイヤー７により電気的に接続
されている。Further, a silicon wafer substrate 1 having a plurality of bare chips 2 mounted thereon is adhered to a ceramic package 5 such as alumina or AlN with an Ag epoxy adhesive 6, and at the same time, the silicone wafer substrate 1 and the ceramic package 5 are connected by a wire 7. It is electrically connected.
【００１３】さらに、前記ベアチップ２をハーメチック
シールするために、セラミックパッケージ５とＡｇエポ
キシ接着剤あるいはＳｎ／Ｐｂ系はんだ８でキャップ９
が取り付けられた構造をとる。同時に、キャップ９はベ
アーキャップ２の放熱のためのヒートトランスファーで
もある。すなわち、ベアーチップ２とキャップ９とはＡ
ｇエポキシ接着剤、あるいはＳｕ／Ｐｂ系はんだ１０で
接続され、ベアーチップ２の発熱はＡｇエポキシ１０を
通してキャップ９に放熱される。キャップ９の材質は熱
伝導性のよいＡｌＮやＣｕ系の金属などが用いられる。Further, in order to hermetically seal the bare chip 2, a ceramic package 5 and an Ag epoxy adhesive or a Sn / Pb type solder 8 are used to cap 9.
Takes the structure with attached. At the same time, the cap 9 is also a heat transfer for heat dissipation of the bare cap 2. That is, the bare chip 2 and the cap 9 are
The bare chip 2 is connected to the cap 9 through the Ag epoxy adhesive or the Su / Pb solder 10 and is radiated to the cap 9 through the Ag epoxy 10. As the material of the cap 9, AlN or Cu-based metal having good thermal conductivity is used.
【００１４】また、ベアＬＳＩチップ２はセラミックパ
ッケージ５の内部に形成されている配線（図示されてな
い）を通して、セラミックパッケージ５の裏側の入出力
ピン１１に接続される。さらに、セラミックパッケージ
５の内層に電源および接地層を設ける構成も可能であ
る。The bare LSI chip 2 is connected to the input / output pins 11 on the back side of the ceramic package 5 through wiring (not shown) formed inside the ceramic package 5. Further, it is possible to provide a power source and a ground layer in the inner layer of the ceramic package 5.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、複数のＬ
ＳＩを裸のままシリコーンウエハー基板上に直接搭載
し、さらに、専用のセラミックパッケージに実装する構
造としたので、高速かつ高放熱性のマルチチップモジュ
ールが可能となる。As described above, according to the present invention, a plurality of L
Since the SI is directly mounted on the silicone wafer substrate as it is and is mounted on a dedicated ceramic package, a high-speed and high heat dissipation multi-chip module is possible.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明のマルチチップモジュールの実施例を示
す断面図である。FIG. 1 is a sectional view showing an embodiment of a multi-chip module of the present invention.
【図２】シリコンウエハー基板の拡大図である。FIG. 2 is an enlarged view of a silicon wafer substrate.
【図３】本発明のマルチチップモジュールの他の例を示
す断面図である。FIG. 3 is a cross-sectional view showing another example of the multi-chip module of the present invention.
【図４】本発明のマルチチップモジュールの他の例を示
す断面図である。FIG. 4 is a cross-sectional view showing another example of the multi-chip module of the present invention.
１ シリコーンウエハー基板 ２ ベアーＬＳＩチップ ３ ワイヤーボンディング ３’ ＴＡＢリード ３” ハンダバンプ ４ Ａｇエポキシ接着剤 ５ セラミックパッケージ ６ Ａｇエポキシ接着剤 ７ ワイヤー ８ Ａｇエポキシ接着剤あるいはＳｎ／Ｐｂ系はんだ ９ キャップ １０ Ａｇエポキシ接着剤 １１ 入出力ピン １２ 金属導体層 １３ 有機絶縁層 1 Silicone Wafer Substrate 2 Bear LSI Chip 3 Wire Bonding 3'TAB Lead 3 "Solder Bump 4 Ag Epoxy Adhesive 5 Ceramic Package 6 Ag Epoxy Adhesive 7 Wire 8 Ag Epoxy Adhesive or Sn / Pb Solder 9 Cap 10 Ag Epoxy Adhesive Agent 11 Input / output pin 12 Metal conductor layer 13 Organic insulating layer
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/36 Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/36
Claims (5)
るシリコーンウエハー基板と、前記シリコーンウエハー
基板の表面に搭載されているベアＬＳＩチップと、前記
シリコーンウエハー基板の前記ベアーＬＳＩチップが搭
載されていないもう一つの面と接着し、かつ前記シリコ
ーンウエハー基板の入出力端子と電気的に接続するセラ
ミックパッケージと、前記ベアーＬＳＩチップの一つの
面と接続し、かつ前記セラミックパッケージを封止する
キャップとを備えたことを特徴とするマルチチップモジ
ュール。1. A silicone wafer substrate on which a metal conductor layer and an organic insulating layer are formed, a bare LSI chip mounted on the surface of the silicone wafer substrate, and the bare LSI chip of the silicone wafer substrate are mounted. And a ceramic package that adheres to the other surface and that is electrically connected to the input / output terminals of the silicone wafer substrate, and a cap that connects to one surface of the bare LSI chip and seals the ceramic package. And a multi-chip module characterized by including.
ある請求項１に記載のマルチチップモジュール。2. The multichip module according to claim 1, wherein the metal conductor layer is Cu, Au or Al.
に記載のマルチチップモジュール。3. The organic insulating layer is polyimide.
The multi-chip module described in.
請求項１に記載のマルチチップモジャール。4. The multi-chip mojar according to claim 1, wherein the organic insulating layer is benzocyclobutene.
求項１に記載のマルチチップモジュール。5. The multi-chip module according to claim 1, wherein the ceramic package is AlN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4147023A JPH05343606A (en) | 1992-06-08 | 1992-06-08 | Multi chip module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4147023A JPH05343606A (en) | 1992-06-08 | 1992-06-08 | Multi chip module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05343606A true JPH05343606A (en) | 1993-12-24 |
Family
ID=15420800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4147023A Withdrawn JPH05343606A (en) | 1992-06-08 | 1992-06-08 | Multi chip module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05343606A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998000866A1 (en) * | 1996-06-28 | 1998-01-08 | The Whitaker Corporation | Reduced parasitic capacitance semiconductor devices |
| EP0709882A3 (en) * | 1994-10-27 | 1998-04-15 | Nec Corporation | Semiconductor device with passivation layer made out of benzocyclobutene polymer and silicon powder |
| US6376912B1 (en) | 1996-03-29 | 2002-04-23 | Tokin Corporation | Common mode choke coil of the conductor/insulator stacked type that uses a high machinability substrate and benzocyclobutene as the insulator |
| US7936074B2 (en) * | 2004-11-04 | 2011-05-03 | Tabula, Inc. | Programmable system in package |
| US8201124B1 (en) | 2005-03-15 | 2012-06-12 | Tabula, Inc. | System in package and method of creating system in package |
-
1992
- 1992-06-08 JP JP4147023A patent/JPH05343606A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0709882A3 (en) * | 1994-10-27 | 1998-04-15 | Nec Corporation | Semiconductor device with passivation layer made out of benzocyclobutene polymer and silicon powder |
| US6376912B1 (en) | 1996-03-29 | 2002-04-23 | Tokin Corporation | Common mode choke coil of the conductor/insulator stacked type that uses a high machinability substrate and benzocyclobutene as the insulator |
| US6392297B2 (en) * | 1996-03-29 | 2002-05-21 | Tokin Corporation | Electronic circuit element of conductor/insulator stacked type using high machinability substrate and benzocyclobutene as insulator |
| WO1998000866A1 (en) * | 1996-06-28 | 1998-01-08 | The Whitaker Corporation | Reduced parasitic capacitance semiconductor devices |
| US5883422A (en) * | 1996-06-28 | 1999-03-16 | The Whitaker Corporation | Reduced parasitic capacitance semiconductor devices |
| US7936074B2 (en) * | 2004-11-04 | 2011-05-03 | Tabula, Inc. | Programmable system in package |
| US8536713B2 (en) | 2004-11-04 | 2013-09-17 | Tabula, Inc. | System in package with heat sink |
| US8201124B1 (en) | 2005-03-15 | 2012-06-12 | Tabula, Inc. | System in package and method of creating system in package |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990831 |