JPH05343605A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH05343605A JPH05343605A JP15172492A JP15172492A JPH05343605A JP H05343605 A JPH05343605 A JP H05343605A JP 15172492 A JP15172492 A JP 15172492A JP 15172492 A JP15172492 A JP 15172492A JP H05343605 A JPH05343605 A JP H05343605A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- substrate
- integrated circuit
- terminal pad
- ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体モノリシック集
積回路（以降ＳＣＩＣと称す）や電子部品とそれを実装
する基板からなる混成集積回路装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device comprising a semiconductor monolithic integrated circuit (hereinafter referred to as SCIC) and electronic parts and a board on which the parts are mounted.
【０００２】[0002]
【従来の技術】従来、この種の混成集積回路装置は、薄
膜や厚膜導体を蒸着や印刷焼成したセラミック基板上に
ＳＣＩＣのチップをダイスボンディングし、そのＳＣＩ
Ｃの電極と前記薄膜や厚膜導体をワイヤボンディングで
接続したり、ＡＳＬＴ（アドバンシィド ソリッド ロジ
ック テクノロジー）と呼ぶ基板を多階層に構成する方
法がとられている。2. Description of the Related Art Conventionally, in this type of hybrid integrated circuit device, an SCIC chip is die-bonded on a ceramic substrate on which a thin film or thick film conductor is vapor-deposited or printed and fired, and the SCI is obtained.
A method of connecting the electrode of C to the thin film or thick film conductor by wire bonding, or configuring a substrate called ASLT (advanced solid logic technology) in multiple layers is adopted.
【０００３】以下、図面を参照しながら従来の混成集積
回路装置について説明する。図９は、従来のワイヤボン
ディングした混成集積回路装置の断面図を示すものであ
り、図１０は従来のＡＳＬＴを用いた混成集積回路装置
の斜視図を示すものである。A conventional hybrid integrated circuit device will be described below with reference to the drawings. FIG. 9 shows a cross-sectional view of a conventional wire-bonded hybrid integrated circuit device, and FIG. 10 shows a perspective view of a conventional hybrid integrated circuit device using an ASLT.
【０００４】図９において、３１は基板であり、３２は
リード端子であり、３３はその端子を半田付けする端子
パッドであり、３４はＳＣＩＣチップであり、基板３１
の表面に印刷焼成した厚膜導体３６とワイヤ３７と接続
されている。３５はチップ部品であり、厚膜導体３６と
半田付けされている。In FIG. 9, 31 is a substrate, 32 is a lead terminal, 33 is a terminal pad for soldering the terminal, 34 is an SCIC chip, and the substrate 31
Is connected to the thick film conductor 36 and the wire 37 which are printed and fired on the surface of the. Reference numeral 35 denotes a chip component, which is soldered to the thick film conductor 36.
【０００５】しかしながら、上記のような構成では、近
年のＳＣＩＣの多機能高集積化やＡＳＩＣ化にともなう
多ピン化と、高密度実装化につれて次のような問題点が
生じる。 （１）ＳＣＩＣの多ピン化にともないそれを実装した混
成集積回路装置も多端子化し集積度が低下する。 （２）混成集積回路装置の基板からリード端子を取り付
けた構造では、近年のディジタル回路の高周波化に対し
てインダクタンス成分が増して信号の遅延等の問題が発
生し使えない。 （３）混成集積回路装置の形状が混成集積回路装置の基
板からリード端子を取り付けた構造では形状が大きくな
り、多ピン化によって更に大型化し、近年の高密度実装
の要求に応えられない。However, in the above-mentioned structure, the following problems arise with the increase in the number of pins and the high-functionality integration and ASIC of SCIC in recent years and the high-density mounting. (1) As the number of pins of the SCIC increases, the number of terminals of the hybrid integrated circuit device mounting the SCIC also increases and the degree of integration decreases. (2) The structure in which the lead terminal is attached from the substrate of the hybrid integrated circuit device cannot be used because a problem such as signal delay occurs due to an increase in inductance component with the recent increase in frequency of digital circuits. (3) The shape of the hybrid integrated circuit device is large in the structure in which the lead terminals are attached from the substrate of the hybrid integrated circuit device, and the size is further increased due to the increase in the number of pins, which cannot meet the recent demand for high-density mounting.
【０００６】基板を多階層化することで高集積度を実現
する手段としてＡＳＬＴによる実装方法がある。以下従
来のＡＳＬＴを用いた方法について説明する。There is a mounting method by ASLT as a means for realizing a high degree of integration by making a substrate multi-layered. A method using the conventional ASLT will be described below.
【０００７】図１０は、従来のＡＳＬＴの斜視図を示す
ものであり、図１０において、４１ａ，４１ｂ，４１
ｃ，４１ｄ，４１ｅは基板であり、４２は導体である。FIG. 10 is a perspective view of a conventional ASLT. In FIG. 10, 41a, 41b, 41 are shown.
Reference numerals c, 41d, 41e are substrates, and 42 is a conductor.
【０００８】また、基板４１ａにおいて、４３はＳＣＩ
Ｃのチップであり、導体４２にフェースダウン・ボンデ
ィングされている。４４は端子であり、導体４２に半田
付けされている。４５はチップ部品であり、導体４２に
半田付けされている。前記構成は基板４１ｂ，４１ｃ，
４１ｄ，４１ｅにおいても同様の構造であり、端子４４
により各基板の導体４２に半田付けされ共通接続されて
いる。端子４４は、 （ａ）多階層化する全基板を多階層構造化するための支
持機能。 （ｂ）多階層化した全基板の電気信号伝送路機能。 （ｃ）ＡＳＬＴをプリント基板に支持する機能。 （ｄ）ＡＳＬＴの電気信号をプリント基板に伝達する伝
送路機能。 の４つの機能の条件の内１つでも機能として要求されれ
ば端子を設けなければならない。In the board 41a, 43 is an SCI.
The C chip is face-down bonded to the conductor 42. Reference numeral 44 is a terminal, which is soldered to the conductor 42. Reference numeral 45 is a chip component, which is soldered to the conductor 42. The above-mentioned configuration includes substrates 41b, 41c,
41d and 41e have the same structure, and the terminal 44
Are soldered and commonly connected to the conductors 42 of each board. The terminal 44 has (a) a support function for forming a multi-layer structure on all the boards that are multi-layered. (B) The electric signal transmission line function of all the boards that are multi-layered. (C) A function of supporting the ASLT on the printed circuit board. (D) A transmission line function for transmitting the electric signal of the ASLT to the printed circuit board. If even one of the four function conditions is required as a function, a terminal must be provided.
【０００９】これを論理式で表現すると、 （ａ）＋（ｂ）＋（ｃ）＋（ｄ）＝（端子を設ける） となり、実使用の上では（ａ）と（ｂ）または（ｃ）と
（ｄ）のどちらかの機能要求が多いため、ＡＳＬＴの端
子は多端子化し、集積度が低下する。If this is expressed by a logical expression, it becomes (a) + (b) + (c) + (d) = (provide a terminal), and in actual use, (a) and (b) or (c) Since there is a large demand for the function of either (1) or (d), the number of terminals of the ASLT is increased and the degree of integration is reduced.
【００１０】更に、前記したＳＣＩＣの多機能高集積化
やＡＳＩＣ化にともなう多ピン化につれて、図１０のよ
うな構成では更に次のような問題点が生じる。 （１）多階層化した各基板の電気信号の伝送路機能を端
子４４が担うため高階層化に伴い、更にＡＳＬＴの多端
子化を招き集積度を低下させる。 （２）各基板を多階層構造化する支持機能を持つ多数の
各階層基板の共通端子で保持された構造のため、故障基
板の交換が困難である。 （３）また、ＡＳＬＴのように各基板を多階層構造化し
た集積回路を構成する場合、内蔵する回路を各基板に振
り分ける必要があるがその際、内蔵回路を回路機能毎に
切り別けて基板の独立性を確保すると、前記した（ｂ）
の条件を要求する端子が増してＡＳＬＴの集積度が低下
する。 （４）ＡＳＬＴの集積度を確保すると基板の独立性が無
くなり、設計変更、集積回路基板単品の検査、ＡＳＬＴ
の保守性が損なわれる。といった問題が生じる。Further, with the increase in the number of pins of the SCIC as described above, which is accompanied by the multi-function and high integration of the SCIC and the ASIC, the following problems further occur in the configuration shown in FIG. (1) Since the terminal 44 plays the function of the transmission path of the electric signal of each multi-layered board, as the number of layers increases, the number of terminals of the ASLT is further increased and the integration degree is lowered. (2) It is difficult to replace a faulty board because of the structure in which the boards are held by the common terminals of a large number of boards that have a supporting function for forming a multi-layered structure. (3) Further, in the case of forming an integrated circuit in which each substrate has a multi-layered structure like ASLT, it is necessary to distribute the built-in circuit to each substrate. If the independence of
The number of terminals that require the above condition increases and the integration degree of ASLT decreases. (4) When the integration degree of ASLT is secured, the independence of the board is lost, and the design change, the inspection of the integrated circuit board single product, the ASLT
Maintainability is deteriorated. Such a problem occurs.
【００１１】[0011]
【発明が解決しようとする課題】上記従来の構成ではＳ
ＣＩＣの多機能高集積化やＡＳＩＣ化による多ピン化に
伴う集積度の低下という課題に加え、基板を多階層化し
た場合に故障基板の交換をしにくいという課題と、多階
層構造化した集積回路の各階層基板の独立性が確保しづ
らいという課題と、端子のインダクタンスが高周波回路
で使えないという課題を有するものであった。In the above conventional configuration, S is used.
In addition to the problem that the degree of integration decreases as the number of pins increases due to the multi-functionality and high integration of CICs and ASICs, it is difficult to replace a faulty board when the boards are hierarchized, and the multi-tiered integration There are problems that it is difficult to ensure the independence of each hierarchical substrate of the circuit and that the inductance of the terminals cannot be used in the high frequency circuit.
【００１２】[0012]
【課題を解決するための手段】本発明は上記課題を解決
するために、端子をボール状とし、そのボール状端子を
集積回路基板に面実装するようにしたものである。In order to solve the above-mentioned problems, the present invention has a ball-shaped terminal, and the ball-shaped terminal is surface-mounted on an integrated circuit board.
【００１３】[0013]
【作用】この構成によって、ボール状端子は集積回路基
板の外形をはみ出すことなく基板の任意の位置に設けら
れるので、多端子にしても集積度を落とすことがない。
更に、この構造の集積回路装置を多階層に積層すれば各
階層の基板に不要な端子を設置することなく多層化した
集積回路装置を構成できる。With this configuration, the ball-shaped terminal is provided at an arbitrary position on the substrate without protruding the outer shape of the integrated circuit substrate, so that even if multiple terminals are provided, the degree of integration is not reduced.
Furthermore, by stacking the integrated circuit devices of this structure in multiple layers, a multilayered integrated circuit device can be configured without installing unnecessary terminals on the boards of each layer.
【００１４】[0014]
【実施例】以下本発明の実施例について図１〜図８を参
照しながら説明する。Embodiments of the present invention will be described below with reference to FIGS.
【００１５】図１は本発明の実施例における混成集積回
路装置の斜視図を示すものである。図１において、１は
基板であり、２はボール状端子であり、３はそのボール
状端子２を半田付けする端子パッドであり、４はＳＣＩ
Ｃチップであり、基板１の表面に印刷焼成した厚膜導体
６にフェースダウン・ボンディングされている。５はチ
ップ部品であり、厚膜導体６に半田付けされている。FIG. 1 is a perspective view of a hybrid integrated circuit device according to an embodiment of the present invention. In FIG. 1, 1 is a substrate, 2 is a ball-shaped terminal, 3 is a terminal pad for soldering the ball-shaped terminal 2, and 4 is an SCI.
It is a C chip and is face-down bonded to the thick film conductor 6 printed and fired on the surface of the substrate 1. Reference numeral 5 denotes a chip component, which is soldered to the thick film conductor 6.
【００１６】ボール状端子２の直径は、基板１に実装し
た状態で基板１に実装したＳＣＩＣ４およびチップ部品
５の実装高さよりボール状端子２の実装高さが高くなる
ように決めてある。The diameter of the ball-shaped terminal 2 is determined so that the mounting height of the ball-shaped terminal 2 is higher than the mounting height of the SCIC 4 and the chip component 5 mounted on the substrate 1 in the state of being mounted on the substrate 1.
【００１７】以上のように構成された混成集積回路装置
は図２に示すように銅張り積層基板７（以降プリント基
板と称す）に、基板１とプリント基板７の間にボール状
端子２を介在する形でリフローソルダリング法によって
実装される。As shown in FIG. 2, the hybrid integrated circuit device configured as described above has a ball-shaped terminal 2 interposed between a board 1 and a printed board 7 on a copper-clad laminated board 7 (hereinafter referred to as a printed board). Is implemented by the reflow soldering method.
【００１８】図３〜図５は基板１にボール状端子２を半
田付けする端子パッド３の詳細斜視図を示すものであ
る。FIGS. 3 to 5 are detailed perspective views of the terminal pad 3 for soldering the ball-shaped terminal 2 to the substrate 1.
【００１９】図３において、基板１の表面に印刷焼成し
た端子パッド３は、パッド３ａ，３ｂよりなり、そして
パッド３ａには溝８が図３に示すごとくＹ字状に設けら
れている。Ｙ字状溝８が集中する中心位置はボール状端
子２の位置で、Ｙ字状溝８が集中する中心位置にボール
状端子２が落ち込むことでボール状端子２の位置決め安
定性が高く配置実装が容易になる。更にリフローソルダ
リング時にＹ字状溝８に溶融した半田が流れ込みボール
状端子２と端子パッド３の半田濡れ性および半田付け強
度が向上する。In FIG. 3, the terminal pad 3 printed and baked on the surface of the substrate 1 is composed of pads 3a and 3b, and a groove 8 is provided in the pad 3a in a Y shape as shown in FIG. The center position where the Y-shaped groove 8 is concentrated is the position of the ball-shaped terminal 2, and the ball-shaped terminal 2 is dropped to the center position where the Y-shaped groove 8 is concentrated, so that the ball-shaped terminal 2 is highly positioned and mounted. Will be easier. Further, the solder melted in the Y-shaped groove 8 flows during the reflow soldering, and the solder wettability and the soldering strength of the ball-shaped terminal 2 and the terminal pad 3 are improved.
【００２０】端子パッド３の溝８は図３に示すＹ字状だ
けでなく、図４に示すように十字状などのボール状端子
２の位置を中心に放射状に多数の溝８を設けたり、図５
に示すように溝８の中央部が細くなった糸巻き状であっ
ても同じ効果が得られる。The groove 8 of the terminal pad 3 is not limited to the Y-shape shown in FIG. 3, but as shown in FIG. 4, a large number of grooves 8 may be provided radially around the position of the ball-shaped terminal 2 such as a cross. Figure 5
The same effect can be obtained even if the central portion of the groove 8 has a thin wound shape as shown in FIG.
【００２１】端子パッド３の溝８は図３の端子パッド部
の断面に示すようにパッド３ａ、パッド３ｂ、の２層に
各々印刷して焼成することで得られるがパッド３ｂだけ
でも溝８を実現でき、その場合も２層に各々印刷したと
きと同様に半田濡れ性および半田付け強度が向上する効
果が得られる。The groove 8 of the terminal pad 3 can be obtained by printing on two layers of a pad 3a and a pad 3b and firing as shown in the cross section of the terminal pad portion of FIG. In this case, the solder wettability and the soldering strength can be improved in the same manner as in the case of printing on each of the two layers.
【００２２】図６は本発明の他の実施例における詳細斜
視図を示すものである。図６において、１は基板であ
り、９は基板１の表面に設けた第１の端子パッドであ
り、１０は基板１の第１の端子パッド９と反対側の裏面
に設けた第２の端子パッドであり、１１は第１の端子パ
ッド９に設けた溝であり、１２は第２の端子パッド１０
に設けた溝であり、１３は基板１の表裏を貫通する孔で
ある。FIG. 6 is a detailed perspective view of another embodiment of the present invention. In FIG. 6, 1 is a substrate, 9 is a first terminal pad provided on the front surface of the substrate 1, and 10 is a second terminal provided on the back surface of the substrate 1 opposite to the first terminal pad 9. Pads, 11 are grooves provided in the first terminal pad 9, and 12 is a second terminal pad 10.
Is a groove provided in the substrate 1, and 13 is a hole penetrating the front and back of the substrate 1.
【００２３】基板１の表面に印刷焼成した第１の端子パ
ッド９は溝１１が図６に示すように十字状に設けられて
いる。十字状溝１１が集中する中心位置１４はボール状
端子２が置かれる位置で、その位置１４において基板の
表裏を貫通する孔１３が設けられ、そしてその孔１３に
は導電性材料１５が内壁に塗布されているか、充填され
ている。基板１の裏面には基板１の表面に印刷焼成した
第１の端子パッド９と同様の構造の第２の端子パッド１
０が印刷焼成により設けられており基板１の表面の第１
の端子パッド９に設けられた十字状溝１１が集中する中
心位置１４と基板１の裏面の第２の端子パッド１０に設
けられた十字状溝１２が集中する中心位置１６とは導電
性材料１５が内壁に塗布または充填されている孔１３の
中心軸と一致すると共に、導電性材料１５によって電気
的接続がされている（以降、電気的接続がされた貫通孔
をスルーホールと称す）。The first terminal pads 9 printed and fired on the surface of the substrate 1 are provided with grooves 11 in a cross shape as shown in FIG. A central position 14 where the cross-shaped grooves 11 are concentrated is a position where the ball-shaped terminal 2 is placed, and at that position 14, a hole 13 penetrating the front and back of the substrate is provided, and the conductive material 15 is formed on the inner wall of the hole 13. Coated or filled. The second terminal pad 1 having the same structure as the first terminal pad 9 printed and fired on the front surface of the substrate 1 is provided on the back surface of the substrate 1.
0 is provided by printing and baking, and is the first of the surface of the substrate 1.
The central position 14 where the cross-shaped grooves 11 provided in the terminal pad 9 are concentrated and the central position 16 where the cross-shaped grooves 12 provided in the second terminal pad 10 on the back surface of the substrate 1 are concentrated are the conductive material 15 Coincides with the central axis of the hole 13 applied or filled in the inner wall, and is electrically connected by the conductive material 15 (hereinafter, the through hole electrically connected is referred to as a through hole).
【００２４】図７は図６に示す基板の表裏をスルーホー
ルで接続した端子パッドを用いた集積回路装置の実施例
である。FIG. 7 shows an embodiment of an integrated circuit device using terminal pads in which the front and back of the substrate shown in FIG. 6 are connected by through holes.
【００２５】図７において、１７ａは第１の集積回路の
基板であり、図６に示した第１の端子パッドに半田付け
されたボール状端子１８ａ、スルーホールを持たない第
３の端子パッド１９ａ、第３の端子パッド１９ａに半田
付けされたボール状端子２０ａ、図６に示すような第２
の端子パッド２１ａ、及びスルーホールを介して第１の
集積回路の基板１７ａの第１の端子パッドを備える面の
回路配線と電気的接続がされる第４の端子パッド２２ａ
を有している。In FIG. 7, reference numeral 17a denotes a substrate of the first integrated circuit, which is a ball-shaped terminal 18a soldered to the first terminal pad shown in FIG. 6 and a third terminal pad 19a having no through hole. , The ball-shaped terminal 20a soldered to the third terminal pad 19a, the second terminal as shown in FIG.
Terminal pad 21a and a fourth terminal pad 22a electrically connected to the circuit wiring on the surface of the substrate 17a of the first integrated circuit provided with the first terminal pad via the through hole.
have.
【００２６】１７ｂは第２の集積回路の基板であり、図
６に示した第１の端子パッドに半田付けされたボール状
端子１８ｂ、スルーホールを持たない第３の端子パッド
１９ｂ、第３の端子パッド１９ｂに半田付けされたボー
ル状端子２０ｂ、図６に示すような第２の端子パッド２
１ｂ及びスルーホールを介して第１の集積回路の基板１
７ｂの第１の端子パッドを備える面の回路配線と電気的
接続がされる第４の端子パッド２２ｂを有している。Reference numeral 17b denotes a substrate of the second integrated circuit, which is a ball-shaped terminal 18b soldered to the first terminal pad shown in FIG. 6, a third terminal pad 19b having no through hole, and a third terminal pad 19b. Ball-shaped terminal 20b soldered to terminal pad 19b, second terminal pad 2 as shown in FIG.
Substrate 1 of the first integrated circuit via 1b and through holes
7b has a fourth terminal pad 22b electrically connected to the circuit wiring on the surface having the first terminal pad.
【００２７】１７ｃは第３の集積回路の基板であり、図
６に示した第１の端子パッドに半田付けされたボール状
端子１８ｃ、スルーホールを持たない第３の端子パッド
１９ｃ、第３の端子パッド１９ｃに半田付けされたボー
ル状端子２０ｃ、図６に示すような第２の端子パッド２
１ｃ、及びスルーホールを介して第１の集積回路の基板
１７ｃの第１の端子パッドを備える面の回路配線と電気
的接続がされる第４の端子パッド２２ｃを有している。Reference numeral 17c designates a substrate of the third integrated circuit, which is a ball-shaped terminal 18c soldered to the first terminal pad shown in FIG. 6, a third terminal pad 19c having no through hole, and a third terminal pad 19c. Ball-shaped terminal 20c soldered to terminal pad 19c, second terminal pad 2 as shown in FIG.
1c and a fourth terminal pad 22c electrically connected to the circuit wiring on the surface of the substrate 17c of the first integrated circuit provided with the first terminal pad via the through hole.
【００２８】１７ｄは第４の集積回路の基板であり、図
６に示した第１の端子パッドに半田付けされたボール状
端子１８ｄ、スルーホールを持たない第３の端子パッド
１９ｄ、第３の端子パッド１９ｄに半田付けされたボー
ル状端子２０ｄを有している。Reference numeral 17d denotes a substrate of the fourth integrated circuit, which is a ball-shaped terminal 18d soldered to the first terminal pad shown in FIG. 6, a third terminal pad 19d having no through hole, and a third terminal pad 19d. It has ball-shaped terminals 20d soldered to the terminal pads 19d.
【００２９】図７において、第１の集積回路はボール状
端子１８ａ，２０ａを介してプリント基板７に実装され
る。第２の集積回路はボール状端子１８ｂ，２０ｂを第
１の集積回路の第２，第４の端子パッド２１ａ，２２ａ
にリフローソルダリングによって接続し、第３の集積回
路はボール状端子１８ｃ，２０ｃを第２の集積回路の第
２，第４の端子パッド２１ｂ，２２ｂにリフローソルダ
リングによって接続し、第４の集積回路はボール状端子
１８ｄ，２０ｄを第３の集積回路の第２，第４の端子パ
ッド２１ｃ，２２ｃにリフローソルダリングによって接
続する。In FIG. 7, the first integrated circuit is mounted on the printed board 7 via the ball-shaped terminals 18a and 20a. In the second integrated circuit, the ball-shaped terminals 18b and 20b are connected to the second and fourth terminal pads 21a and 22a of the first integrated circuit.
And the third integrated circuit connects the ball-shaped terminals 18c and 20c to the second and fourth terminal pads 21b and 22b of the second integrated circuit by reflow soldering. The circuit connects the ball-shaped terminals 18d, 20d to the second and fourth terminal pads 21c, 22c of the third integrated circuit by reflow soldering.
【００３０】図１０のＡＳＬＴの場合、端子４４は、 （ａ）多階層化する全基板を多階層構造化するための支
持機能。 （ｂ）多階層化した全基板の電気信号伝送路機能。 （ｃ）集積回路をプリント基板に支持する機能。 （ｄ）集積回路の電気信号をプリント基板に伝達する伝
送路機能。 の４つの機能の条件の内１つでも機能として要求されれ
ば端子を設けなければならないことから （ａ）＋（ｂ）＋（ｃ）＋（ｄ）＝（端子を設ける） の論理式で表現した。In the case of the ASLT shown in FIG. 10, the terminal 44 has (a) a supporting function for forming a multi-layer structure on all the boards to be multi-layered. (B) The electric signal transmission line function of all the boards that are multi-layered. (C) A function of supporting the integrated circuit on the printed circuit board. (D) A transmission line function for transmitting electric signals of the integrated circuit to the printed circuit board. If at least one of the four function conditions is required as a function, a terminal must be provided. Therefore, (a) + (b) + (c) + (d) = (provide terminal) Expressed.
【００３１】図７の例では（ａ）と（ｂ）の２つの機能
がなくなり、端子は（ｃ）と（ｄ）に加えて、 （ｅ）基板を積層構造化するための支持機能。 （ｆ）上下基板の電気信号伝送路機能。 の４つの機能の条件になるが、プリント基板に実装する
接続構造と半田付け工法は各集積回路の積層の層間の接
続と同じであり、実質的には（ｃ）は（ｅ）、（ｄ）は
（ｆ）の機能に集約できて、 （ｅ）＋（ｆ）＝（端子を設ける） の論理式で端子を設ければよく、高い集積度が得られ
る。In the example of FIG. 7, the two functions of (a) and (b) are eliminated, and the terminal has (c) and (d), and (e) a supporting function for forming a laminated structure of the substrate. (F) Electric signal transmission line function of upper and lower substrates. The connection structure to be mounted on the printed circuit board and the soldering method are the same as the connection between the layers of the laminated layers of the integrated circuits, and substantially (c) is (e) and (d). ) Can be aggregated into the function of (f), and terminals can be provided by a logical expression of (e) + (f) = (provide terminals), and a high degree of integration can be obtained.
【００３２】また、上下基板の電気信号の伝送路を考え
ればよいため、多層構造化する際に内蔵回路を基板に振
り分けをする際機能ブロックごとに割り振りをしても集
積度に影響する端子の増加が無いので基板の独立性が確
保でき、設計変更、集積回路基板単品の検査、集積回路
の保守性が容易にできる。Further, since it is only necessary to consider the electric signal transmission paths of the upper and lower substrates, when the built-in circuits are distributed to the substrates in the multilayer structure, even if the functional circuits are allocated to each functional block, the degree of integration of the terminals is affected. Since there is no increase, the independence of the board can be ensured, and the design change, the inspection of a single integrated circuit board, and the maintainability of the integrated circuit can be easily performed.
【００３３】図７の例では４つの集積回路を４階層に積
層した構造を示したが、積層する層数を変えても各集積
回路の層間の接続方法は同じである。Although the example of FIG. 7 shows a structure in which four integrated circuits are laminated in four layers, the method of connecting the layers of each integrated circuit is the same even if the number of laminated layers is changed.
【００３４】また、プリント基板に実装する接続構造と
半田付け工法は各集積回路の積層の層間の接続と同じで
あり、プリント基板で通常用いる半田付け工法を用いる
ため専用の半田付け装置は必要なく、各層間の接続はボ
ール状端子で行っているので多階層中の故障基板の交換
は故障基板と故障基板の上の基板のボール状端子を各々
下の基板から取り外して良品基板と交換後、取り外し箇
所を再度半田付けすれば容易にできる。Further, the connection structure to be mounted on the printed circuit board and the soldering method are the same as the connection between the laminated layers of the integrated circuits, and the soldering method usually used for the printed circuit board is used, so that no dedicated soldering device is required. , Since the connection between each layer is made with ball-shaped terminals, the faulty board in the multi-layer can be replaced after removing the faulty board and the ball-shaped terminals of the board above the faulty board from the board below respectively, and replacing it with a good board. This can be easily done by re-soldering the removed part.
【００３５】ボール状端子１８は形状に方向性がないた
め取扱いが容易であると共に、（ｅ）と（ｆ）の機能を
得るのにリード端子より端子パッドが小さくでき、短い
ため高周波領域の回路でも小さいインダクタンスの実装
ができる。Since the ball-shaped terminal 18 has no directionality in its shape, it is easy to handle, and the terminal pad can be made smaller than the lead terminal in order to obtain the functions (e) and (f). However, a small inductance can be mounted.
【００３６】図８（ａ），（ｂ）に端子パッドの実施例
を示す。図８（ａ）において１は基板であり、２３はリ
ード端子の端子パッドである。FIGS. 8A and 8B show an embodiment of the terminal pad. In FIG. 8A, 1 is a substrate, and 23 is a terminal pad of a lead terminal.
【００３７】図８（ｂ）において１は基板であり、２４
はボール状端子の端子パッドであり、図８（ａ）のリー
ド端子の端子パッドと同じ領域ｗにリード端子よりもボ
ール状端子のほうが多端子化できることを示している。In FIG. 8B, 1 is a substrate, and 24
Is a terminal pad of a ball-shaped terminal, and it is shown that the ball-shaped terminal can have more terminals than the lead terminal in the same region w as the terminal pad of the lead terminal of FIG.
【００３８】[0038]
【発明の効果】以上のように本発明によれば、ＳＣＩＣ
の多機能高集積化やＡＳＩＣ化による多ピン化に伴う集
積度の低下が無く、多階層構造化した基板の中で故障し
た基板の交換が容易にでき、多階層構造化した集積回路
の各階層基板の独立性が確保でき、端子のインダクタン
スが低いので高周波回路でも使えるという効果を有する
ものである。As described above, according to the present invention, the SCIC
There is no reduction in the degree of integration that accompanies the increase in the number of pins due to the multi-functional high integration and ASIC, and it is possible to easily replace a defective substrate in a multi-layer structured substrate, and Since the independence of the hierarchical substrate can be secured and the inductance of the terminal is low, it can be used in a high frequency circuit.
【図１】本発明の一実施例による混成集積回路装置の斜
視図FIG. 1 is a perspective view of a hybrid integrated circuit device according to an embodiment of the present invention.
【図２】同装置の実装される状態を示す断面図FIG. 2 is a cross-sectional view showing a mounted state of the device.
【図３】同装置において、端子パッドの例を示す斜視図FIG. 3 is a perspective view showing an example of a terminal pad in the same device.
【図４】同装置において、端子パッドの例を示す斜視図FIG. 4 is a perspective view showing an example of a terminal pad in the same device.
【図５】同装置において、端子パッドの例を示す斜視図FIG. 5 is a perspective view showing an example of a terminal pad in the same device.
【図６】本発明の他の実施例において、端子パッドと基
板の一部を断面で示す斜視図FIG. 6 is a perspective view showing a cross section of a terminal pad and a part of a substrate according to another embodiment of the present invention.
【図７】本発明の他の実施例による混成集積回路装置を
示す断面図FIG. 7 is a sectional view showing a hybrid integrated circuit device according to another embodiment of the present invention.
【図８】（ａ）はリード端子の端子パッドの例を示す斜
視図 （ｂ）はボール状端子の端子パッドの実施例を示す斜視
図FIG. 8A is a perspective view showing an example of a terminal pad of a lead terminal, and FIG. 8B is a perspective view showing an example of a terminal pad of a ball-shaped terminal.
【図９】従来のワイヤボンディングした混成集積回路装
置の断面図FIG. 9 is a cross-sectional view of a conventional wire-bonded hybrid integrated circuit device.
【図１０】従来のＡＳＬＴを用いた混成集積回路装置の
斜視図FIG. 10 is a perspective view of a hybrid integrated circuit device using a conventional ASLT.
１ 基板 ２ ボール状端子 ３ 端子パッド ４ ＳＣＩＣチップ ５ チップ部品 1 substrate 2 ball terminal 3 terminal pad 4 SCIC chip 5 chip parts
Claims (4)
Ｃ、チップ部品と共に端子パッドを備え、この端子パッ
ドにボール状端子を取り付けたことを特徴とする混成集
積回路装置。1. At least a semiconductor monolithic I on a substrate.
A hybrid integrated circuit device comprising a terminal pad together with C and a chip component, and a ball-shaped terminal attached to the terminal pad.
ルを介してボール状端子取り付け面と反対の面に端子パ
ッドとを設けたことを特徴とする請求項１記載の混成集
積回路装置。2. The hybrid integrated circuit device according to claim 1, wherein the substrate is provided with a through hole and a terminal pad on the surface opposite to the ball-shaped terminal mounting surface through the through hole.
パッドに、他の基板のボール状端子を接続して階層化し
たことを特徴とする請求項２記載の混成集積回路装置。3. The hybrid integrated circuit device according to claim 2, wherein the ball-shaped terminals of another substrate are connected to the terminal pads on the surface opposite to the ball-shaped terminal mounting surface to form a hierarchy.
る３本以上の溝を設けたことを特徴とする請求項１記載
の混成集積回路装置。4. The hybrid integrated circuit device according to claim 1, wherein the terminal pad surface is provided with three or more grooves passing through substantially the center of the terminal pad surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15172492A JPH05343605A (en) | 1992-06-11 | 1992-06-11 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15172492A JPH05343605A (en) | 1992-06-11 | 1992-06-11 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05343605A true JPH05343605A (en) | 1993-12-24 |
Family
ID=15524903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15172492A Pending JPH05343605A (en) | 1992-06-11 | 1992-06-11 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05343605A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6043559A (en) * | 1996-09-09 | 2000-03-28 | Intel Corporation | Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses |
| US6965166B2 (en) | 1999-02-24 | 2005-11-15 | Rohm Co., Ltd. | Semiconductor device of chip-on-chip structure |
-
1992
- 1992-06-11 JP JP15172492A patent/JPH05343605A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6043559A (en) * | 1996-09-09 | 2000-03-28 | Intel Corporation | Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses |
| US6440770B1 (en) | 1996-09-09 | 2002-08-27 | Intel Corporation | Integrated circuit package |
| US6965166B2 (en) | 1999-02-24 | 2005-11-15 | Rohm Co., Ltd. | Semiconductor device of chip-on-chip structure |
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