JPH05326894A - Wiring device - Google Patents
Wiring deviceInfo
- Publication number
- JPH05326894A JPH05326894A JP14796792A JP14796792A JPH05326894A JP H05326894 A JPH05326894 A JP H05326894A JP 14796792 A JP14796792 A JP 14796792A JP 14796792 A JP14796792 A JP 14796792A JP H05326894 A JPH05326894 A JP H05326894A
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- Japan
- Prior art keywords
- wiring
- signal processing
- signal
- rewiring
- initial
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、集積回路の自動設
計、特にゲートアレイ方式の概略配線設計において、配
線すべき信号の処理順序を自動的に制御し、配線を行う
配線装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring device for automatically controlling the processing order of signals to be wired and performing wiring in automatic design of integrated circuits, particularly in gate line type schematic wiring design. ..
【０００２】[0002]
【従来の技術】従来のゲートアレイ方式の概略配線設計
は、配線すべき信号の処理順序を特にきめることなく、
信号を一本ずつ最短経路で配線する初期配線と、配線が
混雑した箇所を引きはがして配線をし直す再配線とを行
う２段階方式が広く採用されている。2. Description of the Related Art A conventional gate-array type general wiring design does not require a particular processing order of signals to be wired.
A two-step method is widely used in which initial wiring for wiring signals one by one in the shortest route and rewiring for stripping a congested area and rewiring are widely used.
【０００３】[0003]
【発明が解決しようとする課題】従来の配線方法は以上
のように実施されているので、初期配線における信号の
配線順序が不適切であると、配線の局所混雑が多発し、
これによって経路改善を行うために要する再配線の処理
時間が大幅に増大するなどの問題点があった。Since the conventional wiring method is carried out as described above, if the wiring order of the signals in the initial wiring is improper, local congestion of the wiring frequently occurs,
As a result, there is a problem that the processing time for rewiring required to improve the route is significantly increased.
【０００４】この発明は上記のような従来の問題点を解
消するためになされたものであり、信号が通り得る最短
経路の数と配線の予想混雑度を考慮した信号処理順序を
決定して初期配線を行うことにより、再配線の処理時間
を増大することなく、局所混雑と経路の迂回の少ない配
線を実現できる配線装置を得ることを目的とする。The present invention has been made in order to solve the above-mentioned conventional problems, and determines the signal processing sequence in consideration of the number of shortest paths through which signals can pass and the expected congestion degree of wiring, and the initial stage. An object of the present invention is to obtain a wiring device that can realize wiring with less local congestion and route detouring without increasing the processing time for rewiring by performing wiring.
【０００５】[0005]
【課題を解決するための手段】この発明に係る配線装置
は、集積回路の論理的な接続情報および集積回路の構造
等の回路構造情報から経路未定である信号に対し信号処
理順序を決定する信号処理順序決定手段と、該信号処理
順序決定手段により決定した信号の処理順序に従って初
期配線を行う初期配線手段とを備え、再配線手段に、該
初期配線手段により配線された信号に対して再配線を行
わせて、配線経路情報を出力させるようにしたものであ
る。A wiring device according to the present invention is a signal for determining a signal processing order for a signal whose route is undetermined from logical connection information of an integrated circuit and circuit structure information such as a structure of the integrated circuit. The processing order determining means and the initial wiring means for performing the initial wiring according to the processing order of the signals determined by the signal processing order determining means are provided, and the rewiring means reroutes the signals wired by the initial wiring means. And the wiring route information is output.
【０００６】[0006]
【作用】この発明における信号処理順序決定手段は、チ
ャネルグラフ上で線路上の辺の辺長の和が最小であるよ
うな最短経路を求め、経路未定信号の最短経路が通過す
る領域に対して、すべて経路未定信号が通過する期待値
と配線格子数にもとづいて算出した配線容量より、信号
がその領域をどの程度通りやすいかを検出し、上記最短
経路上の各領域の予想混雑度より、ある経路未定信号の
取り得る最短経路のひとつが、回路上でどの程度通りや
すいかを検出し、ある経路未定信号の取り得る最短経路
の各々に対する通りやすさより、この信号が最短経路の
うちいずれかで実際に配線されるのはどの程度の期待度
かを検出し、上記最短経路の数が少ない程、また通りに
くい最短経路をもつもの程、先に配線処理を実施させる
ようにする。The signal processing order determining means in the present invention finds the shortest route such that the sum of the side lengths of the lines on the channel graph is the minimum, and determines the shortest route of the route undetermined signal for the region passing through. , The wiring capacity calculated based on the expected value and the number of wiring grids that all route-undecided signals pass, to detect how easily the signal passes through that area, and from the expected congestion degree of each area on the shortest path, One of the shortest routes that a certain route undetermined signal can take is detected in the circuit, and this signal is determined to be one of the shortest routes based on the ease of passing each shortest route that a certain route undetermined signal can take. Then, the degree of expectation that is actually routed is detected, and the wiring process is performed earlier as the number of the shortest routes is smaller or the shortest route is hard to pass.
【０００７】[0007]
実施例１．以下、この発明の一実施例を図について説明
する。図１において、１は集積回路の論理的な接続情
報、２は集積回路の構造等の回路構造情報、４はこれら
の各情報１，２から経路未定である信号に対し信号処理
順序を決定する信号処理順序決定手段である。Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 is logical connection information of an integrated circuit, 2 is circuit structure information such as a structure of the integrated circuit, and 4 is a signal processing order for a signal whose route is undecided from the respective information 1 and 2. It is a signal processing order determination means.
【０００８】また、５は信号処理順序決定手段４により
決定した信号の処理順序に従って初期配線を行う初期配
線手段、６は初期配線手段５により配線された信号に対
して再配線を行う再配線手段、７は再配線手段６により
出力される概略配線経路情報である。Reference numeral 5 denotes initial wiring means for performing initial wiring according to the signal processing order determined by the signal processing order determination means 4, and 6 is rewiring means for rewiring the signals wired by the initial wiring means 5. , 7 are schematic wiring route information output by the rewiring unit 6.
【０００９】さらに、上記信号処理順序決定手段４は、
図３で示すように、最短経路を求める手段８と、予想混
雑度を求める手段９と、最短経路の通りやすさを求める
手段１０と、信号の期待度を求める手段１１で構成され
る。Further, the signal processing order determining means 4 is
As shown in FIG. 3, it comprises means 8 for obtaining the shortest route, means 9 for obtaining the expected congestion degree, means 10 for obtaining the ease of passing the shortest route, and means 11 for obtaining the degree of expectation of the signal.
【００１０】以下に、２端子信号の場合の信号処理順序
決定手段４における上記４つの手段について、図４に示
すようなチャネルグラフを用いて説明する。まず、集積
回路を適当な間隔で水平方向に分割する。The above-mentioned four means in the signal processing order determining means 4 for a two-terminal signal will be described below with reference to a channel graph as shown in FIG. First, the integrated circuit is horizontally divided at appropriate intervals.
【００１１】次に、このような分割によって区切られた
領域（以下、区分領域という）に対応する頂点１２の集
合Ｖを頂点集合とし、隣接する二つの区分領域に対応す
る頂点対を結ぶ辺１３の集合Ｅを持つチャネルグラフＧ
＝（Ｖ，Ｅ）を作成する。Next, a set V of vertices 12 corresponding to a region divided by such division (hereinafter referred to as a segmented region) is defined as a vertex set, and an edge 13 connecting a pair of vertices corresponding to two adjacent segmented regions. A channel graph G with a set E of
= (V, E) is created.
【００１２】上記集合Ｅの各辺１３の内、水平方向の辺
１３には水平方向の配線格子数に対応した容量を、垂直
方向の辺１３には、垂直方向の配線格子数に対応した容
量を与える。この容量は図１に示す容量記憶テーブル３
に格納される。また、集合Ｅの各辺１３に、両端の頂点
１２に対応する区分領域の中心間の距離を表す辺長を与
える。信号が結ぶべき端子は、各端子の存在する区分領
域に対応した頂点に存在するものとする。Of the sides 13 of the set E, the side 13 in the horizontal direction has a capacity corresponding to the number of wiring grids in the horizontal direction, and the side 13 in the vertical direction has a capacity corresponding to the number of wiring grids in the vertical direction. give. This capacity is the capacity storage table 3 shown in FIG.
Stored in. Further, each side 13 of the set E is given a side length representing the distance between the centers of the divided areas corresponding to the vertices 12 at both ends. It is assumed that the terminals to which the signals are connected are located at the vertices corresponding to the divided areas where the terminals are located.
【００１３】このとき、最短経路を求める手段８はチャ
ネルグラフＧ上で、経路上の辺の辺長の和が最小である
ような経路を求める。最短経路は一般に複数個あるが、
その数は初期配線の処理の進行に伴い減少する。At this time, the means 8 for finding the shortest path finds a path on the channel graph G such that the sum of the side lengths of the sides on the path is the smallest. Generally, there are multiple shortest paths,
The number decreases as the initial wiring process progresses.
【００１４】ある信号が通り得る最短経路がなくなれ
ば、信号が結ぶべき２頂点を対角線とする矩形を上下左
右に１頂点分だけ拡張した矩形内での迂回経路を最短経
路の代用とする。初期配線の処理がさらに進んで迂回経
路もとれなくなれば、拡張した矩形を上下左右にさらに
１頂点分だけ拡張した矩形内での迂回経路を用いる。When there is no shortest path that a certain signal can pass through, a detour path in a rectangle obtained by expanding a rectangle whose two vertices to be connected by a signal are diagonal lines up and down, left and right is used as a substitute for the shortest path. When the initial wiring process further progresses and the detour route cannot be obtained, the detour route within the rectangle obtained by further extending the extended rectangle vertically and horizontally by one vertex is used.
【００１５】次に、予想混雑度を求める手段９では、経
路未定の信号は最短経路のうちのいずれかで配線され、
その信号の最短経路はいずれも等しい確率で選ばれ得る
と仮定し、現在信号処理順序を決定しようとする段階
で、経路未定信号の最短経路が通過する各辺に対してそ
の信号が通過する期待値を求め、ある辺における期待値
の合計と容量記憶テーブル３に格納された配線容量の逆
数の積を予想混雑度として与える。Next, in the means 9 for obtaining the expected congestion degree, a signal whose route has not been determined is routed on one of the shortest routes,
Assuming that the shortest path of the signal can be selected with equal probability, at the stage of trying to determine the current signal processing order, it is expected that the signal will pass for each side through which the shortest path of the undetermined route passes. The value is calculated, and the product of the sum of the expected values on a certain side and the reciprocal of the wiring capacity stored in the capacity storage table 3 is given as the expected congestion degree.
【００１６】さらに、最短経路の通りやすさを求める手
段１０は、最短経路上の各辺の予想混雑度の逆数の積を
その最短経路の通りやすさとして与える。すなわち、チ
ャネルグラフＧにおいて、経路未定の２端子信号ｓの最
短経路の集合をＰ＝｛ｐ1 ，ｐ2 ，…ｐ3 ｝とし、最短
経路ｐｉ（ｉ＝１，２，…，ｎ）上の辺の集合Ｚ、その
うちの一つの辺をωとすると予想混雑度がｈ（ω）のと
き、経路ｐｉの通りやすさを表す関数ｆは、ｆ（ｐｉ）
＝Π１／ｈ（ω）（ただし、ω∈Ｚ）のように定義す
る。Further, the means 10 for determining the easiness of passage of the shortest route gives the product of the reciprocal of the expected congestion degree of each side on the shortest route as the easiness of passage of the shortest route. That is, in the channel graph G, the set of shortest paths of the two-terminal signals s whose paths have not been determined is set as P = {p 1 , p 2 , ... P 3 }, and the shortest path pi (i = 1, 2, ..., N) If the expected congestion degree is h (ω) where ω is one of the set Z of the edges of, then the function f expressing the ease of passing the route pi is f (pi).
= Π1 / h (ω) (where ωεZ) is defined.
【００１７】また、信号の期待度を求める手段１１は、
ある経路に未定信号の通り得る最短経路の各々に対する
通りやすさの和を経路未定信号の期待度として与える。
経路未定の２端子信号ｓが最短経路ｐｉ（ｉ＝１，２，
…，ｎ）のうち、いずれかで実際に配線されることの期
待度は関数Ｆとして、Ｆ（ｓ）＝Σｆ（ｐｉ）で表わさ
れる。この関数Ｆが２端子信号の信号処理順序決定関数
である。The means 11 for obtaining the degree of expectation of a signal is
The sum of the ease of passage for each of the shortest routes that can pass an undetermined signal on a certain route is given as the degree of expectation of the route undetermined signal.
The shortest route pi (i = 1, 2,
, N), the degree of expectation of being actually wired in any one of them is expressed as a function F by F (s) = Σf (pi). This function F is a signal processing order determination function for a two-terminal signal.
【００１８】なお、上記実施例では２端子信号の場合に
ついて述べたが、３端子以上を持つ多端子信号に拡張し
た場合には、多端子信号ｋを２端子信号ｋ１，ｋ２，
…，Ｋｍの部分信号に分離する。多端子信号の部分信号
のうち、一つでも配線の困難が予想されるものであれ
ば、その多端子信号は先に配線すべきなので、多端子信
号ｋに関する信号処理順序決定関数Ｆは、Ｆ（ｋ）＝Ｍ
ｉｎ｛Ｆ（ｋ１），…，Ｆ（ｋｍ）｝で表わされる。こ
の信号処理順序決定関数Ｆ値の小さい信号程配線困難で
あると考えられ、信号処理順序がここで決定する。In the above embodiment, the case of a two-terminal signal is described, but when the multi-terminal signal having three or more terminals is expanded, the multi-terminal signal k is converted into a two-terminal signal k1, k2.
..., Km is separated into partial signals. If even one of the partial signals of the multi-terminal signal is expected to be difficult to wire, the multi-terminal signal should be wired first. Therefore, the signal processing order determination function F for the multi-terminal signal k is F (K) = M
It is represented by in {F (k1), ..., F (km)}. It is considered that the smaller the signal processing order determination function F value is, the more difficult the wiring is, and the signal processing order is determined here.
【００１９】次に動作を、図２のフローチャートに沿っ
て説明する。まず、初期配線一括処理本数をＮに設定し
（ステップＳ１）、次に経路未定の信号があるか否かを
調べ（ステップＳ２）、ある場合には信号処理順序決定
手段４は接続情報１と回路構造情報２を読み込み、現
在、経路未定である信号に対し信号処理順序決定関数値
を算出し、信号処理順序を決定する（ステップＳ３）。Next, the operation will be described with reference to the flowchart of FIG. First, the initial wiring batch processing number is set to N (step S1), and then it is checked whether or not there is a signal whose route has not been determined (step S2). The circuit structure information 2 is read, the signal processing order determination function value is calculated for the signal whose route is currently undetermined, and the signal processing order is determined (step S3).
【００２０】続いて、初期配線手段５は、信号処理順序
決定手段４により算出した信号処理順序決定関数値の小
さい信号から順番に処理をする。このとき、各信号につ
いて配線容量が正の辺のみを通り、かつコスト最少の経
路を求める（ステップＳ４）。Subsequently, the initial wiring means 5 processes in order from the signal having the smallest signal processing order determining function value calculated by the signal processing order determining means 4. At this time, for each signal, a path that passes only the side where the wiring capacitance is positive and has the lowest cost is obtained (step S4).
【００２１】信号処理順序決定手段４で順序決めの要因
となる信号が通り得る最短経路の数と配線の予想混雑度
は初期配線の処理の進行に伴って変化するので、ある程
度の本数を初期配線する度に信号処理順序決定手段４に
制御を戻し、信号処理順序を決定しなおす（ステップＳ
２）。Since the number of the shortest paths through which the signals that cause the order determination in the signal processing order determination means 4 and the expected congestion degree of the wiring change as the processing of the initial wiring progresses, a certain number of the initial wiring is set. Each time, the control is returned to the signal processing order determining means 4 and the signal processing order is determined again (step S).
2).
【００２２】こうして、信号処理順序決定手段４および
初期配線手段５による処理が繰り返され、ステップＳ２
で未処理の信号が無いと判断されると、再配線手段６に
進む（ステップＳ５）。In this way, the processing by the signal processing order determining means 4 and the initial wiring means 5 is repeated, and step S2 is performed.
If it is determined that there is no unprocessed signal, the process proceeds to the rewiring unit 6 (step S5).
【００２３】また、再配線手段６は初期配線手段５によ
り配線された信号に対して、配線容量がある値以下にな
るような混雑した辺を通る信号をひきはがして、経路を
決め直すことを繰り返し、概略の配線経路情報７を出力
する（ステップＳ５）。Further, the rewiring means 6 removes the signal wired by the initial wiring means 5 from a signal passing through a congested side where the wiring capacitance becomes a certain value or less, and redetermines the route. The outline wiring route information 7 is repeatedly output (step S5).
【００２４】そして、上記初期配線手段５と再配線手段
６において、信号の概略配線経路が決まる度にその信号
が通る各辺の配線容量を各々１ずつ引き、容量記憶テー
ブル３の内容を更新する。In each of the initial wiring means 5 and the rewiring means 6, each time the rough wiring route of a signal is determined, the wiring capacitance of each side through which the signal is passed is subtracted by 1 to update the contents of the capacitance storage table 3. ..
【００２５】[0025]
【発明の効果】以上のように、この発明によれば、集積
回路の論理的な接続情報および集積回路の構造等の回路
構造情報から経路未定である信号に対し信号処理順序を
決定する信号処理順序決定手段と、該信号処理順序決定
手段により決定した信号の処理順序に従って初期配線を
行う初期配線手段とを備え、再配線手段に、該初期配線
手段により配線された信号に対して再配線を行わせて、
配線経路情報を出力させるように構成したので、初期配
線の段階で局所混雑の少ない配線ができ、この結果再配
線の処理時間を従来より短くでき、詳細配線において配
線不能の発生を防ぐことができるとともに、経路の不要
な迂回を少なくして、回路の性能も良好に保つことがで
きるものが得られる効果がある。As described above, according to the present invention, the signal processing for determining the signal processing order for the signal whose route is undetermined from the logical connection information of the integrated circuit and the circuit structure information such as the structure of the integrated circuit. An order determining unit and an initial wiring unit that performs initial wiring in accordance with the processing order of the signals determined by the signal processing order determining unit are provided, and the rewiring unit reroutes the signals wired by the initial wiring unit. Let me do it
Since it is configured to output the wiring route information, wiring with less local congestion can be performed at the stage of initial wiring, and as a result, the processing time for rewiring can be shortened as compared with the conventional method, and it is possible to prevent the occurrence of wiring failure in detailed wiring. At the same time, there is an effect that unnecessary detours of the route can be reduced and good circuit performance can be maintained.
【図１】この発明の一実施例による配線装置を示すブロ
ック図である。FIG. 1 is a block diagram showing a wiring device according to an embodiment of the present invention.
【図２】この発明の一実施例による配線装置による配線
処理の流れを示すフローチャートである。FIG. 2 is a flowchart showing a flow of wiring processing by the wiring device according to the embodiment of the present invention.
【図３】この発明の中心部分である信号処理順序決定手
段の内部構成を示すブロック図である。FIG. 3 is a block diagram showing an internal configuration of a signal processing order determining unit, which is a central part of the present invention.
【図４】この発明の一実施例によるチャンネルグラフの
例を示す説明図である。FIG. 4 is an explanatory diagram showing an example of a channel graph according to an embodiment of the present invention.
１ 接続情報 ２ 回路構造情報 ４ 信号処理順序決定手段 ５ 初期配線手段 ６ 再配線手段 ７ 概略配線経路情報 1 Connection Information 2 Circuit Structure Information 4 Signal Processing Order Determining Means 5 Initial Wiring Means 6 Rewiring Means 7 General Wiring Route Information
Claims (1)
回路の構造等の回路構造情報から経路未定である信号に
対し信号処理順序を決定する信号処理順序決定手段と、
該信号処理順序決定手段により決定した信号の処理順序
に従って初期配線を行う初期配線手段と、該初期配線手
段により配線された信号に対して再配線を行い配線経路
情報を出力する再配線手段とを備えた配線装置。1. A signal processing order determining means for determining a signal processing order for a signal whose route is undecided from logical connection information of the integrated circuit and circuit structure information such as a structure of the integrated circuit.
Initial wiring means for performing initial wiring according to the processing order of the signals determined by the signal processing order determining means; and rewiring means for rewiring the signals wired by the initial wiring means and outputting wiring route information. Wiring device equipped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14796792A JPH05326894A (en) | 1992-05-15 | 1992-05-15 | Wiring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14796792A JPH05326894A (en) | 1992-05-15 | 1992-05-15 | Wiring device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05326894A true JPH05326894A (en) | 1993-12-10 |
Family
ID=15442150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14796792A Pending JPH05326894A (en) | 1992-05-15 | 1992-05-15 | Wiring device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05326894A (en) |
-
1992
- 1992-05-15 JP JP14796792A patent/JPH05326894A/en active Pending
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