JPH05324263A - Huffman code zrl processing circuit - Google Patents
Huffman code zrl processing circuitInfo
- Publication number
- JPH05324263A JPH05324263A JP13383492A JP13383492A JPH05324263A JP H05324263 A JPH05324263 A JP H05324263A JP 13383492 A JP13383492 A JP 13383492A JP 13383492 A JP13383492 A JP 13383492A JP H05324263 A JPH05324263 A JP H05324263A
- Authority
- JP
- Japan
- Prior art keywords
- code
- zrl
- signal
- eob
- huffman
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Image Processing (AREA)
- Compression Of Band Width Or Redundancy In Fax (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ハフマン符号化、特に
二次元ハフマン符号化を用いたディジタル画像信号処理
装置のＺＲＬ処理回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ZRL processing circuit of a digital image signal processing apparatus using Huffman coding, particularly two-dimensional Huffman coding.
【０００２】[0002]
【従来の技術】情報の伝達効率を高めるため、情報中の
個々のデータに於いて出現頻度が高いデータ程、其のデ
ータの変換符号長を短く取るという可変長符号を用いた
符号化装置が一般に使用されている。2. Description of the Related Art In order to improve the transmission efficiency of information, there is an encoding device using a variable length code in which the conversion code length of each piece of data in the information having a higher appearance frequency is shorter. Commonly used.
【０００３】この可変長符号の一種として広く用いられ
ているハフマン符号とは、ある情報源から出力される情
報中の斯くデータの生起確率が均一でなく互いに相関が
ない場合に、データ出現頻度の高い情報ほど短い符号に
変換することで、情報伝達量を効率的に圧縮するもので
ある。The Huffman code, which is widely used as a type of variable-length code, means the occurrence frequency of data when the occurrence probabilities of such data in information output from a certain information source are not uniform and do not correlate with each other. By converting higher information into shorter codes, the amount of information transmission is efficiently compressed.
【０００４】上記ハフマン符号方法を利用して変換した
データ列の例を図３−ａに示す。An example of a data string converted by using the above Huffman coding method is shown in FIG.
【０００５】図に於いて、ＤＣ ２１は画像符号の開始
を示す直流成分符号であり、ＺＲＬ２２は０が１６個続
く度に出力される符号であり、Ａ ２３は有効係数とよ
ばれる各データの符号、ＥＯＢはデータブロックの終わ
りを示す符号である。In the figure, DC 21 is a DC component code indicating the start of an image code, ZRL 22 is a code output every 16 consecutive 0's, and A 23 is the effective coefficient of each data. The code, EOB, is a code indicating the end of the data block.
【０００６】図で示されるように、有効係数符号とＥＯ
Ｂ符号の間にもＺＲＬ符号が生成されている。As shown in the figure, the effective coefficient code and EO
The ZRL code is also generated between the B codes.
【０００７】[0007]
【発明が解決しようとする課題】このように、従来のハ
フマン符号処理回路では、ブロック中の位置を問わず、
０が１６個続いた時点で常にＺＲＬ符号を出力してお
り、有効係数符号とＥＯＢ符号の間でも０が１６個以上
続くと、最大３個のＺＲＬ符号を出力する。As described above, in the conventional Huffman code processing circuit, regardless of the position in the block,
The ZRL code is always output when 16 0s continue, and when 16 or more 0s continue between the effective coefficient code and the EOB code, a maximum of 3 ZRL codes are output.
【０００８】本来、ＥＯＢ符号は、ＥＯＢ符号の後は当
該ブロックの最後までデータ全てが０である事を意味し
ており、有効係数符号とＥＯＢ符号の間のＺＲＬ符号は
不必要に冗長度の増大させていた。Originally, the EOB code means that after the EOB code, all the data is 0 until the end of the block, and the ZRL code between the effective coefficient code and the EOB code has unnecessary redundancy. Was increasing.
【０００９】本発明は、こような不必要なＺＲＬ符号を
除去するためになされたものである。The present invention has been made to remove such unnecessary ZRL codes.
【００１０】[0010]
【課題を解決するための手段】ハフマン符号変換部か
ら、入力されたコードデータに対応して変換し出力され
るハフマン符号とは別に、これと対応してＺＲＬ信号、
有効係数信号、ＥＯＢ信号の３種の信号を出力し、この
３種の信号を受けて指示を発するＺＲＬ処理指示部と、
この指示部からの指示をうけ所定のＺＲＬ処理を実行す
るＺＲＬ処理部とを設け、ＥＯＢ符号に先行するＺＲＬ
符号の送出を除去する様構成した。In addition to the Huffman code that is converted and output from the Huffman code conversion unit corresponding to the input code data, a ZRL signal corresponding to the Huffman code,
A ZRL processing instruction section that outputs three types of signals, an effective coefficient signal and an EOB signal, and that issues an instruction in response to these three types of signals;
A ZRL processing unit that executes a predetermined ZRL process in response to an instruction from this instruction unit is provided, and the ZRL preceding the EOB code is provided.
It is configured to eliminate the transmission of the code.
【００１１】[0011]
【実施例】本発明の一実施例について図１のＺＲＬ処理
回路ブロック図、図２の実施例フロー図、図３の符号化
データ構成を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the block diagram of the ZRL processing circuit of FIG. 1, the flow chart of the embodiment of FIG. 2 and the encoded data structure of FIG.
【００１２】図１のＺＲＬ処理回路ブロック図におい
て、１はハフマン符号変換部で、ラン長１１、カテゴリ
１２を入力してＺＲＬ信号１３、有効係数信号１４、Ｅ
ＯＢ信号１５、符号データ１６、データ長１７を出力す
る。In the block diagram of the ZRL processing circuit of FIG. 1, reference numeral 1 denotes a Huffman code conversion unit, which inputs a run length 11 and a category 12 to input a ZRL signal 13, an effective coefficient signal 14, E.
The OB signal 15, code data 16 and data length 17 are output.
【００１３】２は、処理指示部で、ハフマン符号変換部
からのＺＲＬ信号１３、有効係数信号１４、ＥＯＢ信号
１５を受け、ＺＲＬ処理回路３に次のごとく指示を出
す、即ち、ＺＲＬ信号を受けると（ステップ２０２）、
内部カウンタのカウント数ＣがＣ＜３の場合はカウンタ
を１だけカウントアップしＣ＝Ｃ＋１とし（ステップ２
０８）、Ｃ＝３の場合はＺＲＬ符号を出力するよう指示
する（ステップ２０７）。A processing instruction unit 2 receives the ZRL signal 13, the effective coefficient signal 14, and the EOB signal 15 from the Huffman code conversion unit, and issues the following instruction to the ZRL processing circuit 3, that is, receives the ZRL signal. And (step 202),
When the count number C of the internal counter is C <3, the counter is incremented by 1 and C = C + 1 (step 2
08), and when C = 3, an instruction is issued to output the ZRL code (step 207).
【００１４】有効係数信号を受けると（ステップ２０
３）、カウント数と同数のＺＲＬ符号と（ステップ２１
０〜２１４）、所定の有効変換データを出力するよう指
示を出し（ステップ２１５）、カウント数をリセットし
Ｃ＝０とする（ステップ２１６）。When the effective coefficient signal is received (step 20)
3) the number of ZRL codes equal to the number of counts (step 21
0 to 214), an instruction is issued to output predetermined valid conversion data (step 215), and the count number is reset to C = 0 (step 216).
【００１５】ＥＯＢ信号を受けると（ステップ２０
４）、ＥＯＢ符号を出力するよう指示し（ステップ２１
７）、カウント数をリセットしＣ＝０とする（ステップ
２１８）。When the EOB signal is received (step 20)
4) instruct to output the EOB code (step 21
7) Then, the count number is reset to C = 0 (step 218).
【００１６】以上の処理をデータが終了するまで繰り返
し終了する（ステップ２０５）。The above process is repeated until the data is completed (step 205).
【００１７】３は、ＺＲＬ処理回路で、指示部２の指示
を受けハフマン符号変換部からの符号データを出力す
る。A ZRL processing circuit 3 receives the instruction from the instruction unit 2 and outputs the code data from the Huffman code conversion unit.
【００１８】即ち、ＺＲＬ符号が入力された場合は、次
に有効係数信号が来るまで送出を保留し、もしＥＯＢ符
号が来た場合はＺＲＬ符号を送出しない。That is, when the ZRL code is input, the transmission is suspended until the next effective coefficient signal arrives, and when the EOB code comes, the ZRL code is not transmitted.
【００１９】なお、ＺＲＬ符号はＺＲＬ符号発生部４で
発生させるが、ハフマン符号変換部１で生成したＺＲＬ
符号を記憶させ使用しても良い。Although the ZRL code is generated by the ZRL code generation unit 4, the ZRL code generated by the Huffman code conversion unit 1 is used.
The code may be stored and used.
【００２０】図４は本発明の第２の実施例のブロック図
である。FIG. 4 is a block diagram of the second embodiment of the present invention.
【００２１】[0021]
【発明の効果】以上説明したように本発明は、アップカ
ウンタを指示部に取り付ける事により、図３−ｂの出力
データ構成の例に示した様に、有効係数符号とＥＯＢ符
号間に生成したＺＲＬ符号をすべて除去することが出来
るので符号量の増大を防止するという優れた効果を発揮
する。As described above, according to the present invention, by attaching the up-counter to the instruction section, as shown in the example of the output data structure of FIG. 3B, it is generated between the effective coefficient code and the EOB code. Since all ZRL codes can be removed, an excellent effect of preventing an increase in the code amount is exhibited.
【図１】実施例の回路ブロック図FIG. 1 is a circuit block diagram of an embodiment.
【図２】実施例のフロー図FIG. 2 is a flowchart of an embodiment.
【図３】従来処理とＺＲＬ処理回路の出力データブロッ
ク図FIG. 3 is an output data block diagram of a conventional processing and ZRL processing circuit.
【図４】第２の実施例の回路ブロック図FIG. 4 is a circuit block diagram of a second embodiment.
１ ハフマン符号変換部 １１ ラン長データ １２ カテゴリデータ １３ ＺＲＬ信号 １４ 有効係数信号 １５ ＥＯＢ信号 １６ 符号データ １７ データ長 ２ 処理指示部 ３ ＺＲＬ処理回路 ４ ＺＲＬ符号発生部 ２１ 画像成分の始まりである直流成分 ２２ ラン長１６個並びの符号 ２３ 有効係数 ２４ ＥＮＤ ＯＦ ＢＬＯＣＫ 1 Huffman code conversion unit 11 Run length data 12 Category data 13 ZRL signal 14 Effective coefficient signal 15 EOB signal 16 Code data 17 Data length 2 Processing instruction unit 3 ZRL processing circuit 4 ZRL code generation unit 21 DC component at the beginning of image component 22 Codes with 16 run lengths arranged 23 Effective coefficient 24 END OF BLOCK
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成５年８月１０日[Submission date] August 10, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１３[Correction target item name] 0013
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１３】 ２は、処理指示部で、ハフマン符号変換
部１からのＺＲＬ信号１３、有効係数信号１４、ＥＯＢ
信号１５を受け、ＺＲＬ処理回路３に指示を出し、即
ち、ＺＲＬ信号４を受けると（ステップ２０２）、内部
カウンタのカウント数を１だけカウントアップしてＣ＝
Ｃ＋１とする（ステップ２０８）。Reference numeral 2 denotes a processing instruction unit, which is a ZRL signal 13 from the Huffman code conversion unit 1, an effective coefficient signal 14, and an EOB.
When the signal 15 is received and an instruction is given to the ZRL processing circuit 3, that is, when the ZRL signal 4 is received (step 202), the count number of the internal counter is incremented by 1 and C =
C + 1 is set (step 208).
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図２[Name of item to be corrected] Figure 2
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図２】 [Fig. 2]
Claims (1)
するハフマン符号変換部を備えたハフマン符号化装置に
於いて、 前記ハフマン符号変換部からのＺＲＬ（ＺＥＲＯ ＲＵ
Ｎ ＬＥＮＧＴＨ）信号、有効係数信号、ＥＯＢ（ＥＮ
Ｄ ＯＦ ＢＬＯＣＫ）信号入力に対応して指示を発す
るＺＲＬ処理指示部と、前記ＺＲＬ処理指示部からの指
示をうけ所定のＺＲＬ処理を実行するＺＲＬ処理部とを
設け、 ＥＯＢ符号に先行するＺＲＬ符号を除去する様構成した
ことを特徴とするハフマン符号ＺＲＬ処理回路。1. A Huffman coding apparatus including a Huffman code conversion unit for converting code data into a corresponding Huffman code, wherein a ZRL (ZERO RU) from the Huffman code conversion unit is used.
N LENGTH) signal, effective coefficient signal, EOB (EN
A ZRL processing instruction section for issuing an instruction in response to a D OF BLOCK) signal input and a ZRL processing section for executing a predetermined ZRL processing in response to an instruction from the ZRL processing instruction section, and a ZRL code preceding the EOB code A Huffman code ZRL processing circuit characterized by being configured to remove
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13383492A JPH05324263A (en) | 1992-05-26 | 1992-05-26 | Huffman code zrl processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13383492A JPH05324263A (en) | 1992-05-26 | 1992-05-26 | Huffman code zrl processing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05324263A true JPH05324263A (en) | 1993-12-07 |
Family
ID=15114134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13383492A Pending JPH05324263A (en) | 1992-05-26 | 1992-05-26 | Huffman code zrl processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05324263A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091856A (en) * | 1996-09-05 | 2000-07-18 | Mitsubishi Electric Semiconductor Software Co., Ltd | Picture encoding device for compressing picture data |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0377477A (en) * | 1989-08-19 | 1991-04-03 | Victor Co Of Japan Ltd | Method and apparatus for variable length coding |
-
1992
- 1992-05-26 JP JP13383492A patent/JPH05324263A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0377477A (en) * | 1989-08-19 | 1991-04-03 | Victor Co Of Japan Ltd | Method and apparatus for variable length coding |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091856A (en) * | 1996-09-05 | 2000-07-18 | Mitsubishi Electric Semiconductor Software Co., Ltd | Picture encoding device for compressing picture data |
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