JPH053199A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH053199A JPH053199A JP11204291A JP11204291A JPH053199A JP H053199 A JPH053199 A JP H053199A JP 11204291 A JP11204291 A JP 11204291A JP 11204291 A JP11204291 A JP 11204291A JP H053199 A JPH053199 A JP H053199A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon oxide
- silicon nitride
- layer
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に高周波用バイポーラ集積回路の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high frequency bipolar integrated circuit.
【０００２】[0002]
【従来の技術】図２（ａ）〜（ｄ）及び図３（ａ）〜
（ｄ）は従来の半導体装置の製造方法を説明するための
工程順に示した半導体チップの断面図である。2. Description of the Related Art FIGS. 2 (a)-(d) and 3 (a)-
(D) is sectional drawing of the semiconductor chip shown in order of process for demonstrating the manufacturing method of the conventional semiconductor device.
【０００３】まず、図２（ａ）に示すように、Ｐ型のシ
リコン基板１にＮ+ 型の埋込層２及びＮ- 型のエピタキ
シャル層３を形成した後、エピタキシャル層３の表面を
熱酸化して酸化シリコン膜４を０．５μｍの厚さに形成
する。次に、写真蝕刻法により酸化シリコン膜４を選択
的にエッチングして開孔部を形成し、酸化シリコン膜４
をマスクとしてＰ型の不純物の高濃度に拡散して深さ
１．２μｍのＰ型拡散層５を形成する。First, as shown in FIG. 2A, after an N + type buried layer 2 and an N − type epitaxial layer 3 are formed on a P type silicon substrate 1, the surface of the epitaxial layer 3 is heated. Oxidation is performed to form a silicon oxide film 4 with a thickness of 0.5 μm. Next, the silicon oxide film 4 is selectively etched by a photo-etching method to form openings, and the silicon oxide film 4 is formed.
Is used as a mask to diffuse a high concentration of P-type impurities to form a P-type diffusion layer 5 having a depth of 1.2 μm.
【０００４】次に、図２（ｂ）に示すように、酸化シリ
コン膜４を全面に亘りエッチング除去した後、Ｐ型拡散
層５を含むエピタキシャル層３の表面を熱酸化して厚さ
５０ｎｍの酸化シリコン膜６と、厚さ１５０ｎｍの窒化
シリコン膜７を順次に堆積する。次に、写真蝕刻法によ
り窒化シリコン膜７を選択的にエッチングして除去す
る。Next, as shown in FIG. 2B, after the silicon oxide film 4 is entirely removed by etching, the surface of the epitaxial layer 3 including the P-type diffusion layer 5 is thermally oxidized to a thickness of 50 nm. A silicon oxide film 6 and a silicon nitride film 7 having a thickness of 150 nm are sequentially deposited. Next, the silicon nitride film 7 is selectively etched and removed by photolithography.
【０００５】次に、図２（ｃ）に示すように、窒化シリ
コン膜７をマスクとしてＰ型拡散層５及びエピタキシャ
ル層３を熱酸化して酸化シリコン膜８を１．５μｍの厚
さに形成する。Next, as shown in FIG. 2C, the P-type diffusion layer 5 and the epitaxial layer 3 are thermally oxidized using the silicon nitride film 7 as a mask to form a silicon oxide film 8 with a thickness of 1.5 μm. To do.
【０００６】次に、図２（ｄ）に示すように、酸化シリ
コン膜８をエッチング除去して溝を設けた後熱酸化によ
る厚さ５０ｎｍの酸化シリコン膜９を形成する。次に、
溝直下のＰ型シリコン基板１に反転防止用のＰ+ 型拡散
層２４を形成した後、全面に厚さ５０ｎｍの窒化シリコ
ン膜１０を形成する。Next, as shown in FIG. 2D, the silicon oxide film 8 is removed by etching to form a groove, and then a silicon oxide film 9 having a thickness of 50 nm is formed by thermal oxidation. next,
After the P + type diffusion layer 24 for preventing inversion is formed on the P type silicon substrate 1 immediately below the groove, the silicon nitride film 10 having a thickness of 50 nm is formed on the entire surface.
【０００７】次に、図３（ａ）に示すように、異方性ド
ライエッチング法により上面からみて影となる部分以外
の窒化シリコン膜１０をエッチング除去した後、熱酸化
により厚さ１．５μｍの厚い酸化シリコン膜１１を形成
する。次に、窒化シリコン膜１０，７を順次エッチング
し除去する。Next, as shown in FIG. 3A, the silicon nitride film 10 other than the shadowed portion as seen from the upper surface is removed by etching by an anisotropic dry etching method, and then a thickness of 1.5 μm is obtained by thermal oxidation. Thick silicon oxide film 11 is formed. Next, the silicon nitride films 10 and 7 are sequentially etched and removed.
【０００８】次に、図３（ｂ）に示すように、全面に窒
化シリコン膜１２を０．１μｍの厚さに堆積する。Next, as shown in FIG. 3B, a silicon nitride film 12 is deposited on the entire surface to a thickness of 0.1 μm.
【０００９】次に、図３（ｃ）に示すように、写真蝕刻
法により、窒化シリコン膜１２及び酸化シリコン膜６を
選択的に順次にエッチングして開孔部を設け、窒化シリ
コン膜１２をマスクとしてＮ型の不純物を熱拡散して埋
込層２に達するコレクタ引出領域１４を形成する。Next, as shown in FIG. 3C, the silicon nitride film 12 and the silicon oxide film 6 are selectively and sequentially etched by a photo-etching method to form an opening, and the silicon nitride film 12 is formed. As a mask, N type impurities are thermally diffused to form collector extraction region 14 reaching buried layer 2.
【００１０】次に、図３（ｄ）に示すように、窒化シリ
コン膜１２及び酸化シリコン膜６を全面エッチング除去
した後、エピタキシャル層３の表面を熱酸化して酸化シ
リコン膜１５を５０ｎｍの厚さに形成する。次に、エピ
タキシャル層３の表面にホウ素イオンを加速エネルギー
４０ｋｅＶ，ドーズ量２×１０5 ｃｍ-2で選択的にイオ
ン注入して高濃度ベース拡散層１６を形成し、同様にホ
ウ素イオンを加速エネルギー３０ｋｅＶ，ドーズ量１×
１０14ｃｍ-2で選択的にイオン注入して活性ベース拡散
層１７を形成した後、窒化シリコン膜１８を０．１μｍ
の厚さに形成する。次に写真蝕刻法により、窒化シリコ
ン膜１８及び酸化シリコン膜１５を選択的に順次エッチ
ング除去してエミッタ拡散窓、及びコレクタコンタクト
窓を開孔した後、気相成長法によりポリシリコン層１９
を０．２μｍの厚さに形成してヒ素イオンを加速エネル
ギー７０ｋｅＶ，ドーズ量１×１０16ｃｍ-2でイオン注
入した後、熱処理して深さ０．３μｍのエミッタ拡散層
２０を形成する。次に、窒化シリコン膜１８及び酸化シ
リコン膜１５を選択的に開孔してベースコンタクト窓を
形成し、全面にアルミニウム層を１．５μｍの厚さに堆
積し、写真蝕刻法によりアルミニウム層及びポリシリコ
ン層１９を選択的にエッチングしてパターニングし、エ
ミッタ電極２１，ベース電極２２，コレクタ電極２３の
夫々を形成する。Next, as shown in FIG. 3D, after the silicon nitride film 12 and the silicon oxide film 6 are entirely removed by etching, the surface of the epitaxial layer 3 is thermally oxidized to form a silicon oxide film 15 with a thickness of 50 nm. To form. Next, boron ions are selectively ion-implanted on the surface of the epitaxial layer 3 at an acceleration energy of 40 keV and a dose amount of 2 × 10 5 cm −2 to form a high-concentration base diffusion layer 16, and similarly, the boron ions are accelerated at an acceleration energy. 30 keV, dose 1x
After selectively implanting ions at 10 14 cm -2 to form the active base diffusion layer 17, the silicon nitride film 18 is formed to a thickness of 0.1 μm.
To the thickness of. Next, the silicon nitride film 18 and the silicon oxide film 15 are selectively and sequentially removed by photoetching to open the emitter diffusion window and the collector contact window, and then the polysilicon layer 19 is formed by vapor phase epitaxy.
Is formed to a thickness of 0.2 μm, arsenic ions are ion-implanted at an acceleration energy of 70 keV and a dose of 1 × 10 16 cm −2 , and then heat-treated to form an emitter diffusion layer 20 having a depth of 0.3 μm. Next, the silicon nitride film 18 and the silicon oxide film 15 are selectively opened to form a base contact window, an aluminum layer is deposited to a thickness of 1.5 μm on the entire surface, and the aluminum layer and the poly layer are formed by photolithography. The silicon layer 19 is selectively etched and patterned to form the emitter electrode 21, the base electrode 22, and the collector electrode 23, respectively.
【００１１】[0011]
【発明が解決しようとする課題】この従来の半導体装置
は、上面よりコレクタ電極を取り出す必要がある為、通
常Ｎ型の不純物を高濃度で選択的に熱拡散することによ
り埋込層へ接続させてコレクタ引出領域を設けている
が、この熱拡散のマスキング層として窒化シリコン膜が
一般的に用いられる為、どうしてもＮ型の高濃度拡散層
の周囲に結晶欠陥が発生しやすくなり、半導体チップの
良品率を低下させるという問題があり、この傾向は半導
体基板として結晶面方位（１１１）を用いたときに特に
顕著にあらわれていた。In this conventional semiconductor device, it is necessary to take out the collector electrode from the upper surface. Therefore, normally, N-type impurities are selectively thermally diffused at a high concentration to be connected to the buried layer. However, since a silicon nitride film is generally used as a masking layer for this thermal diffusion, crystal defects are apt to occur around the N-type high-concentration diffusion layer and the semiconductor chip of the semiconductor chip is inevitable. There is a problem of decreasing the non-defective rate, and this tendency has been particularly remarkable when the crystal plane orientation (111) is used as the semiconductor substrate.
【００１２】[0012]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、一導電型半導体基板の一主面に逆導電型埋込
層を設け前記埋込層を含む表面に逆導電型エピタキシャ
ル層を設ける工程と、前記エピタキシャル層を選択的に
熱酸化して前記半導体基板に達する厚い酸化膜を形成し
て素子形成領域を区画する工程と、前記素子形成領域の
表面を熱酸化して設けた酸化膜の上に窒化シリコン膜と
酸化シリコン膜を順次積層して設ける工程と、前記素子
形成領域上の前記酸化シリコン膜及び窒化シリコン膜並
びに酸化膜を順次エッチングして開孔部を設ける工程と
前記酸化シリコン膜及び窒化シリコン膜をマスクとして
前記開孔部の素子形成領域に逆導電型不純物を導入して
前記埋込層に達する逆導電型拡散層を形成する工程とを
含んで構成される。According to a method of manufacturing a semiconductor device of the present invention, a reverse conductivity type buried layer is provided on one main surface of a single conductivity type semiconductor substrate, and a reverse conductivity type epitaxial layer is formed on a surface including the buried layer. And a step of selectively thermally oxidizing the epitaxial layer to form a thick oxide film reaching the semiconductor substrate to partition the element forming region, and thermally oxidizing the surface of the element forming region. A step of sequentially laminating a silicon nitride film and a silicon oxide film on the oxide film, and a step of sequentially etching the silicon oxide film, the silicon nitride film, and the oxide film on the element forming region to provide an opening. A step of introducing a reverse conductivity type impurity into the element forming region of the opening using the silicon oxide film and the silicon nitride film as a mask to form a reverse conductivity type diffusion layer reaching the buried layer.
【００１３】[0013]
【実施例】次に、本発明について図面を参照しながら説
明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【００１４】図１（ａ）〜（ｃ）は本発明の一実施例を
説明するための工程順に示した半導体チップの断面図で
ある。FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.
【００１５】まず、図１（ａ）に示すように、図２
（ａ）〜（ｄ）及び図３（ａ）により説明した従来例と
同様の工程でＰ型シリコン基板１にＮ+ 型の埋込層２、
Ｎ- 型のエピタキシャル層３、酸化シリコン膜６，１１
及びＰ+ 型拡散層２４の夫々を形成する。First, as shown in FIG.
The N + type buried layer 2 is formed on the P type silicon substrate 1 in the same process as the conventional example described with reference to FIGS.
N − type epitaxial layer 3, silicon oxide films 6, 11
And the P + type diffusion layer 24 are formed.
【００１６】次に、図１（ｂ）に示すように、酸化シリ
コン膜６，１１の表面に０．１μｍの厚さの窒化シリコ
ン膜１２及び厚さ３０ｎｍの酸化シリコン膜１３を順次
堆積する。Next, as shown in FIG. 1B, a silicon nitride film 12 having a thickness of 0.1 μm and a silicon oxide film 13 having a thickness of 30 nm are sequentially deposited on the surfaces of the silicon oxide films 6 and 11.
【００１７】次に、図１（ｃ）に示すように、酸化シリ
コン膜１３，窒化シリコン膜１２，酸化シリコン膜６を
選択的に順次エッチングして除去し、コレクタ拡散窓を
開孔した後、酸化シリコン膜１３及び窒化シリコン膜１
２をマスクとしてＮ型不純物を高濃度に熱拡散して埋込
層２に達するコレクタ引出領域１４を形成する。Next, as shown in FIG. 1C, the silicon oxide film 13, the silicon nitride film 12, and the silicon oxide film 6 are selectively and sequentially etched to be removed, and a collector diffusion window is opened. Silicon oxide film 13 and silicon nitride film 1
2 is used as a mask to form a collector extraction region 14 which reaches the buried layer 2 by thermally diffusing N-type impurities into a high concentration.
【００１８】以後、酸化シリコン膜１３，窒化シリコン
膜１２，酸化シリコン膜６を順次にエッチング除去した
後、図３（ｄ）に示した従来例と同様の工程により、高
濃度ベース拡散層１６，活性ベース拡散層１７，エミッ
タ拡散層２０の夫々を形成し、半導体集積回路を構成す
る。After that, after the silicon oxide film 13, the silicon nitride film 12, and the silicon oxide film 6 are sequentially removed by etching, the high-concentration base diffusion layer 16 and the high-concentration base diffusion layer 16 are formed by the same process as the conventional example shown in FIG. Each of the active base diffusion layer 17 and the emitter diffusion layer 20 is formed to form a semiconductor integrated circuit.
【００１９】このように実施例においては、窒化シリコ
ン膜１２上を薄い酸化シリコン膜１３により被覆保護し
た状態でコレクタ引出領域形成用のＮ型高濃度不純物を
拡散することにより、従来製法のようにＮ型高濃度拡散
層の周囲に生ずる結晶欠陥の発生を抑えて半導体チップ
の良品率を向上させることを可能とする。As described above, in the embodiment, the N-type high-concentration impurity for forming the collector extraction region is diffused in the state where the silicon nitride film 12 is covered and protected by the thin silicon oxide film 13, and thus the conventional manufacturing method is performed. It is possible to suppress the occurrence of crystal defects around the N-type high-concentration diffusion layer and improve the yield rate of semiconductor chips.
【００２０】[0020]
【発明の効果】以上に説明したように本発明は、窒化シ
リコン膜の表面を薄い酸化シリコン膜により被覆保護し
た状態でＮ型不純物の高濃度拡散を行うことにより、Ｎ
型高濃度拡散層の周囲の結晶欠陥の発生を抑えて半導体
装置の低電圧リーク不良，耐圧劣化，高周波特性の変動
等を低減し、信頼性を向上できるという効果を有する。As described above, according to the present invention, the N-type impurity is diffused at a high concentration while the surface of the silicon nitride film is covered and protected by the thin silicon oxide film.
This has the effect of suppressing the occurrence of crystal defects around the high-concentration type diffusion layer, reducing low-voltage leak defects, breakdown voltage deterioration, fluctuations in high-frequency characteristics, etc. of the semiconductor device, and improving reliability.
【図１】本発明の一実施例を説明するための工程順に示
した半導体チップの断面図。1A to 1D are cross-sectional views of a semiconductor chip, which are shown in the order of steps for explaining an embodiment of the present invention.
【図２】従来の半導体装置の製造方法を説明するための
工程順に示した半導体チップの断面図。2A to 2D are cross-sectional views of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.
【図３】従来の半導体装置の製造方法を説明するための
工程順に示した半導体チップの断面図。FIG. 3 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.
１ Ｐ型シリコン基板 ２ 埋込層 ３ エピタキシャル層 ４，６，８，９，１１，１３，１５ 酸化シリコン膜 ５，２４ Ｐ+ 型拡散層 ７，１０，１２，１８ 窒化シリコン膜 １４ コレクタ引出領域 １６ 高濃度ベース拡散層 １７ 活性ベース拡散層 １９ ポリシリコン層 ２０ エミッタ拡散層 ２１ エミッタ電極 ２２ ベース電極 ２３ コレクタ電極1 P-type silicon substrate 2 Buried layer 3 Epitaxial layer 4, 6, 8, 9, 11, 13, 13 15 Silicon oxide film 5,24 P + type diffusion layer 7, 10, 12, 18 Silicon nitride film 14 Collector extraction region 16 High-concentration base diffusion layer 17 Active base diffusion layer 19 Polysilicon layer 20 Emitter diffusion layer 21 Emitter electrode 22 Base electrode 23 Collector electrode
Claims (1)
埋込層を設け前記埋込層を含む表面に逆導電型エピタキ
シャル層を設ける工程と、前記エピタキシャル層を選択
的に熱酸化して前記半導体基板に達する厚い酸化膜を形
成して素子形成領域を区画する工程と、前記素子形成領
域の表面を熱酸化して設けた酸化膜の上に窒化シリコン
膜と酸化シリコン膜を順次積層して設ける工程と、前記
素子形成領域上の前記酸化シリコン膜及び窒化シリコン
膜並びに酸化膜を順次エッチングして開孔部を設ける工
程と前記酸化シリコン膜及び窒化シリコン膜をマスクと
して前記開孔部の素子形成領域に逆導電型不純物を導入
して前記埋込層に達する逆導電型拡散層を形成する工程
とを含むことを特徴とする半導体装置の製造方法。Claim: What is claimed is: 1. A step of providing a reverse conductivity type buried layer on one main surface of a single conductivity type semiconductor substrate, and providing a reverse conductivity type epitaxial layer on a surface including the buried layer, and the epitaxial layer. And selectively forming a thick oxide film reaching the semiconductor substrate to partition the element formation region, and thermally oxidizing the surface of the element formation region to form a silicon nitride film on the oxide film. And a silicon oxide film are sequentially stacked, and the silicon oxide film and the silicon nitride film on the element formation region are sequentially etched to form an opening, and the silicon oxide film and the silicon nitride film are formed. Is used as a mask to form a reverse-conductivity-type diffusion layer that reaches the buried layer by introducing a reverse-conductivity-type impurity into the element formation region of the opening, and manufacturing the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11204291A JP2633411B2 (en) | 1991-05-17 | 1991-05-17 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11204291A JP2633411B2 (en) | 1991-05-17 | 1991-05-17 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH053199A true JPH053199A (en) | 1993-01-08 |
| JP2633411B2 JP2633411B2 (en) | 1997-07-23 |
Family
ID=14576564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11204291A Expired - Fee Related JP2633411B2 (en) | 1991-05-17 | 1991-05-17 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2633411B2 (en) |
-
1991
- 1991-05-17 JP JP11204291A patent/JP2633411B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2633411B2 (en) | 1997-07-23 |
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