JPH05315543A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH05315543A JPH05315543A JP4115558A JP11555892A JPH05315543A JP H05315543 A JPH05315543 A JP H05315543A JP 4115558 A JP4115558 A JP 4115558A JP 11555892 A JP11555892 A JP 11555892A JP H05315543 A JPH05315543 A JP H05315543A
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- Prior art keywords
- polysilicon
- oxide film
- film
- silicon
- amorphous silicon
- Prior art date
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- Semiconductor Integrated Circuits (AREA)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
スタックトキャパシタ（積層型容量素子）構造の１トラ
ンジスタメモリセルからなるＤＲＡＭ（ｄｙｎａｍｉｃ
ｒａｎｄｏｍ ａｃｃｅｓｓ ｍｅｍｏｒｙ）に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a DRAM (dynamic) consisting of a one-transistor memory cell having a stacked capacitor structure.
Random access memory).
【０００２】[0002]
【従来の技術】半導体メモリは、ビット当たりの製造単
価低減あるいは、メモリアクセス時間短縮のため、メモ
リセル面積の縮小による高集積化が図られてきた。2. Description of the Related Art Semiconductor memories have been highly integrated by reducing the memory cell area in order to reduce the manufacturing cost per bit or to shorten the memory access time.
【０００３】現在、０．８μｍ幅の最小設計ルールを用
いた４ＭｂＤＲＡＭあるいは１ＭｂＳＲＡＭが製品化さ
れている。さらに、０．６μｍ幅の最小設計ルールを用
いた１６ＭｂＤＲＡＭあるいは４ＭｂＳＲＡＭが開発さ
れている。At present, a 4 Mb DRAM or a 1 Mb SRAM using a minimum design rule of 0.8 μm width has been commercialized. Furthermore, 16 Mb DRAM or 4 Mb SRAM using the minimum design rule of 0.6 μm width has been developed.
【０００４】メモリセル面積の縮小によって、メモリセ
ルに蓄積できる電荷容量が低下する。ＤＲＡＭの高集積
化が進むにつれて、キャパシタ容量の確保が難しくなっ
てきている。小さいセル面積でも十分な電荷蓄積量を得
るために開発された、溝掘り（トレンチ）型または積層
（スタック）型が実用化されている。The reduction in memory cell area reduces the charge capacity that can be stored in the memory cell. As the DRAM is highly integrated, it is becoming difficult to secure the capacitance of the capacitor. A trench type or a stack type, which has been developed to obtain a sufficient charge storage amount even in a small cell area, has been put into practical use.
【０００５】特に積層型セルは、ソフトエラー耐性が高
く、トレンチ形成と違ってシリコン基板結晶に対して損
傷を与えない。蓄積電極の形状を工夫すれば実効セル面
積を増加できるなどの優れた特長があるので、次世代メ
モリセル構造として注目されている。In particular, the laminated cell has high soft error resistance and does not damage the silicon substrate crystal unlike the trench formation. It has attracted attention as a next-generation memory cell structure because it has the outstanding features that the effective cell area can be increased by devising the shape of the storage electrode.
【０００６】６４Ｍｂ以上のＤＲＡＭ用高密度メモリセ
ルとして、ＨＳＧ−Ｓｉ（ｈｅｍｉｓｐｈｅｒｉｃａｌ
−ｇｒａｉｎ−ｓｉｌｉｃｏｎ）蓄積電極が笠井直紀、
坂尾眞人、石嶋俊之、井川英治、渡辺啓二、寺田和夫、
吉川公麿によって「ＨＳＧポリシリコン蓄積電極を用い
た６４ＭｂＤＲＡＭ用メモリセル」、電子情報通信学会
技術研究報告ＳＤＭ９０−２０２、ｐｐ．４７−５２に
提案されている。これは表面に微細な凹凸を形成したポ
リシリコンを蓄積電極として、実効的な電極表面積を増
加して蓄積容量を大きくする方法である。As a high density memory cell for DRAM of 64 Mb or more, HSG-Si (hemipherical)
-Grain-silicon) storage electrode is Naoki Kasai,
Masato Sakao, Toshiyuki Ishishima, Eiji Ikawa, Keiji Watanabe, Kazuo Terada,
Kimio Yoshikawa, "Memory Cell for 64 Mb DRAM Using HSG Polysilicon Storage Electrode", IEICE Technical Report SDM90-202, pp. 47-52. This is a method of increasing the storage capacitance by increasing the effective electrode surface area by using polysilicon having fine irregularities formed on the surface as a storage electrode.
【０００７】このＨＳＧポリシリコン蓄積電極の形成方
法について、図６（ａ）〜（ｃ）を参照して説明する。A method of forming this HSG polysilicon storage electrode will be described with reference to FIGS. 6 (a) to 6 (c).
【０００８】はじめに図６（ａ）に示すように、Ｐ型シ
リコン基板１上にＬＯＣＯＳ（選択酸化）法によりフィ
ールド酸化膜２を形成したのち、ゲート酸化膜３、ゲー
ト電極４、ソース５ａおよびドレイン５ｂを形成してＭ
ＯＳＦＥＴを形成する。First, as shown in FIG. 6A, a field oxide film 2 is formed on a P-type silicon substrate 1 by a LOCOS (selective oxidation) method, and then a gate oxide film 3, a gate electrode 4, a source 5a and a drain are formed. 5b to form M
Form OSFET.
【０００９】つぎにＣＶＤ（化学気相成長）法により層
間絶縁膜６を堆積したのち、コンタクトホールを開口す
る。つぎにＬＰＣＶＤ法により６００℃でポリシリコン
を堆積したのち、レジスト（図示せず）をマスクとして
ドライエッチングして、蓄積電極７を形成する。Next, after depositing an interlayer insulating film 6 by a CVD (chemical vapor deposition) method, a contact hole is opened. Next, after depositing polysilicon at 600 ° C. by the LPCVD method, dry etching is performed using a resist (not shown) as a mask to form the storage electrode 7.
【００１０】つぎに図６（ｂ）に示すように、ＨＳＧポ
リシリコンからなるＨＳＧ−Ｓｉ膜８ａを形成する。隣
接する蓄積電極の電極間隔をレジストパターンで実現可
能な最小幅よりも狭めるとともに、凹凸によって表面積
を拡大することができる。Next, as shown in FIG. 6B, an HSG-Si film 8a made of HSG polysilicon is formed. It is possible to narrow the electrode interval between the adjacent storage electrodes to be smaller than the minimum width that can be realized by the resist pattern and to increase the surface area by the unevenness.
【００１１】このＨＳＧ−Ｓｉ膜８ａはつぎのようにし
て形成する。はじめに反応ガスとして流量２００ｓｃｃ
ｍのＳｉＨ4 を用いたＬＰＣＶＤ法により基板温度５５
０℃、圧力１Ｔｏｒｒにおいて３０分間で、厚さ１５０
ｎｍのアモルファスシリコンを堆積する。つぎに基板温
度を５５０℃に保って、反応ガス供給を止め、窒素雰囲
気で３０分間アニールして多結晶となったＨＳＧ−Ｓｉ
膜８ａが形成される。The HSG-Si film 8a is formed as follows. First, the reaction gas flow rate is 200 scc
substrate temperature 55 by the LPCVD method using m SiH 4
30 minutes at 0 ° C. and 1 Torr pressure, thickness 150
nm amorphous silicon is deposited. Next, the substrate temperature was kept at 550 ° C., the supply of the reaction gas was stopped, and annealing was performed for 30 minutes in a nitrogen atmosphere to make HSG-Si polycrystalline.
The film 8a is formed.
【００１２】さらに図６（ｃ）に示すように、ＲＩＥ法
によってエッチバックすることにより、ＨＳＧ−Ｓｉ膜
８ａからなる各蓄積電極７間を分離する。Further, as shown in FIG. 6C, the storage electrodes 7 made of the HSG-Si film 8a are separated from each other by etching back by the RIE method.
【００１３】[0013]
【発明が解決しようとする課題】ＨＳＧ−Ｓｉ蓄積電極
は、その電極表面に凹凸を形成して、実効的な電極表面
積を増加した積層（スタック）型蓄積電極である。The HSG-Si storage electrode is a stack type storage electrode in which the surface of the electrode is made uneven to increase the effective electrode surface area.
【００１４】従来の蓄積電極形成方法では、ＨＳＧ−Ｓ
ｉ膜を成長したのち、各蓄積電極間を分離するためＨＳ
Ｇ−Ｓｉ膜をエッチバックする必要がある。このエッチ
バックによって、ＨＳＧ−Ｓｉ蓄積電極の表面形状が変
化する。In the conventional storage electrode forming method, the HSG-S is used.
After growing the i-film, HS is used to separate each storage electrode.
It is necessary to etch back the G-Si film. This etchback changes the surface shape of the HSG-Si storage electrode.
【００１５】蓄積電極表面のうち、上面および側壁上部
は、エッチバック前の形状がエッチングのあと転写され
て凹凸形状が残っている。しかし、側壁下部はエッチン
グによって凹凸形状が消滅して、蓄積電極の表面積が減
少する。Of the surface of the storage electrode, the upper surface and the upper portion of the side wall are transferred with the shape before etching back after etching, and the uneven shape remains. However, the lower surface of the side wall is etched to eliminate the uneven shape, and the surface area of the storage electrode is reduced.
【００１６】このように、従来方法では蓄積電極側壁の
凹凸形状が消滅して、ＨＳＧ−Ｓｉ蓄積電極の総表面積
が減少し、メモリセルの蓄積電荷容量が減少するという
欠点があった。As described above, the conventional method has a drawback in that the concavo-convex shape of the side wall of the storage electrode disappears, the total surface area of the HSG-Si storage electrode decreases, and the stored charge capacity of the memory cell decreases.
【００１７】[0017]
【課題を解決するための手段】本発明の半導体装置は、
半導体基板の一主面にＭＯＳＦＥＴのドレインに接続す
る第１のポリシリコンが形成され、前記第１のポリシリ
コンの表面を覆って厚さ２ｎｍ以下の酸化シリコン膜が
形成され、前記酸化シリコン膜上に成長した半径１０〜
１００ｎｍの半球面シリコン粒で覆われた第２のポリシ
リコンが形成されたものである。The semiconductor device of the present invention comprises:
First polysilicon that is connected to the drain of the MOSFET is formed on one main surface of the semiconductor substrate, and a silicon oxide film having a thickness of 2 nm or less is formed so as to cover the surface of the first polysilicon. Radius grown to 10
Second polysilicon covered with 100 nm hemispherical silicon grains is formed.
【００１８】また本発明の半導体装置の製造方法は、Ｍ
ＯＳＦＥＴが形成された半導体基板の一主面上に、ＣＶ
Ｄ法によりアモルファスシリコンを堆積する工程と、前
記アモルファスシリコンを選択エッチングしてパターニ
ングする工程と、５００〜６００℃で弗化水素処理した
のち、酸素分圧１×１０-4Ｔｏｒｒ以下でアニール処理
して前記アモルファスシリコンをポリシリコンに結晶化
する工程とを含むものである。The method of manufacturing a semiconductor device according to the present invention is
CV is formed on one main surface of the semiconductor substrate on which the OSFET is formed.
A step of depositing amorphous silicon by the D method, a step of patterning the amorphous silicon by selective etching, a hydrogen fluoride treatment at 500 to 600 ° C., and an annealing treatment at an oxygen partial pressure of 1 × 10 −4 Torr or less. And crystallizing the amorphous silicon into polysilicon.
【００１９】[0019]
【実施例】本発明の第１の実施例について、図１（ａ）
〜（ｃ）を参照して説明する。EXAMPLE FIG. 1A shows a first example of the present invention.
This will be described with reference to (c).
【００２０】はじめに図１（ａ）に示すように、面方位
（１００）、抵抗率１０Ω−ｃｍのＰ型シリコン基板１
上に、ＬＯＣＯＳ法によりフィールド酸化膜２を形成す
る。つぎに、ゲート酸化膜３およびゲート電極４を形成
したのち、ソース５ａおよびドレイン５ｂを拡散して、
スィッチングトランジスタの素子部を形成する。First, as shown in FIG. 1A, a P-type silicon substrate 1 having a plane orientation (100) and a resistivity of 10 Ω-cm.
A field oxide film 2 is formed thereon by the LOCOS method. Next, after forming the gate oxide film 3 and the gate electrode 4, the source 5a and the drain 5b are diffused,
The element portion of the switching transistor is formed.
【００２１】つぎに、ＣＶＤ法により酸化膜を堆積した
のち、ドレイン５ｂに接続するコンタクトホールを開口
して層間絶縁膜６を形成する。つぎにＬＰＣＶＤ法によ
りポリシリコンを堆積したのち、レジスト（図示せず）
をマスクとしてエッチングすることにより、蓄積電極７
を形成する。このとき形成された蓄積電極７は、高さが
０．３μｍ、電極間距離が０．４μｍである。Next, after depositing an oxide film by the CVD method, a contact hole connecting to the drain 5b is opened to form an interlayer insulating film 6. Next, after depositing polysilicon by the LPCVD method, a resist (not shown)
Is used as a mask to etch the storage electrode 7
To form. The storage electrode 7 formed at this time has a height of 0.3 μm and an inter-electrode distance of 0.4 μm.
【００２２】ここまでは、図６（ａ）に示す従来方法と
同じである。Up to this point, the method is the same as the conventional method shown in FIG.
【００２３】つぎにＬＰＣＶＤ装置を用いて、基板温度
５１０℃、圧力１０Ｔｏｒｒ、Ｓｉ2 Ｈ6 流量２００ｓ
ｃｃｍ、Ｎ2 流量５ｓｌｍ（５０００ｓｃｃｍ）の条件
で、全面に厚さ０．１μｍのノンドープのアモルファス
シリコン８を成長した。このとき、圧力を高くしてステ
ップカバレッジ（段差被覆性）を悪化させ、蓄積電極７
上の膜厚を層間絶縁膜６上の膜厚よりも厚くする必要が
ある。Next, using an LPCVD apparatus, the substrate temperature was 510 ° C., the pressure was 10 Torr, and the Si 2 H 6 flow rate was 200 s.
Under conditions of ccm and N 2 flow rate of 5 slm (5000 sccm), non-doped amorphous silicon 8 having a thickness of 0.1 μm was grown on the entire surface. At this time, the pressure is increased to deteriorate the step coverage (step coverage), and the storage electrode 7
It is necessary to make the upper film thickness thicker than the film thickness on the interlayer insulating film 6.
【００２４】つぎに図１（ｂ）に示すように、ＲＩＥ法
によってアモルファスシリコン８のエッチバックを行な
って各蓄積電極７間を分離する。Next, as shown in FIG. 1B, the amorphous silicon 8 is etched back by the RIE method to separate the respective storage electrodes 7.
【００２５】つぎに図１（ｃ）に示すように、弗化水素
処理を行なったのち、窒素雰囲気でアニールしてＨＳＧ
−Ｓｉ膜８ａを形成する。Next, as shown in FIG. 1 (c), after hydrogen fluoride treatment, annealing is performed in a nitrogen atmosphere to perform HSG.
-Si film 8a is formed.
【００２６】このとき図２に示す装置を用いる。これは
抵抗加熱方式の縦型ＬＰＣＶＤ炉をアニール室１２と
し、高純度窒素ガスでパージしたロードロック室１３に
よって、弗化水素処理室１１と連結したものである。ロ
ードロック室１３の酸素分圧は、１×１０-6Ｔｏｒｒ以
下とし、アニール処理室の到達真空度は、１×１０-8Ｔ
ｏｒｒとする。さらに図３に示すように、高純度窒素パ
ージ室の代りに真空ポンプ１５を用いた真空排気式ロー
ドロック室１３を設けることもできる。At this time, the apparatus shown in FIG. 2 is used. The resistance heating type vertical LPCVD furnace is used as an annealing chamber 12 and is connected to a hydrogen fluoride treatment chamber 11 by a load lock chamber 13 purged with high-purity nitrogen gas. The oxygen partial pressure in the load lock chamber 13 is 1 × 10 −6 Torr or less, and the ultimate vacuum in the annealing chamber is 1 × 10 −8 T.
orr. Further, as shown in FIG. 3, a vacuum exhaust type load lock chamber 13 using a vacuum pump 15 may be provided instead of the high purity nitrogen purge chamber.
【００２７】つぎにＨＳＧ−Ｓｉ膜の形成方法について
図３および図４を参照して説明する。はじめに、弗化水
素処理室１１でアモルファスシリコンのエッチバックが
完了したウェーハ１５に弗化水素処理を行なって、アモ
ルファスシリコン表面の自然酸化膜を除去する。つぎ
に、ウエーハ１５を高純度窒素雰囲気のロードロック室
１３を介して、５５０℃に保ったアニール室１２に移動
させた。アニール室１２を排気して真空度１×１０-8Ｔ
ｏｒｒに５分間保ったのち、窒素流量を２０ｓｌｍと
し、真空度１Ｔｏｒｒ、温度５５０℃で３０分間アニー
ルすることにより、ＨＳＧ−Ｓｉ膜を形成することがで
きる。Next, a method of forming the HSG-Si film will be described with reference to FIGS. 3 and 4. First, the wafer 15 whose amorphous silicon has been etched back is subjected to hydrogen fluoride treatment in the hydrogen fluoride treatment chamber 11 to remove the native oxide film on the surface of the amorphous silicon. Next, the wafer 15 was moved to the annealing chamber 12 kept at 550 ° C. via the load lock chamber 13 in the high-purity nitrogen atmosphere. The annealing chamber 12 is evacuated to a vacuum degree of 1 × 10 -8 T
After being kept at orrr for 5 minutes, the flow rate of nitrogen is set to 20 slm and annealing is performed at a vacuum degree of 1 Torr and a temperature of 550 ° C. for 30 minutes to form an HSG-Si film.
【００２８】従来の蓄積電極においては、電極側壁下部
の凹凸が消滅しているのに対し、本実施例では、蓄積電
極の全面にわたって凹凸が形成されている。In the conventional storage electrode, the unevenness on the lower part of the electrode side wall is eliminated, whereas in this embodiment, the unevenness is formed over the entire surface of the storage electrode.
【００２９】蓄積電極の凹凸半径は５０ｎｍ、最終電極
寸法は高さ０．４μｍ×幅０．７μｍ×奥行き０．７μ
ｍで、電極間距離は０．１μｍとなった。一方、従来法
においては、蓄積電極側壁の高さ０．３μｍまでの領域
で凹凸が消滅していた。The concavo-convex radius of the storage electrode is 50 nm, and the final electrode dimensions are 0.4 μm in height × 0.7 μm in width × 0.7 μm in depth.
In m, the distance between the electrodes was 0.1 μm. On the other hand, in the conventional method, the unevenness disappeared in the region up to the height of the sidewall of the storage electrode of 0.3 μm.
【００３０】つぎに本発明の第２の実施例について説明
する。Next, a second embodiment of the present invention will be described.
【００３１】第２の実施例では、Ｐ（燐）をドープしな
がらアモルファスシリコンを成長した。In the second embodiment, amorphous silicon was grown while doping P (phosphorus).
【００３２】第１の実施例と同様に図１（ａ）に示すよ
うに、Ｐ型シリコン基板１上にスィッチングトランジス
タを形成したのち、ＣＶＤ法により層間絶縁膜を堆積し
てコンタクトホールを開口する。つぎにポリシリコンの
堆積したのちレジスト（図示せず）をマスクとしてエッ
チングして、蓄積電極７を形成する。Similar to the first embodiment, as shown in FIG. 1A, after forming a switching transistor on the P type silicon substrate 1, an interlayer insulating film is deposited by the CVD method to open a contact hole. .. Next, after depositing polysilicon, etching is performed using a resist (not shown) as a mask to form a storage electrode 7.
【００３３】つぎにＬＰＣＶＤ装置を用いて、基板温度
５１０℃、圧力０．１Ｔｏｒｒ、Ｓｉ2 Ｈ6 流量２００
ｓｃｃｍ、４％ＰＨ3 流量１００ｓｃｃｍの条件で３５
分経ったら、ＰＨ3 を止めて５分経過してＰドープアモ
ルファスシリコン８を堆積した。Next, using an LPCVD apparatus, the substrate temperature was 510 ° C., the pressure was 0.1 Torr, and the Si 2 H 6 flow rate was 200.
sccm, 4% PH 3 flow rate 100 sccm 35
After a lapse of minutes, PH 3 was stopped and after 5 minutes, P-doped amorphous silicon 8 was deposited.
【００３４】燐をドープしたので、圧力を高くしなくて
もステップカバレッジを悪化させることができる。Since phosphorus is doped, step coverage can be deteriorated without increasing the pressure.
【００３５】あとの５分間をノンドープ成長としたの
は、アモルファスシリコン膜８の表面Ｐ濃度を減少させ
て、あとで表面に形成される誘電率の小さい自然酸化膜
を薄くするためである。The non-doping growth for the remaining 5 minutes is to reduce the surface P concentration of the amorphous silicon film 8 and thin the natural oxide film formed later on the surface having a small dielectric constant.
【００３６】また、高濃度Ｐドープシリコン膜はステッ
プカバレージが悪いので、蓄積電極７上の膜厚はフィー
ルド酸化２上の膜厚よりも厚くなる。堆積したアモルフ
ァスシリコン８の膜厚は、第１の実施例と同じ０．１μ
ｍとなった。Since the high-concentration P-doped silicon film has poor step coverage, the film thickness on the storage electrode 7 is larger than that on the field oxide 2. The thickness of the deposited amorphous silicon 8 is 0.1 μm, which is the same as that in the first embodiment.
It became m.
【００３７】つぎに図１（ｂ）に示すように、ＲＩＥ法
によりアモルファスシリコン８をエッチバックして各蓄
積電極７間を分離する。Next, as shown in FIG. 1B, the amorphous silicon 8 is etched back by the RIE method to separate the respective storage electrodes 7.
【００３８】つぎに図１（ｃ）に示すように、第１の実
施例と同様にしてＨＳＧ−Ｓｉ膜８ａを形成した。本実
施例のアモルファスシリコン８はＰドープされているの
で、結晶化の核発生が早く、１０分間のアニールでＨＳ
Ｇ−Ｓｉ膜８ａを形成することができた。Next, as shown in FIG. 1C, an HSG-Si film 8a was formed in the same manner as in the first embodiment. Since the amorphous silicon 8 of the present embodiment is P-doped, nucleation of crystallization is fast, and HS is obtained by annealing for 10 minutes.
The G-Si film 8a could be formed.
【００３９】本実施例でも第１の実施例と同様に、蓄積
電極７の全表面に凹凸が形成された。Ｐドープアモルフ
ァスシリコンをアニールしても、ＨＳＧ−Ｓｉ蓄積電極
が得られることが確認された。本実施例の場合、ＨＳＧ
−Ｓｉ形成前に蓄積電極全体がＰドープされているの
で、あとの工程で不純物を拡散する必要がないという長
所がある。In this embodiment as well, as in the first embodiment, unevenness was formed on the entire surface of the storage electrode 7. It was confirmed that the HSG-Si storage electrode can be obtained even if the P-doped amorphous silicon is annealed. In the case of this embodiment, HSG
Since the entire storage electrode is P-doped before the formation of —Si, there is an advantage that it is not necessary to diffuse impurities in a later step.
【００４０】つぎに本発明の第３の実施例について、図
４（ａ）〜（ｃ）を参照して説明する。Next, a third embodiment of the present invention will be described with reference to FIGS.
【００４１】はじめに図４（ａ）に示すように、スィッ
チングトランジスタが形成されたＰ型シリコン基板１に
層間絶縁膜６のコンタクトホールを通してドレイン５ｂ
に接続する蓄積電極７を形成する。First, as shown in FIG. 4A, the drain 5b is passed through the contact hole of the interlayer insulating film 6 in the P-type silicon substrate 1 on which the switching transistor is formed.
Forming a storage electrode 7 connected to.
【００４２】つぎに図４（ｂ）に示すように、ＣＶＤ炉
を用いて８００℃でアルゴンをキャリアガスとして１０
０ｐｐｍに希釈した酸素で１０分間処理して、蓄積電極
７上に厚さ１ｎｍの酸化シリコン膜９を成長させる。Next, as shown in FIG. 4 (b), argon was used as a carrier gas at 10 ° C. in a CVD furnace at 10 ° C.
By treating with oxygen diluted to 0 ppm for 10 minutes, a silicon oxide film 9 having a thickness of 1 nm is grown on the storage electrode 7.
【００４３】つぎに図４（ｃ）に示すように、引き続い
て８００℃に保ったままジクロロシラン、塩化水素、水
素を導入して半径１００ｎｍの半球状の表面をもつ厚さ
２００ｎｍの選択凹凸シリコン膜１０を成長させる。酸
化シリコン膜９上にのみ選択成長させることができる。Next, as shown in FIG. 4 (c), while keeping the temperature at 800 ° C., dichlorosilane, hydrogen chloride, and hydrogen were introduced, and the selective uneven silicon having a thickness of 200 nm and having a hemispherical surface with a radius of 100 nm. The film 10 is grown. The selective growth can be performed only on the silicon oxide film 9.
【００４４】厚さ２ｎｍ以下の酸化シリコン膜の上から
選択シリコン成長を行なうと、酸化シリコン膜上にはシ
リコンは成長しない。酸化シリコン膜の裂け目を核とし
てポリシリコンが成長するので、半球状のシリコンが成
長する。When selective silicon growth is performed on a silicon oxide film having a thickness of 2 nm or less, silicon does not grow on the silicon oxide film. Since polysilicon grows with the crevice of the silicon oxide film as a nucleus, hemispherical silicon grows.
【００４５】この選択凹凸シリコン膜１０の表面が電荷
蓄積領域となる。選択成長であるので、蓄積電極の側面
も含めて全面に凹凸が残っている。隣接する蓄積電極７
の最小間隔をＬとして、選択凹凸シリコン膜１０の膜厚
はＬ／２未満とする。The surface of the selected uneven silicon film 10 serves as a charge storage region. Since the growth is selective, unevenness remains on the entire surface including the side surface of the storage electrode. Adjacent storage electrode 7
The minimum interval is defined as L, and the film thickness of the selected uneven silicon film 10 is set to less than L / 2.
【００４６】つぎに本発明の第４の実施例について、図
５（ａ）〜（ｂ）を参照して説明する。Next, a fourth embodiment of the present invention will be described with reference to FIGS.
【００４７】はじめに図５（ａ）に示すように、スィッ
チングトランジスタが形成されたＰ型シリコン基板１に
層間絶縁膜６を形成したのち蓄積電極７を形成する。First, as shown in FIG. 5A, an interlayer insulating film 6 is formed on a P-type silicon substrate 1 on which switching transistors are formed, and then a storage electrode 7 is formed.
【００４８】つぎにＣＶＤ炉を用いて８００℃で窒素を
キャリアガスとして１００ｐｐｍに希釈した水蒸気で５
分間処理して、蓄積電極７上に厚さ１ｎｍの酸化シリコ
ン膜９を成長させる。Next, using a CVD furnace, at 5 ° C. with water vapor diluted to 100 ppm with nitrogen as a carrier gas at 800 ° C.
After processing for a minute, a silicon oxide film 9 having a thickness of 1 nm is grown on the storage electrode 7.
【００４９】つぎに反応ガスの圧力を高くした若干選択
性の悪い条件で選択凹凸シリコン膜１０を成長させる。Next, the selectively uneven silicon film 10 is grown under the condition that the pressure of the reaction gas is increased and the selectivity is slightly poor.
【００５０】つぎに図５（ｂ）に示すように、酸化シリ
コン膜９以外の層間絶縁膜６上に成長したポリシリコン
（選択凹凸シリコン膜１０）をエッチングする。選択成
長を用いているので、層間絶縁膜６上に堆積する選択凹
凸シリコン膜１０は極く薄く、エッチング時間は短い。Next, as shown in FIG. 5B, the polysilicon (selected uneven silicon film 10) grown on the interlayer insulating film 6 other than the silicon oxide film 9 is etched. Since the selective growth is used, the selectively uneven silicon film 10 deposited on the interlayer insulating film 6 is extremely thin and the etching time is short.
【００５１】本実施例ではエッチング工程を追加してい
るので、汚れなどで選択性が失なわれた基板に対しても
適用することができる。選択凹凸シリコン膜の成長が確
実にできて、プロセスが安定している。Since an etching step is added in the present embodiment, it can be applied to a substrate whose selectivity is lost due to dirt or the like. The selective concavo-convex silicon film can be reliably grown, and the process is stable.
【００５２】[0052]
【発明の効果】ＣＶＤ法によりアモルファスシリコンを
堆積したのち、エッチバックして隣接蓄積電極間を分離
する。そのあと酸素分圧１×１０-4Ｔｏｒｒ以下で弗化
水素処理およびアニールを行なって、ＨＳＧ−Ｓｉ蓄積
電極を形成する。あるいは、選択凹凸酸化シリコン膜を
成長する。EFFECTS OF THE INVENTION After depositing amorphous silicon by the CVD method, etching back is performed to separate adjacent storage electrodes. After that, hydrogen fluoride treatment and annealing are performed at an oxygen partial pressure of 1 × 10 −4 Torr or less to form an HSG-Si storage electrode. Alternatively, a selective uneven silicon oxide film is grown.
【００５３】その結果、蓄積電極の全面にわたって凹凸
を形成することができた。従来、蓄積電極の側壁下部の
凹凸形状が消滅していた場合と比較して、本発明では蓄
積電荷容量を３５〜５０％増加させることができた。As a result, unevenness could be formed over the entire surface of the storage electrode. According to the present invention, the accumulated charge capacity can be increased by 35 to 50% as compared with the case where the uneven shape on the lower portion of the side wall of the accumulation electrode has disappeared conventionally.
【００５４】メモリセル面積の縮小による高集積化によ
って、アスペクト比が大きくなるにつれて、いっそう蓄
積電容量を増加させる効果が著しくなる。As the aspect ratio becomes larger due to the higher integration due to the reduction of the memory cell area, the effect of further increasing the storage capacitance becomes more remarkable.
【図１】本発明の第１および第２の実施例を工程順に示
す断面図である。FIG. 1 is a cross-sectional view showing the first and second embodiments of the present invention in the order of steps.
【図２】本発明の第１および第２の実施例で用いた弗化
水素処理およびアニールのための装置を示す模式図であ
る。FIG. 2 is a schematic diagram showing an apparatus for hydrogen fluoride treatment and annealing used in the first and second embodiments of the present invention.
【図３】本発明の第１および第２の実施例で用いた弗化
水素処理およびアニールのための装置を示す模式図であ
る。FIG. 3 is a schematic view showing an apparatus for hydrogen fluoride treatment and annealing used in the first and second embodiments of the present invention.
【図４】本発明の第３の実施例を工程順に示す断面図で
ある。FIG. 4 is a cross-sectional view showing a third embodiment of the present invention in process order.
【図５】本発明の第４の実施例を工程順に示す断面図で
ある。FIG. 5 is a cross-sectional view showing a fourth embodiment of the present invention in process order.
【図６】従来のＨＳＧポリシリコン蓄積電極の形成方法
を示す断面図である。FIG. 6 is a cross-sectional view showing a method of forming a conventional HSG polysilicon storage electrode.
１ Ｐ型シリコン基板 ２ フィールド酸化膜 ３ ゲート酸化膜 ４ ゲート電極 ５ａ ソース ５ｂ ドレイン ６ 層間絶縁膜 ７ 蓄積電極 ８ アモルファスシリコン ８ａ ＨＳＧ−Ｓｉ膜 ９ 酸化シリコン膜 １０ 選択凹凸シリコン膜 １１ 弗化水素処理室 １２ アニール室 １３ ロードロック室 １４ ヒーター １５ 真空ポンプ １６ ウェーハローダ １７ ウェーハ 1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4 Gate electrode 5a Source 5b Drain 6 Interlayer insulating film 7 Storage electrode 8 Amorphous silicon 8a HSG-Si film 9 Silicon oxide film 10 Selective uneven silicon film 11 Hydrogen fluoride treatment chamber 12 Annealing chamber 13 Load lock chamber 14 Heater 15 Vacuum pump 16 Wafer loader 17 Wafer
Claims (5)
一主面上に、ＣＶＤ法によりアモルファスシリコンを堆
積する工程と、前記アモルファスシリコンを選択エッチ
ングしてパターニングする工程と、５００〜６００℃で
弗化水素処理したのち、酸素分圧１×１０-4Ｔｏｒｒ以
下でアニール処理して前記アモルファスシリコンをポリ
シリコンに結晶化する工程とを含む半導体装置の製造方
法。1. A step of depositing amorphous silicon by a CVD method on a main surface of a semiconductor substrate on which a MOSFET is formed, a step of selectively etching the amorphous silicon and patterning, and a fluorination at 500 to 600 ° C. A method of manufacturing a semiconductor device, which comprises a step of crystallizing the amorphous silicon into polysilicon by subjecting to hydrogen treatment and then annealing at an oxygen partial pressure of 1 × 10 −4 Torr or less.
リコンを堆積する請求項１記載の半導体装置の製造方
法。2. The method for manufacturing a semiconductor device according to claim 1, wherein phosphorus-doped amorphous silicon is deposited by a CVD method.
レインに接続する第１のポリシリコンが形成され、前記
第１のポリシリコンの表面を覆って厚さ２ｎｍ以下の酸
化シリコン膜が形成され、前記酸化シリコン膜上に成長
した半径１０〜１００ｎｍの半球面シリコン粒で覆われ
た第２のポリシリコンが形成された半導体装置。3. A first polysilicon connected to a drain of a MOSFET is formed on one main surface of a semiconductor substrate, and a silicon oxide film having a thickness of 2 nm or less is formed so as to cover the surface of the first polysilicon. A semiconductor device in which second polysilicon covered with hemispherical silicon grains having a radius of 10 to 100 nm grown on the silicon oxide film is formed.
一主面上に、ＣＶＤ法により第１のポリシリコンを堆積
したのち、選択エッチングしてパターニングする工程
と、ヘリウム、窒素、アルゴンのうち１つをキャリアガ
スとして希釈した、酸素および水蒸気のうちの１つの雰
囲気で熱処理して前記第１のポリシリコン表面に酸化シ
リコン膜を形成する工程と、ＣＶＤ法により前記酸化シ
リコン膜の表面に選択的に半球面シリコン粒で覆われた
第２のポリシリコンを成長する工程とを含む半導体装置
の製造方法。4. A step of depositing a first polysilicon by a CVD method on a main surface of a semiconductor substrate on which a MOSFET is formed and then patterning by selective etching, and one of helium, nitrogen and argon. Is used as a carrier gas and heat-treated in an atmosphere of one of oxygen and water vapor to form a silicon oxide film on the surface of the first polysilicon, and a step of selectively forming a silicon oxide film on the surface of the silicon oxide film by a CVD method. Growing a second polysilicon covered with hemispherical silicon grains.
記第２のポリシリコンをエッチバックする工程を含む請
求項４記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of etching back the second polysilicon after growing the second polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4115558A JPH05315543A (en) | 1992-05-08 | 1992-05-08 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4115558A JPH05315543A (en) | 1992-05-08 | 1992-05-08 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05315543A true JPH05315543A (en) | 1993-11-26 |
Family
ID=14665517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4115558A Withdrawn JPH05315543A (en) | 1992-05-08 | 1992-05-08 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05315543A (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5407534A (en) * | 1993-12-10 | 1995-04-18 | Micron Semiconductor, Inc. | Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal |
| US5656531A (en) * | 1993-12-10 | 1997-08-12 | Micron Technology, Inc. | Method to form hemi-spherical grain (HSG) silicon from amorphous silicon |
| JPH09307080A (en) * | 1996-05-02 | 1997-11-28 | Lg Semicon Co Ltd | Manufacture of capacitor of semiconductor element |
| US5753559A (en) * | 1996-01-16 | 1998-05-19 | United Microelectronics Corporation | Method for growing hemispherical grain silicon |
| NL1004811C2 (en) * | 1996-12-18 | 1998-06-19 | United Microelectronics Corp | Increasing capacitance of semiconductor device |
| FR2758008A1 (en) * | 1996-12-30 | 1998-07-03 | United Microelectronics Corp | Hemispherical grain silicon formation technique for ultra high density integrated circuits |
| KR100219482B1 (en) * | 1996-05-23 | 1999-09-01 | 윤종용 | Method for capacitor in semiconductor device |
| US5972771A (en) * | 1994-03-11 | 1999-10-26 | Micron Technology, Inc. | Enhancing semiconductor structure surface area using HSG and etching |
| KR100234383B1 (en) * | 1996-07-23 | 1999-12-15 | 윤종용 | Method of manufacturing a capacitor for a semiconductor device |
| US6020248A (en) * | 1997-06-26 | 2000-02-01 | Nec Corporation | Method for fabricating semiconductor device having capacitor increased in capacitance by using hemispherical grains without reduction of dopant concentration |
| US6046082A (en) * | 1997-06-05 | 2000-04-04 | Nec Corporation | Method for manufacturing semiconductor device |
| KR100268415B1 (en) * | 1997-10-01 | 2000-10-16 | 윤종용 | Capacitor Manufacturing Method of Semiconductor Memory Device |
| US6146966A (en) * | 1996-05-21 | 2000-11-14 | Nec Corporation | Process for forming a capacitor incorporated in a semiconductor device |
| KR100296966B1 (en) * | 1998-01-09 | 2001-10-25 | 로버트 에이치. 씨. 챠오 | Silicon manufacturing method of hemispherical particle structure |
| KR100400326B1 (en) * | 2001-12-29 | 2003-10-01 | 주식회사 하이닉스반도체 | Forming method of lower electrode of semiconductor device |
| US6930015B2 (en) | 1997-02-28 | 2005-08-16 | Micron Technology, Inc. | Diffusion-enhanced crystallization of amorphous materials to improve surface roughness |
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1992
- 1992-05-08 JP JP4115558A patent/JPH05315543A/en not_active Withdrawn
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5629223A (en) * | 1993-12-10 | 1997-05-13 | Micron Technology, Inc. | Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal |
| US5656531A (en) * | 1993-12-10 | 1997-08-12 | Micron Technology, Inc. | Method to form hemi-spherical grain (HSG) silicon from amorphous silicon |
| US5837580A (en) * | 1993-12-10 | 1998-11-17 | Micron Technology, Inc. | Method to form hemi-spherical grain (HSG) silicon |
| US5407534A (en) * | 1993-12-10 | 1995-04-18 | Micron Semiconductor, Inc. | Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal |
| US6667218B2 (en) | 1994-03-11 | 2003-12-23 | Micron Technology, Inc. | Enhancing semiconductor structure surface area using HSG and etching |
| US6291849B1 (en) | 1994-03-11 | 2001-09-18 | Micron Technology, Inc. | Semiconductor structures and apparatus having separated polysilicon grains |
| US5972771A (en) * | 1994-03-11 | 1999-10-26 | Micron Technology, Inc. | Enhancing semiconductor structure surface area using HSG and etching |
| US5753559A (en) * | 1996-01-16 | 1998-05-19 | United Microelectronics Corporation | Method for growing hemispherical grain silicon |
| JPH09307080A (en) * | 1996-05-02 | 1997-11-28 | Lg Semicon Co Ltd | Manufacture of capacitor of semiconductor element |
| US6146966A (en) * | 1996-05-21 | 2000-11-14 | Nec Corporation | Process for forming a capacitor incorporated in a semiconductor device |
| KR100219482B1 (en) * | 1996-05-23 | 1999-09-01 | 윤종용 | Method for capacitor in semiconductor device |
| KR100234383B1 (en) * | 1996-07-23 | 1999-12-15 | 윤종용 | Method of manufacturing a capacitor for a semiconductor device |
| NL1004811C2 (en) * | 1996-12-18 | 1998-06-19 | United Microelectronics Corp | Increasing capacitance of semiconductor device |
| FR2758008A1 (en) * | 1996-12-30 | 1998-07-03 | United Microelectronics Corp | Hemispherical grain silicon formation technique for ultra high density integrated circuits |
| US6930015B2 (en) | 1997-02-28 | 2005-08-16 | Micron Technology, Inc. | Diffusion-enhanced crystallization of amorphous materials to improve surface roughness |
| US7238613B2 (en) | 1997-02-28 | 2007-07-03 | Micron Technology, Inc. | Diffusion-enhanced crystallization of amorphous materials to improve surface roughness |
| US6046082A (en) * | 1997-06-05 | 2000-04-04 | Nec Corporation | Method for manufacturing semiconductor device |
| CN1101596C (en) * | 1997-06-05 | 2003-02-12 | 日本电气株式会社 | Method for manufacturing semiconductor device |
| US6020248A (en) * | 1997-06-26 | 2000-02-01 | Nec Corporation | Method for fabricating semiconductor device having capacitor increased in capacitance by using hemispherical grains without reduction of dopant concentration |
| KR100268415B1 (en) * | 1997-10-01 | 2000-10-16 | 윤종용 | Capacitor Manufacturing Method of Semiconductor Memory Device |
| KR100296966B1 (en) * | 1998-01-09 | 2001-10-25 | 로버트 에이치. 씨. 챠오 | Silicon manufacturing method of hemispherical particle structure |
| KR100400326B1 (en) * | 2001-12-29 | 2003-10-01 | 주식회사 하이닉스반도체 | Forming method of lower electrode of semiconductor device |
| US9111775B2 (en) | 2011-01-28 | 2015-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Silicon structure and manufacturing methods thereof and of capacitor including silicon structure |
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