JPH05299660A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05299660A JPH05299660A JP10108392A JP10108392A JPH05299660A JP H05299660 A JPH05299660 A JP H05299660A JP 10108392 A JP10108392 A JP 10108392A JP 10108392 A JP10108392 A JP 10108392A JP H05299660 A JPH05299660 A JP H05299660A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- passivation
- forming step
- ultraviolet rays
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＥＰＲＯＭの如き紫外
線消去式の不揮発性半導体素子を具備した半導体装置の
製造方法に関し、特に１回書き込み型のＯＴＰ（One Ti
me Programable）ＲＯＭの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having an ultraviolet erasable non-volatile semiconductor element such as an EPROM, and more particularly to a one-time write type OTP (One Ti
me Programmable) ROM manufacturing method.
【０００２】[0002]
【従来の技術】従来、紫外線消去式の不揮発性半導体素
子を具備した半導体装置、例えばＥＰＲＯＭの製造方法
は、シリコン基板上に第１ゲート酸化膜、第１ゲート多
結晶シリコン膜（フローテイングゲート）、第２ゲート
酸化膜、第２ゲート多結晶シリコン膜（コントロールゲ
ート）を順次形成した後、ソース・ドレインをＡｓ，
Ｐ，Ｂ等の不純物のイオン注入等によりゲート電極に対
しセルフアラインに形成して、ＥＰＲＯＭを形成する。
つづいてＣＶＤ法により層間絶縁膜となるＢＰＳＧ膜を
成長させた後、コンタクト穴を開口しアルミニウム等に
よる配線電極を形成している。2. Description of the Related Art Conventionally, a method of manufacturing a semiconductor device, such as an EPROM, equipped with an ultraviolet erasable non-volatile semiconductor element is known as a first gate oxide film and a first gate polycrystalline silicon film (floating gate) on a silicon substrate. , A second gate oxide film, and a second gate polycrystal silicon film (control gate) are sequentially formed, and then the source / drain is formed of As,
An EPROM is formed by self-aligning with the gate electrode by ion implantation of impurities such as P and B.
Subsequently, after growing a BPSG film as an interlayer insulating film by the CVD method, contact holes are opened and wiring electrodes made of aluminum or the like are formed.
【０００３】ＥＰＲＯＭは紫外線を照射することによ
り、その情報の消去が可能となることから、書き換え可
能型ＥＰＲＯＭではパッシベーション膜として紫外線の
透過が可能なＰＳＧ膜やＳｉＯ2 膜が使用されている。Since information can be erased from the EPROM by irradiating it with ultraviolet rays, the rewritable EPROM uses a PSG film or a SiO 2 film capable of transmitting ultraviolet rays as a passivation film.
【０００４】一方、例えばゲーム機用ソフトなど、書き
込みは１回であるがその種類が豊富であるなど、用途の
多様化にともなう少量他品種製品への生産対応というニ
ーズより、１回書き込み型のＯＴＰＲＯＭが注目されて
いる。その場合パッシベーション膜としてはパッシベー
ション効果に優れた窒化シリコン膜が用いられている。
ここでパッシベーション膜として用いられる窒化シリコ
ン膜は、プラズマＣＶＤ法により反応ガスをプラズマ化
して堆積させた膜（以下、これをＰ−ＳｉＮ膜と称す
る）が使用されているが、その光学吸収端波長は２５０
ｎｍ以上であり、紫外線を容易に透過させることができ
ない。そのためＰ−ＳｉＮ形成後ではＥＰＲＯＭに書き
込まれた情報の消去は困難であり、従って、パッシベー
ション膜としてＰ−ＳｉＮ膜を用いた場合には形成した
半導体素子の、特にＥＰＲＯＭに書き込まれた情報の記
憶保持特性等の電気特性の検査をＰ−ＳｉＮ膜の形成前
に行う必要がある。[0004] On the other hand, for example, game software is written once, but there are many types of writing. For example, one-writing type is required due to the need for production support for small-volume products of other types as the applications are diversified. OTPROM is receiving attention. In that case, a silicon nitride film having an excellent passivation effect is used as the passivation film.
As the silicon nitride film used as the passivation film, a film (hereinafter, referred to as a P-SiN film) formed by converting a reactive gas into plasma by a plasma CVD method is used, and its optical absorption edge wavelength is used. Is 250
Since it is not less than nm, ultraviolet rays cannot be easily transmitted. Therefore, it is difficult to erase the information written in the EPROM after the P-SiN is formed. Therefore, when the P-SiN film is used as the passivation film, the information stored in the formed semiconductor element, particularly the EPROM, is stored. It is necessary to inspect the electrical characteristics such as the holding characteristics before forming the P-SiN film.
【０００５】パッシベーション膜としてＰ−ＳｉＮ膜を
用いたＯＴＰＲＯＭの従来の製造方法について、図４
（ａ）〜（ｄ）を用いて説明する。上述のようにＥＰＲ
ＯＭ（図示せず）を形成したシリコン基板１に層間絶縁
膜としてＢＰＳＧ膜２を形成し、通常のホト・エッチン
グ工程（以下、ＰＥＰと称する）によりコンタクト穴を
開口する。そして、アルミニウム等の金属膜をスパタ法
を用いて被着し、ＰＥＰにてアルミニウムの配線電極３
および電極パッド４を形成する（図４（ａ））。A conventional manufacturing method of an OTPROM using a P-SiN film as a passivation film is shown in FIG.
A description will be given using (a) to (d). EPR as described above
A BPSG film 2 is formed as an interlayer insulating film on a silicon substrate 1 on which an OM (not shown) is formed, and contact holes are opened by a normal photo-etching process (hereinafter referred to as PEP). Then, a metal film of aluminum or the like is deposited by using a sputtering method, and the wiring electrode 3 of aluminum is formed by PEP.
And the electrode pad 4 is formed (FIG. 4A).
【０００６】そして、ＥＰＲＯＭの記憶保持特性等の検
査を行うため、配線電極３および電極パッド４が大気に
曝された状態で電極パッド４にタングステン等のプロー
ブ針５を接触させるプロービング工程を実施する（図４
（ｂ））。特にＥＰＲＯＭの記憶保持特性の検査では、
電気的に情報の書き込みを行ったＥＰＲＯＭを２００〜
２５０℃の高温にて数時間放置した後の情報の減少の度
合いを検査するため、再度プロービング工程が実施され
る。Then, in order to inspect the memory retention characteristics and the like of the EPROM, a probing step is carried out in which the probe needle 5 such as tungsten is brought into contact with the electrode pad 4 in a state where the wiring electrode 3 and the electrode pad 4 are exposed to the atmosphere. (Fig. 4
(B)). Especially in the inspection of memory retention characteristics of EPROM,
200 to 200 EPROMs with electrically written information
The probing process is performed again to inspect the degree of information loss after standing at a high temperature of 250 ° C. for several hours.
【０００７】そして、ＥＰＲＯＭ等の検査を終えたシリ
コン基板１に紫外線を約３０分照射して検査工程で書き
込まれた情報を消去し（図４（ｃ））、シリコン基板１
を流水洗浄後、パッシベーション膜として１．６μｍの
Ｐ−ＳｉＮ膜６を形成し、ＯＴＰＲＯＭを製造している
（図４（ｄ））。Then, the silicon substrate 1 after the inspection of the EPROM or the like is irradiated with ultraviolet rays for about 30 minutes to erase the information written in the inspection process (FIG. 4C).
After being washed with running water, a P-SiN film 6 having a thickness of 1.6 μm is formed as a passivation film to manufacture an OTPROM (FIG. 4 (d)).
【０００８】このようにして、パッシベーション膜とし
てＰ−ＳｉＮ膜を用いたＯＴＰＲＯＭにおいては、ＥＰ
ＲＯＭに書き込まれた情報の記憶保持特性等の電気特性
の検査をＰ−ＳｉＮ膜の形成前に行っている。Thus, in the OTPROM using the P-SiN film as the passivation film, the EP
The electrical characteristics such as the memory retention characteristics of the information written in the ROM are inspected before the P-SiN film is formed.
【０００９】[0009]
【従来技術の問題点】しかしながら、上記のようにして
製造される１回書き込み型ＥＰＲＯＭでは、その検査工
程において、電極パッド４にタングステン等のプローブ
針５が接触したとき電極パッド４の欠けやプローブ針５
の摩耗等の原因によって微小な導電性材料のかけら７
（以下、これをプロービング屑７と称する）が発生す
る。このプロービング屑７は半導体装置表面に付着し、
特に配線電極３間に付着したプロービング屑７はその後
の流水洗浄でも除去されず、配線間の短絡や素子の漏れ
電流を引き起こし、歩留りを低下させるという問題があ
った。However, in the write once type EPROM manufactured as described above, when the probe needle 5 made of tungsten or the like comes into contact with the electrode pad 4 in the inspection process, the chipping of the electrode pad 4 or the probe Needle 5
Minute pieces of conductive material due to wear on the surface 7
(Hereinafter, this is referred to as probing waste 7.) This probing waste 7 adheres to the surface of the semiconductor device,
In particular, the probing wastes 7 attached between the wiring electrodes 3 are not removed even by the subsequent washing with running water, which causes a short circuit between the wirings and a leakage current of the element, which causes a problem of reducing the yield.
【００１０】[0010]
【発明が解決しようとする課題】本発明はこうした状況
に鑑みてなされたものであって、その目的は、パッシベ
ーション膜形成工程に先だって検査工程を行う必要のあ
る例えば１回書き込み型ＥＰＲＯＭ等の半導体素子を具
備した半導体装置の製造において、検査工程でプロービ
ング屑が発生したとしても、配線間の短絡や素子の漏れ
電流を防止することができ、歩留りを向上させることの
できる製造方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of such a situation, and an object thereof is a semiconductor such as a one-time write EPROM which requires an inspection step prior to a passivation film formation step. To provide a manufacturing method capable of preventing a short circuit between wirings and a leakage current of an element even if a probing waste is generated in an inspection step in manufacturing a semiconductor device including an element, and improving yield. It is in.
【００１１】[0011]
【課題を解決するための手段】そのため本発明は、紫外
線照射を必要とする不揮発性半導体素子を具備した半導
体装置の製造方法において、前記不揮発性半導体素子と
電気接続する配線電極を絶縁膜で被覆する保護膜形成工
程と、前記絶縁膜に開口部を設け前記配線電極の所定領
域を露出させ、該所定領域を電極パッド部とするパッド
部形成工程と、前記パッド部に電気特性検査用の金属針
を接触させて前記不揮発性半導体素子に電気的に情報の
書き込みを行い検査する検査工程と、前記検査工程にて
書き込まれた前記不揮発性半導体素子の情報を前記半導
体装置に紫外線を照射して消去する紫外線照射工程と、
パッシベーション膜を形成するパッシベーション膜形成
工程と、を含むことを特徴としている。Therefore, according to the present invention, in a method of manufacturing a semiconductor device having a non-volatile semiconductor element requiring ultraviolet irradiation, a wiring electrode electrically connected to the non-volatile semiconductor element is covered with an insulating film. A protective film forming step, a step of forming an opening in the insulating film to expose a predetermined region of the wiring electrode, and a pad part forming the predetermined region as an electrode pad part, and a metal for inspecting electrical characteristics on the pad part. An inspection process of inspecting by electrically writing information to the nonvolatile semiconductor element by bringing a needle into contact, and irradiating the semiconductor device with the information of the nonvolatile semiconductor element written in the inspection process by ultraviolet rays. UV irradiation step to erase,
And a passivation film forming step of forming a passivation film.
【００１２】[0012]
【作用および効果】本発明によると、その製造工程は検
査工程の前に保護膜形成工程を行うため配線電極は事前
に絶縁膜で被覆されるため、検査工程においてプロービ
ング屑が発生しても絶縁膜上に付着することになる。そ
のため、プロービング屑が配線電極に接しないので配線
電極間の短絡や素子の漏れ電流の発生を防止でき、歩留
りを向上できるという効果がある。According to the present invention, in the manufacturing process, since the protective film forming process is performed before the inspection process, the wiring electrode is covered with the insulating film in advance, so that even if the probing waste is generated in the inspection process, the insulation is performed. It will adhere to the film. Therefore, since the probing waste does not come into contact with the wiring electrodes, it is possible to prevent a short circuit between the wiring electrodes and a leakage current of the element from occurring, and it is possible to improve the yield.
【００１３】[0013]
【実施例】本発明の実施例について、図面を用いて説明
する。図１（ａ）〜（ｅ）は本発明の第１実施例を示す
工程図であり、図２は本発明の第１実施例により製造さ
れた半導体装置の要部断面図である。Embodiments of the present invention will be described with reference to the drawings. 1 (a) to 1 (e) are process drawings showing a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of essential parts of a semiconductor device manufactured according to the first embodiment of the present invention.
【００１４】図２に示すように、本発明の第１実施例に
おいてはシリコン基板１の表面の素子形成領域には２層
ゲート構造のＥＰＲＯＭが設定され、一方、素子形成領
域以外の領域には素子分離用の厚い酸化膜８が形成さ
れ、電極パッド４が設定されている。As shown in FIG. 2, in the first embodiment of the present invention, an EPROM having a two-layer gate structure is set in the element forming area on the surface of the silicon substrate 1, while the area other than the element forming area is set. A thick oxide film 8 for element isolation is formed and an electrode pad 4 is set.
【００１５】２層ゲート構造は、第１ゲート酸化膜９、
多結晶シリコンからなるフローテイングゲート１０、こ
の多結晶シリコン膜の表面を酸化して形成された第２ゲ
ート酸化膜１１、及び２層目の多結晶シリコン膜からな
るコントロールゲート１２で構成され、ＥＰＲＯＭのソ
ース・ドレイン層１３はＡｓをシリコン基板１にイオン
注入することにより形成される。The two-layer gate structure has a first gate oxide film 9,
The floating gate 10 made of polycrystalline silicon, the second gate oxide film 11 formed by oxidizing the surface of the polycrystalline silicon film, and the control gate 12 made of the second-layer polycrystalline silicon film are used for the EPROM. The source / drain layer 13 is formed by ion-implanting As into the silicon substrate 1.
【００１６】ソース・ドレイン層１３には、層間絶縁膜
であるＢＰＳＧ膜２に形成されたココンタクト穴を介し
てアルミニウムからなる配線電極３が接触し、該配線電
極３により電極パッド４に電気接続される。A wiring electrode 3 made of aluminum comes into contact with the source / drain layer 13 through a co-contact hole formed in the BPSG film 2 which is an interlayer insulating film, and is electrically connected to the electrode pad 4 by the wiring electrode 3. To be done.
【００１７】そして、電極パッド４領域を除いて半導体
装置表面には１０００Åの薄いＰ−ＳｉＮ膜１４及び１
μｍ以上の厚いＰ−ＳｉＮ膜１５が形成される。ここ
で、薄いＰ−ＳｉＮ膜１４は紫外線が透過しえるように
設定されており、厚いＰ−ＳｉＮ膜１５は紫外線が透過
しえないように設定されている。Then, the thin P-SiN films 14 and 1 of 1000 Å are formed on the surface of the semiconductor device except the electrode pad 4 region.
A thick P-SiN film 15 having a thickness of μm or more is formed. Here, the thin P-SiN film 14 is set so that ultraviolet rays can pass therethrough, and the thick P-SiN film 15 is set so that ultraviolet rays cannot pass therethrough.
【００１８】次に、図２に示した本発明の第１実施例に
よる半導体装置の製造工程を、図１（ａ）〜（ｅ）を用
いて説明する。シリコン基板１の表面に２層ゲート構造
型ＥＰＲＯＭ（図示せず）を形成し、ＣＶＤ法にて層間
絶縁膜となるＢＰＳＧ膜２を堆積し、１０００℃以下の
温度でリフロー処理を行い、ＰＥＰにてコンタクト穴を
開口する。そしてアルミニウム等の金属材料をスパッタ
法にて被着し、配線電極３、電極パッド４を形成するた
めＰＥＰにてパターニングし、引き続いて温度約４５０
℃でシンタリング処理を行う（図１（ａ））。Next, the manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. 2 will be described with reference to FIGS. A two-layer gate structure type EPROM (not shown) is formed on the surface of the silicon substrate 1, a BPSG film 2 serving as an interlayer insulating film is deposited by a CVD method, and a reflow process is performed at a temperature of 1000 ° C. or less to form a PEP. To open the contact hole. Then, a metal material such as aluminum is deposited by the sputtering method, patterned by PEP to form the wiring electrodes 3 and the electrode pads 4, and subsequently the temperature is set to about 450.
A sintering process is performed at a temperature of 0 ° C. (FIG. 1A).
【００１９】次に、ＳｉＨ3 とＮＨ3 及びＮ2 を含む反
応ガスをプラズマＣＶＤ装置に導入してプラズマ化させ
て、シリコン基板１上のＢＰＳＧ膜２、配線電極３及び
電極パッド４を被覆する厚さ１０００ÅのＰ−ＳｉＮ膜
１４を成長させる。そして検査のためにプローブ針５を
接触させる電極パッド４上のＰ−ＳｉＮ膜１４を、ＰＥ
Ｐにて除去し開口１６を形成する（図１（ｂ））。Next, a reaction gas containing SiH 3 , NH 3 and N 2 is introduced into a plasma CVD apparatus to turn it into plasma, and the BPSG film 2, the wiring electrodes 3 and the electrode pads 4 on the silicon substrate 1 are covered. A 1000Å thick P-SiN film 14 is grown. Then, the P-SiN film 14 on the electrode pad 4 which is brought into contact with the probe needle 5 for inspection is PE
It is removed with P to form the opening 16 (FIG. 1B).
【００２０】Ｐ−ＳｉＮ膜１４は、紫外線が透過しえる
よう設定された膜であり、本実施例での形成条件は、反
応ガスの流量比としてＳｉＨ4 ：ＮＨ3 ：Ｎ2 ＝１３：
５：４０、ＲＦパワー４２０Ｗ，圧力５．０Ｔｏｒｒと
した。The P-SiN film 14 is a film set so that ultraviolet rays can pass therethrough, and the forming conditions in this embodiment are as follows: SiH4: NH3: N2 = 13:
The power was 5:40, the RF power was 420 W, and the pressure was 5.0 Torr.
【００２１】つづいて、Ｐ−ＳｉＮ膜１４の開口１６か
ら電極パッド４にタングステンのプローブ針５を接触さ
せて、形成したＥＰＲＯＭの電気特性を検査するため検
査用の情報を書き込む。そして、書き込んだ情報の保持
特性を検査するため、温度２００〜２５０℃の窒素雰囲
気中にシリコン基板１を数時間放置した後、再び、Ｐ−
ＳｉＮ膜１４の開口１６から電極パッド４にタングステ
ンのプローブ針５を接触させて、書き込んだ情報の減少
の度合を検査する。Subsequently, the probe needle 5 made of tungsten is brought into contact with the electrode pad 4 through the opening 16 of the P-SiN film 14, and the inspection information is written in order to inspect the electrical characteristics of the formed EPROM. Then, in order to inspect the retention characteristic of the written information, after leaving the silicon substrate 1 for several hours in a nitrogen atmosphere at a temperature of 200 to 250 ° C., the P-
A tungsten probe needle 5 is brought into contact with the electrode pad 4 through the opening 16 of the SiN film 14, and the degree of reduction of written information is inspected.
【００２２】この２回の電極パッド４にタングステンの
プローブ針５を接触させる検査においては従来と同様
に、電極パッド４の欠けやプローブ針５の摩耗等よって
プロービング屑７が発生するが、配線電極３は薄いＰ−
ＳｉＮ膜１４に覆われているため直接配線電極３とプロ
ービング屑７が接することはなく、配線電極３間での短
絡は発生しない（図１（ｃ））。In the inspection in which the tungsten probe needle 5 is brought into contact with the electrode pad 4 twice, the probing waste 7 is generated due to the chipping of the electrode pad 4 or the abrasion of the probe needle 5 as in the conventional case. 3 is thin P-
Since the wiring electrode 3 is covered with the SiN film 14, the wiring electrode 3 and the probing waste 7 do not come into direct contact with each other, and a short circuit does not occur between the wiring electrodes 3 (FIG. 1C).
【００２３】そして、検査工程にてＥＰＲＯＭに書き込
まれた情報を消去するため、シリコン基板１に紫外線を
照射する。紫外線の照射は７４００μＷ／cm2 で３０分
行った（図１（ｄ））。Then, in order to erase the information written in the EPROM in the inspection step, the silicon substrate 1 is irradiated with ultraviolet rays. Ultraviolet irradiation was performed for 30 minutes at 7400 μW / cm 2 (FIG. 1 (d)).
【００２４】図３に本実施例のＥＰＲＯＭのＰ−ＳｉＮ
膜１４の膜厚を変えた場合の、紫外線照射時間に対する
情報の消去特性を示す。Ｐ−ＳｉＮ膜１４の膜厚が１０
００Å以下であれば情報は約４分で消去可能であるが、
Ｐ−ＳｉＮ膜１４の膜厚が５０００Åでは紫外線を３０
分照射しても完全には消去することはできず、完全に消
去するためには紫外線の照射時間が９０分必要であっ
た。FIG. 3 shows the P-SiN of the EPROM of this embodiment.
The erasing characteristics of information with respect to the ultraviolet irradiation time when the film thickness of the film 14 is changed are shown. The film thickness of the P-SiN film 14 is 10
If it is less than 00Å, the information can be erased in about 4 minutes,
If the thickness of the P-SiN film 14 is 5000 Å
Even if it was irradiated for a minute, it could not be completely erased, and it took 90 minutes to irradiate with ultraviolet rays in order to completely erase it.
【００２５】紫外線を照射した後、検査工程で発生した
プロービング屑７を流水洗浄を行い洗い落し、パッシベ
ーション膜として２層目のＰ−ＳｉＮ膜１５をＳｉＨ4
とＮＨ3 及びＮ2 を含む反応ガスをプラズマＣＶＤ装置
に導入してプラズマ化させて１層目のＰ−ＳｉＮ膜１４
と同様の条件で１．５μｍの厚さに成長させる。そして
外部接続のためのワイヤボンデイング用開口１７をＰＥ
Ｐにて形成する（図１（ｅ））。After irradiating with ultraviolet rays, the probing waste 7 generated in the inspection process is washed off with running water, and the second P-SiN film 15 is used as a passivation film to remove SiH4.
And a reaction gas containing NH3 and N2 is introduced into a plasma CVD apparatus to generate plasma, and the first P-SiN film 14 is formed.
It is grown to a thickness of 1.5 μm under the same conditions. PE for the wire bonding opening 17 for external connection
It is formed of P (FIG. 1E).
【００２６】図３より明らかなように、パッシベーショ
ン膜として形成した厚さ１．６μｍの２層目Ｐ−ＳｉＮ
膜１５は紫外線が透過しえない膜であり、このＰ−Ｓｉ
Ｎ膜１５形成後にＥＰＲＯＭに書き込まれた情報は半永
久的に記憶される。As is apparent from FIG. 3, the second layer P-SiN having a thickness of 1.6 μm formed as a passivation film.
The film 15 is a film that cannot transmit ultraviolet rays.
The information written in the EPROM after the N film 15 is formed is semipermanently stored.
【００２７】パッシベーション膜の形成後、図示はしな
いが、チップダイシング後ワイヤボンデイングを行って
窓のない樹脂モールドパッケージに封入することによ
り、ＯＴＰＲＯＭを製造する。After forming the passivation film, although not shown, wire bonding is performed after chip dicing and the chip is diced into a resin mold package having no window to manufacture an OTPROM.
【００２８】そこで本発明の第１実施例によれば、紫外
線が透過しえるよう設定されたＰ−ＳｉＮ膜１４にて配
線電極３を被覆することにより、電極パッド４にタング
ステンのプローブ針５を接触させる検査において発生し
たプロービング屑７が配線電極３に直接接することはな
く、配線電極３間での短絡や素子の漏れ電流の発生を防
止でき、かつパッシベーション効果に優れたＰ−ＳｉＮ
膜をパッシベーション膜にもつ歩留りの高いＯＴＰＲＯ
Ｍが製造できる。Therefore, according to the first embodiment of the present invention, by covering the wiring electrode 3 with the P-SiN film 14 which is set to transmit ultraviolet rays, the tungsten probe needle 5 is attached to the electrode pad 4. The probing waste 7 generated in the contact inspection does not directly contact the wiring electrodes 3, so that a short circuit between the wiring electrodes 3 and a leakage current of the element can be prevented, and the P-SiN excellent in the passivation effect is obtained.
High-yield OTPRO with film as passivation film
M can be manufactured.
【００２９】第１実施例の他の形態として、特公昭６３
−５３７０３号に開示された紫外線を透過しえるＰ−Ｓ
ｉＮ膜を、１層目のＰ−ＳｉＮ膜１４として用いてもよ
く、特公昭６３−５３７０３号に開示された効果に加え
て、緻密な膜である２層目のＰ−ＳｉＮ膜をパッシベー
ション膜として用いてパッシベーション効果を高めるこ
とができる。As another form of the first embodiment, Japanese Patent Publication No. 63-63
-53-703 PS which can transmit ultraviolet rays
The iN film may be used as the P-SiN film 14 of the first layer, and in addition to the effect disclosed in JP-B-63-53703, the P-SiN film of the second layer, which is a dense film, may be used as the passivation film. Can be used as to enhance the passivation effect.
【００３０】次に、本発明の第２実施例である製造工程
を、図５（ａ）〜（ｆ）を用いて説明する。第１実施例
と同様に、層間絶縁膜２を形成したシリコン基板１上に
配線電極３、電極パッド４を形成し、シンタリング処理
を行った半導体装置（図５（ａ））の表面に有機樹脂膜
１８を塗布し、検査のためにプローブ針５を接触させる
電極パッド４上にＰＥＰにて開口１６’を形成する（図
５（ｂ））。Next, a manufacturing process which is a second embodiment of the present invention will be described with reference to FIGS. Similar to the first embodiment, the wiring electrode 3 and the electrode pad 4 are formed on the silicon substrate 1 on which the interlayer insulating film 2 is formed, and the sintering treatment is performed on the surface of the semiconductor device (FIG. 5A). A resin film 18 is applied, and an opening 16 'is formed by PEP on the electrode pad 4 which is brought into contact with the probe needle 5 for inspection (FIG. 5B).
【００３１】つづいて、第１実施例と同様に有機樹脂膜
１８の開口１６’から電極パッド４にタングステンのプ
ローブ針５を接触させて検査を行う（図５（ｃ））。検
査工程にて発生したプロービング屑７は、配線電極３を
被覆する有機樹脂膜１８に付着する。Subsequently, similarly to the first embodiment, a tungsten probe needle 5 is brought into contact with the electrode pad 4 through the opening 16 'of the organic resin film 18 for inspection (FIG. 5C). The probing waste 7 generated in the inspection step adheres to the organic resin film 18 that covers the wiring electrodes 3.
【００３２】つぎに、検査工程にてＥＰＲＯＭに書き込
まれた情報を消去するため、シリコン基板１に紫外線を
照射し（図５（ｄ））、つづいて、有機樹脂膜１８を除
去する（図５（ｅ））。このとき、検査工程にて発生し
有機樹脂膜１８に付着していたプロービング屑７も同時
に除去される。Next, in order to erase the information written in the EPROM in the inspection step, the silicon substrate 1 is irradiated with ultraviolet rays (FIG. 5 (d)), and then the organic resin film 18 is removed (FIG. 5). (E)). At this time, the probing waste 7 generated in the inspection process and attached to the organic resin film 18 is also removed at the same time.
【００３３】そして、パッシベーション膜として紫外線
が透過しえないよう設定されたＰ−ＳｉＮ膜１５を形成
し、外部接続のためのワイヤボンデイング用開口１７を
ＰＥＰにて形成する（図５（ｆ））。Then, a P-SiN film 15 is formed as a passivation film so that ultraviolet rays cannot pass therethrough, and a wire bonding opening 17 for external connection is formed by PEP (FIG. 5 (f)). ..
【００３４】その後、第１実施例にて説明した同様の方
法にてＯＴＰＲＯＭを製造する。尚、有機樹脂膜１８が
紫外線が透過しえる膜である場合の製造方法について第
２実施例として説明したが、有機樹脂膜１８を紫外線が
透過しえない膜で形成した場合にも、有機樹脂膜１８の
除去工程後に紫外線を照射する工程とすることにより、
本発明の効果をえることができる。After that, the OTPROM is manufactured by the same method as described in the first embodiment. Incidentally, the manufacturing method in the case where the organic resin film 18 is a film which can transmit ultraviolet rays has been described as the second embodiment, but even when the organic resin film 18 is formed of a film which cannot transmit ultraviolet rays, By the step of irradiating with ultraviolet rays after the step of removing the film 18,
The effect of the present invention can be obtained.
【００３５】本発明の第２実施例によれば、配線電極３
を被覆した有機樹脂膜１８を、電極パッド４にタングス
テンのプローブ針５を接触させる検査工程において発生
したプロービング屑７と同時に除去するため、配線電極
３間での短絡や素子の漏れ電流の発生を防止でき、かつ
パッシベーション効果に優れたＰ−ＳｉＮ膜をパッシベ
ーション膜にもつ歩留りの高いＯＴＰＲＯＭが製造でき
る。According to the second embodiment of the present invention, the wiring electrode 3
Since the organic resin film 18 coated with is removed at the same time as the probing waste 7 generated in the inspection step in which the tungsten probe needle 5 is brought into contact with the electrode pad 4, a short circuit between the wiring electrodes 3 or a leakage current of the element is prevented. It is possible to manufacture an OTPROM having a high yield which has a P-SiN film as a passivation film which can be prevented and has an excellent passivation effect.
【００３６】以上、本発明の実施例として２層ゲート構
造のＥＰＲＯＭに適用した場合について説明したが、本
発明は何ら上記実施例に限定されることなく、例えばＭ
ＮＯＳ型メモリや、多層配線時の層間絶縁膜とパッシベ
ーション膜の形成にも適用可能である。The case where the present invention is applied to an EPROM having a two-layer gate structure has been described above as an embodiment of the present invention. However, the present invention is not limited to the above-mentioned embodiment, and for example, M
It is also applicable to a NOS type memory and formation of an interlayer insulating film and a passivation film at the time of multilayer wiring.
【図１】（ａ），（ｂ），（ｃ），（ｄ），（ｅ）は本
発明の第１の実施例を示す工程説明図である。1 (a), (b), (c), (d) and (e) are process explanatory views showing a first embodiment of the present invention.
【図２】本発明の第１の実施例にて形成したＥＰＲＯＭ
の断面図である。FIG. 2 is an EPROM formed according to the first embodiment of the present invention.
FIG.
【図３】本発明の第１の実施例にて形成したＥＰＲＯＭ
の紫外線照射による情報の消去特性を示す図面である。FIG. 3 is an EPROM formed according to the first embodiment of the present invention.
5 is a diagram showing the erasing property of information by ultraviolet irradiation of FIG.
【図４】（ａ），（ｂ），（ｃ），（ｄ）は従来の半導
体装置の製造方法を示す工程説明図である。4A, 4B, 4C, and 4D are process explanatory views showing a conventional method for manufacturing a semiconductor device.
【図５】（ａ），（ｂ），（ｃ），（ｄ），（ｅ），
（ｆ）は本発明の第２の実施例を示す工程説明図であ
る。5 (a), (b), (c), (d), (e),
(F) is a process explanatory view showing a second embodiment of the present invention.
１ シリコン基板 ２ ＢＰＳＧ膜 ３ 配線電極 ４ 電極パッド ５ プローブ針 ７ プロービング屑 １４，１５ Ｐ−ＳｉＮ膜 １６，１７ 開口 １８ 有機樹脂膜 1 Silicon substrate 2 BPSG film 3 Wiring electrode 4 Electrode pad 5 Probe needle 7 Probing waste 14,15 P-SiN film 16,17 Opening 18 Organic resin film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山根 宏幸 愛知県刈谷市昭和町１丁目１番地 日本電 装株式会社内 (72)発明者 樋口 安史 愛知県刈谷市昭和町１丁目１番地 日本電 装株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroyuki Yamane, 1-1, Showa-cho, Kariya city, Aichi Prefecture, Nihon Denso Co., Ltd. (72) Inventor, Anshi Higuchi 1-1, Showa-cho, Kariya city, Aichi prefecture Within the corporation
Claims (5)
素子を具備した半導体装置の製造方法において、 前記不揮発性半導体素子と電気接続する配線電極を絶縁
膜で被覆する保護膜形成工程と、 前記絶縁膜に開口部を設け前記配線電極の所定領域を露
出させ、該所定領域を電極パッド部とするパッド部形成
工程と、 前記パッド部に電気特性検査用の金属針を接触させて前
記不揮発性半導体素子に電気的に情報の書き込みを行い
検査する検査工程と、 前記検査工程にて書き込まれた前記不揮発性半導体素子
の情報を前記半導体装置に紫外線を照射して消去する紫
外線照射工程と、 パッシベーション膜を形成するパッシベーション膜形成
工程と、 を含むことを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device comprising a non-volatile semiconductor element requiring ultraviolet irradiation, comprising: a protective film forming step of covering a wiring electrode electrically connected to the non-volatile semiconductor element with an insulating film; A pad portion forming step of forming an opening in the film to expose a predetermined region of the wiring electrode, and using the predetermined region as an electrode pad portion; An inspection step of electrically writing information to the element and inspecting it, an ultraviolet irradiation step of erasing the information of the nonvolatile semiconductor element written in the inspection step by irradiating the semiconductor device with ultraviolet rays, and a passivation film And a passivation film forming step of forming a semiconductor device.
前記絶縁膜は、紫外線を透過しえるよう設定された窒化
シリコン膜であって、この窒化シリコン膜は反応ガスの
プラズマ化によって形成される請求項１に記載の半導体
装置の製造方法。2. The insulating film formed in the protective film forming step is a silicon nitride film set to transmit ultraviolet rays, and the silicon nitride film is formed by converting reaction gas into plasma. Item 2. A method of manufacturing a semiconductor device according to item 1.
て形成される前記パッシベーション膜は、前記保護膜形
成工程において形成された前記窒化シリコン膜上に形成
され、紫外線を透過しえないように設定された窒化シリ
コン膜を含み、この窒化シリコン膜は反応ガスのプラズ
マ化によって形成される請求項２に記載の半導体装置の
製造方法。3. The silicon nitride film formed in the passivation film forming step is formed on the silicon nitride film formed in the protective film forming step, and is set so as not to transmit ultraviolet rays. The method of manufacturing a semiconductor device according to claim 2, further comprising a film, wherein the silicon nitride film is formed by converting a reactive gas into plasma.
はパッシベーション膜形成工程のいずれかに先だち除去
する保護膜除去工程を含む請求項１に記載の半導体装置
の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, further comprising a protective film removing step of removing the protective film prior to either the ultraviolet irradiation step or the passivation film forming step.
て形成される前記パッシベーション膜は前記配線電極を
直接被覆するように形成され、紫外線を透過しえないよ
うに設定された窒化シリコン膜を含み、この窒化シリコ
ン膜は反応ガスのプラズマ化によって形成される請求項
４に記載の半導体装置の製造方法。5. The passivation film formed in the passivation film forming step includes a silicon nitride film which is formed so as to directly cover the wiring electrode and which is set so as not to transmit ultraviolet rays. The method of manufacturing a semiconductor device according to claim 4, wherein the film is formed by converting reaction gas into plasma.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10108392A JPH05299660A (en) | 1992-04-21 | 1992-04-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10108392A JPH05299660A (en) | 1992-04-21 | 1992-04-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05299660A true JPH05299660A (en) | 1993-11-12 |
Family
ID=14291210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10108392A Withdrawn JPH05299660A (en) | 1992-04-21 | 1992-04-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05299660A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006203215A (en) * | 2006-01-23 | 2006-08-03 | Renesas Technology Corp | Semiconductor integrated circuit device and method of manufacturing the same |
| JP2010034595A (en) * | 2009-11-12 | 2010-02-12 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
| WO2014129252A1 (en) * | 2013-02-21 | 2014-08-28 | セイコーインスツル株式会社 | Ultraviolet-erasable nonvolatile semiconductor device |
-
1992
- 1992-04-21 JP JP10108392A patent/JPH05299660A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006203215A (en) * | 2006-01-23 | 2006-08-03 | Renesas Technology Corp | Semiconductor integrated circuit device and method of manufacturing the same |
| JP2010034595A (en) * | 2009-11-12 | 2010-02-12 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
| WO2014129252A1 (en) * | 2013-02-21 | 2014-08-28 | セイコーインスツル株式会社 | Ultraviolet-erasable nonvolatile semiconductor device |
| JP2014165191A (en) * | 2013-02-21 | 2014-09-08 | Seiko Instruments Inc | Ultraviolet ray erasure type nonvolatile semiconductor device |
| CN105074887A (en) * | 2013-02-21 | 2015-11-18 | 精工电子有限公司 | Ultraviolet-erasable nonvolatile semiconductor device |
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