JPH05291413A - Multilayer interconnection structure for semiconductor integrated circuit device - Google Patents

Multilayer interconnection structure for semiconductor integrated circuit device

Info

Publication number
JPH05291413A
JPH05291413A JP11304292A JP11304292A JPH05291413A JP H05291413 A JPH05291413 A JP H05291413A JP 11304292 A JP11304292 A JP 11304292A JP 11304292 A JP11304292 A JP 11304292A JP H05291413 A JPH05291413 A JP H05291413A
Authority
JP
Japan
Prior art keywords
insulating film
interlayer insulating
integrated circuit
circuit device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11304292A
Other languages
Japanese (ja)
Inventor
Junichi Takahashi
淳一 高橋
Katsuyuki Machida
克之 町田
Nobuhiro Shimoyama
展弘 下山
Kazushige Minegishi
一茂 峯岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11304292A priority Critical patent/JPH05291413A/en
Priority to US08/005,670 priority patent/US5376590A/en
Publication of JPH05291413A publication Critical patent/JPH05291413A/en
Priority to US08/296,025 priority patent/US5512513A/en
Priority to US08/594,947 priority patent/US5811872A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To prevent water contained in the layer insulating film of a multilayer metal interconnection structure from reaching a substrate side to a semiconductor element from the insulating film and deteriorating the metal wiring layer and prevent the deterioration of the element characteristics. CONSTITUTION:An SiO2 element isolation insulating film 3 is formed on the major plane of a P-type Si substrate 1 other than many element forming areas 2. A gate electrode 5 is formed in the element forming area 2 through a gate insulating film and an n-type source area 6 and a drain area 7 are formed on the both sides of the gate electrode 5. Then, an oxide film 10 which covers the both areas 6 and 7 with windows 8 and 9 that permit the both areas to face outside is formed. Source and drain metal wiring layers 11 and 12 connected to the source and drain areas through the windows are formed on the oxide film 10 and a layer insulating layer 13 is formed by covering the wiring layers. The layer insulating film is an insulating film laminating body which is formed by sandwiching an insulating film 15, which has a characteristic that permits its formation on a top plane whose level differences are modified even when the base top plane has the level difference, by SiO2 insulating films 14 and 16 which have internal point defects.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】本発明は、多数の半導体素子を形成してい
る半導体基板上に複数の金属配線層が層間絶縁膜を介し
て多層に形成されている構成を有する半導体集積回路装
置における多層配線構体に関する。The present invention relates to a multilayer wiring structure in a semiconductor integrated circuit device having a structure in which a plurality of metal wiring layers are formed in multiple layers on a semiconductor substrate on which a large number of semiconductor elements are formed with an interlayer insulating film interposed therebetween. ..

【０００２】従来、多数の半導体素子を形成している半
導体基板上に複数の金属配線層が層間絶縁膜を介して多
層に形成されている構成を有する半導体集積回路装置に
おける多層配線構体が種々提案されている。Conventionally, various multilayer wiring structures have been proposed in a semiconductor integrated circuit device having a structure in which a plurality of metal wiring layers are formed in multiple layers via an interlayer insulating film on a semiconductor substrate on which a large number of semiconductor elements are formed. Has been done.

【０００３】この場合、層間絶縁膜は、その上に形成さ
れる金属配線層が断線のおそれなしに形成されているこ
との必要から、層間絶縁膜が形成される下地の上面に段
差を有していてもその段差を緩和した上面に形成される
性質（流動性）を有する絶縁材でなる絶縁膜でなるのが
望ましい。In this case, the interlayer insulating film has a step on the upper surface of the base on which the interlayer insulating film is formed, because the metal wiring layer formed on the interlayer insulating film needs to be formed without fear of disconnection. However, it is desirable that the insulating film is made of an insulating material that has the property (fluidity) of being formed on the upper surface with the step difference alleviated.

【０００４】しかしながら、層間絶縁膜が、そのような
性質を有する絶縁材でなる絶縁膜でなる場合、その絶縁
膜は、一般に、種々の形で水分を無視し得ない量含んで
いる。例えば層間絶縁膜を構成している、上述した段差
を緩和した上面に形成される絶縁膜が、常圧ＣＶＤ法に
よって形成されているＳｉＯ2 でなる場合、その絶縁膜
は、シラノ―ル、シロキサンなどの形で水分を、無視し
得ない量で含んでいる。However, when the interlayer insulating film is an insulating film made of an insulating material having such a property, the insulating film generally contains water in various forms in a non-negligible amount. For example, when the insulating film that is formed on the upper surface of the interlayer insulating film with the step difference relaxed is made of SiO 2 formed by the atmospheric pressure CVD method, the insulating film is made of silanol or siloxane. It contains water in a non-negligible amount.

【０００５】このため、層間絶縁膜が、上述した段差を
緩和した上面に形成される絶縁材でなる絶縁膜のみでな
る場合、半導体集積回路装置の動作時、その絶縁膜の水
分が、半導体基板側に、それを用いて形成されている多
数の半導体素子乃至その近傍にまで達し、それら多数の
半導体素子が所期の特性で動作せず、従って、半導体集
積回路装置が所期の特性で動作しない、という欠点を有
していた。For this reason, when the interlayer insulating film is only the insulating film made of the insulating material formed on the upper surface with the step difference alleviated, the water content of the insulating film during the operation of the semiconductor integrated circuit device is changed to the semiconductor substrate. On the side, reaching a large number of semiconductor elements formed by using the semiconductor element or the vicinity thereof, the large number of semiconductor elements do not operate with the desired characteristics, and therefore the semiconductor integrated circuit device operates with the desired characteristics. It had the drawback of not doing it.

【０００６】また、層間絶縁膜が、上述した段差を緩和
した上面に形成される絶縁材でなる絶縁膜のみでなる場
合、半導体集積回路装置の動作時、その絶縁膜の水分
が、層間絶縁膜上に形成されている金属配線層に達し、
それを酸化するなどして、金属配線層を劣化させる、と
いう欠点を有していた。Further, when the interlayer insulating film is only an insulating film made of an insulating material formed on the upper surface in which the above-mentioned step is relaxed, when the semiconductor integrated circuit device is in operation, the moisture in the insulating film causes the interlayer insulating film to become wet. Reach the metal wiring layer formed above,
It has a drawback that the metal wiring layer is deteriorated by oxidizing it.

【０００７】よって、本発明は上述した欠点のない、新
規な半導体集積回路装置の多層配線構体を提案せんとす
るものである。Therefore, the present invention proposes a novel multilayer wiring structure of a semiconductor integrated circuit device which does not have the above-mentioned drawbacks.

【０００８】[0008]

【課題を解決するための手段】本発明による半導体集積
回路装置における多層配線構体は、前述した従来の半導
体集積回路装置における多層配線構体の場合と同様に、
多数の半導体素子を形成している半導体基板上に、複数
の金属配線層が、層間絶縁膜を介して、多層に形成され
ている構成を有する。A multi-layer wiring structure in a semiconductor integrated circuit device according to the present invention is similar to the multi-layer wiring structure in the conventional semiconductor integrated circuit device described above.
It has a structure in which a plurality of metal wiring layers are formed in multiple layers via an interlayer insulating film on a semiconductor substrate on which a large number of semiconductor elements are formed.

【０００９】しかしながら、本発明による半導体集積回
路装置における多層配線構体は、このような構成を有す
る半導体集積回路装置の多層配線構体において、上記層
間絶縁膜が、内部に点欠陥を有する絶縁膜と、上記層間
絶縁膜が形成される下地の上面に段差を有していてもそ
の段差を緩和した上面に形成される性質を有する絶縁材
でなる絶縁膜とがそれらの順に積層させている構成を有
する絶縁膜積層体でなる。However, in the multilayer wiring structure in the semiconductor integrated circuit device according to the present invention, in the multilayer wiring structure of the semiconductor integrated circuit device having such a structure, the interlayer insulating film has an insulating film having a point defect inside. Even if there is a step on the upper surface of the base on which the above-mentioned interlayer insulating film is formed, an insulating film made of an insulating material having a property of being formed on the upper surface with the step relaxed is laminated in that order. It is made of an insulating film laminate.

【００１０】[0010]

【作用・効果】本発明による半導体集積回路装置の多層
配線構体によれば、層間絶縁膜が段差を緩和した上面に
形成される性質を有する絶縁材でなる絶縁膜を有する絶
縁膜積層体でなるので、その層間絶縁膜の上面が段差の
緩和された上面を有し、従って、層間絶縁膜上の金属配
線層が断線のおそれなしに形成されている。According to the multilayer wiring structure of the semiconductor integrated circuit device of the present invention, the insulating film laminate has an insulating film made of an insulating material having a property that the interlayer insulating film is formed on the upper surface with reduced steps. Therefore, the upper surface of the interlayer insulating film has an upper surface with reduced steps, and therefore the metal wiring layer on the interlayer insulating film is formed without fear of disconnection.

【００１１】また、層間絶縁膜が、点欠陥を有する絶縁
膜を有する絶縁膜積層体でなり、そして、点欠陥を有す
る絶縁膜が、その絶縁膜中に拡散、遊離した電子、イオ
ン、中性原子などを捕獲する性質を有することから、水
分を効果的に捕獲する高い能力を有しているので、層間
絶縁膜が形成される下地の上面に段差を有していてもそ
の段差を緩和した上面に形成される性質を有する絶縁材
でなる絶縁膜が種々の形で水分を含んでいるとしても、
その水分が、層間絶縁膜から半導体基板側に、それを用
いて形成されている多数の半導体素子乃至それらの近傍
にまで達するのを有効に阻止することができる。このた
め、半導体素子を所期の特性で動作させることができ、
従って、半導体集積回路装置を所期の特性で動作させる
ことができる。Further, the interlayer insulating film is an insulating film laminated body having an insulating film having a point defect, and the insulating film having a point defect is diffused and liberated in the insulating film. Since it has a property of trapping atoms and the like, it has a high ability to trap water effectively. Therefore, even if there is a step on the upper surface of the base on which the interlayer insulating film is formed, the step is relaxed. Even if the insulating film made of an insulating material having a property of being formed on the upper surface contains water in various forms,
It is possible to effectively prevent the water content from reaching the semiconductor substrate side from the interlayer insulating film to a large number of semiconductor elements formed using the same or the vicinity thereof. Therefore, the semiconductor element can be operated with the desired characteristics,
Therefore, the semiconductor integrated circuit device can be operated with desired characteristics.

【００１２】[0012]

【実施例】次に、図１を伴って、本発明による半導体集
積回路装置の多層配線構体の実施例を述べよう。EXAMPLE Next, an example of the multilayer wiring structure of the semiconductor integrated circuit device according to the present invention will be described with reference to FIG.

【００１３】図１に示す、本発明による半導体集積回路
装置の多層配線構体は、次に述べる構成を有する。The multi-layer wiring structure of the semiconductor integrated circuit device according to the present invention shown in FIG. 1 has the structure described below.

【００１４】すなわち、例えばｐ型を有し且つＳｉでな
る半導体基板１を有し、その主面１ａ側に、多数の素子
形成領域２を画成するように（ただし、図においては、
簡単のため１つの素子形成領域２だけが示されてい
る）、ＳｉＯ2 でなる素子分離用絶縁膜３が、熱酸化に
よって形成されている。That is, for example, a semiconductor substrate 1 having a p-type and made of Si is provided, and a large number of element formation regions 2 are defined on the main surface 1a side (however, in the drawing,
For simplification, only one element formation region 2 is shown), and an element isolation insulating film 3 made of SiO 2 is formed by thermal oxidation.

【００１５】また、半導体基板１の主面１ａ上に、素子
形成領域２上において、ＳｉＯ2 でなるゲ―ト用絶縁膜
４を介して、ゲ―ト用電極５が形成されている。A gate electrode 5 is formed on the element forming region 2 on the main surface 1a of the semiconductor substrate 1 via a gate insulating film 4 made of SiO 2 .

【００１６】さらに、半導体基板１内に、上方からみ
て、ゲ―ト電極５を挟んだ両位置に、ｎ型を有するソ―
ス用半導体領域６及びドレイン用半導体領域７が形成さ
れている。Further, in the semiconductor substrate 1, as viewed from above, both sides of the gate electrode 5 sandwich the n-type source.
A semiconductor region 6 for drain and a semiconductor region 7 for drain are formed.

【００１７】また、半導体基板１上に、ゲ―ト用電極５
を覆い且つソ―ス用半導体領域６及びドレイン用半導体
領域７を外部にそれぞれ臨ませる窓８及び９を有する絶
縁膜１０が形成されている。この場合、絶縁膜１０は、
ＳｉＯ2 でなり、それ自体は公知の常圧ＣＶＤ法によっ
て形成されている。Further, on the semiconductor substrate 1, a gate electrode 5 is formed.
An insulating film 10 is formed which has windows 8 and 9 which cover the source semiconductor region 6 and the drain semiconductor region 7 to the outside. In this case, the insulating film 10 is
It is made of SiO 2 , and is itself formed by a known atmospheric pressure CVD method.

【００１８】さらに、絶縁膜１０上に、その窓８及び９
をそれぞれ通じてソ―ス用半導体領域６及びドレイン用
半導体領域７に連結しているソ―ス用金属配線層１１及
びドレイン用金属配線層１２が形成されている。Further, windows 8 and 9 are formed on the insulating film 10.
A metal wiring layer 11 for a source and a metal wiring layer 12 for a drain, which are connected to the semiconductor region 6 for a source and the semiconductor region 7 for a drain, respectively, are formed.

【００１９】また、半導体基板１上に、絶縁膜１０を介
し且つソ―ス用金属配線層１１及びドレイン領域用金属
配線層１２を覆って延長している層間絶縁膜１３が形成
されている。Further, an interlayer insulating film 13 is formed on the semiconductor substrate 1 and extends through the insulating film 10 and covers the source metal wiring layer 11 and the drain region metal wiring layer 12.

【００２０】この場合、層間絶縁膜１３は、ＳｉＯ2 で
なり且つ点欠陥を有する絶縁膜１４と、ＳｉＯ2 でなり
且つ層間絶縁膜１３が形成される下地の上面に（絶縁膜
１０上にゲ―ト用電極５を形成している状態での、それ
らによる上面）段差を有していてもその段差を緩和した
上面に形成される性質（流動性）を有する絶縁膜１５
と、ＳｉＯ2 でなり且つ点欠陥を有する他の絶縁膜１６
とがそれらの順に積層されている構成を有する絶縁膜積
層体１７でなる。In this case, the interlayer insulating film 13 is made of SiO 2 and has point defects, and the interlayer insulating film 13 made of SiO 2 is formed on the upper surface of the base (on the insulating film 10). -Insulating film 15 having the property (fluidity) of being formed on the upper surface with the step reduced, even if there is a step due to the electrode 5 for forming
And another insulating film 16 made of SiO 2 and having point defects
And an insulating film laminated body 17 having a structure in which they are laminated in that order.

【００２１】この場合、絶縁膜１４及び１６が点欠陥を
有するとは、絶縁膜を構成している原子（この場合Ｓｉ
原子）に不対電子を有していない原子（この場合Ｓｉ原
子）を１０18スピン・ｃｍ3 以上のような高い濃度で有
することを意味する。また、実際上、点欠陥を有する絶
縁膜１４及び１６は、シランＳｉＨ4 と酸素Ｏ2 とを原
料ガスとして用い、そしてそれらの流量比（ＳｉＨ4 の
流量／Ｏ2 の流量）を０．５〜０．８とし、また、堆積
圧力を１．Ｔｏｒｒとし、さらに、マイクロ波電力を６
００ＷとしたサイクロトロンプラズマＣＶＤ法によっ
て、例えば０．３μｍの厚さに形成し、また、絶縁膜１
５は、プラズマを用いない通常のそれ自体は公知の常圧
ＣＶＤ法によって、１．０μｍの厚さに形成した。な
お、絶縁膜１４及び１６が点欠陥を有することは、電子
スピン共鳴法によって同定した。In this case, the fact that the insulating films 14 and 16 have point defects means that the atoms forming the insulating film (Si in this case).
It means that the atom (atom) has no unpaired electron (Si atom in this case) at a high concentration of 10 18 spin · cm 3 or more. In practice, the insulating films 14 and 16 having point defects use silane SiH 4 and oxygen O 2 as source gases, and their flow rate ratio (flow rate of SiH 4 / flow rate of O 2 ) is 0.5. .About.0.8, and the deposition pressure was 1. Torr and microwave power of 6
The insulating film 1 is formed to a thickness of, for example, 0.3 μm by the cyclotron plasma CVD method with 00 W.
No. 5 was formed to a thickness of 1.0 μm by a normal atmospheric pressure CVD method known per se without using plasma. Note that the insulating films 14 and 16 have point defects were identified by an electron spin resonance method.

【００２２】さらに、上述した絶縁膜積層体１７でなる
層間絶縁膜１３上に、他の金属配線層１８が形成されて
いる。Further, another metal wiring layer 18 is formed on the interlayer insulating film 13 formed of the insulating film laminate 17 described above.

【００２３】以上が、本発明による半導体集積回路装置
における多層配線構体の実施例の構成である。The above is the configuration of the embodiment of the multilayer wiring structure in the semiconductor integrated circuit device according to the present invention.

【００２４】このような構成を有する本発明による半導
体集積回路装置における多層配線構体は、多数のＭＯＳ
型電界効果トランジスタを多数の半導体素子として形成
している半導体基板１上に、金属配線層１１及び１２
と、金属配線層１８とが、層間絶縁膜１３を介して、多
層（図においては２層）に形成されている構成を有する
が、このような構成を有する本発明による半導体集積回
路装置の多層配線構体によれば、層間絶縁膜１３が、そ
れが形成される下地の上面（絶縁膜１０上にゲ―ト用電
極５を形成している状態での、それらによる上面）に段
差を有していてもその段差を緩和した上面に形成される
性質を有する絶縁材でなる絶縁膜１５を有する絶縁膜積
層体１７でなるので、層間絶縁膜１３が、図示のよう
に、段差の緩和された上面を有し、このため、層間絶縁
膜１３上の金属配線層１８が、図示のように、断線のお
それなしに形成されている。The multi-layered wiring structure in the semiconductor integrated circuit device according to the present invention having such a structure has a large number of MOSs.
Wiring field layers 11 and 12 are formed on a semiconductor substrate 1 having a plurality of semiconductor field effect transistors as semiconductor elements.
The metal wiring layer 18 and the metal wiring layer 18 are formed in multiple layers (two layers in the figure) via the interlayer insulating film 13. The multilayer structure of the semiconductor integrated circuit device according to the present invention having such a configuration. According to the wiring structure, the interlayer insulating film 13 has a step on the upper surface of the base on which it is formed (the upper surface due to the gate electrode 5 formed on the insulating film 10). However, since the insulating film laminate 17 has the insulating film 15 made of an insulating material having a property of being formed on the upper surface with the step reduced, the interlayer insulating film 13 has the step reduced as illustrated. Since it has an upper surface, the metal wiring layer 18 on the interlayer insulating film 13 is formed without fear of disconnection as shown in the figure.

【００２５】また、層間絶縁膜１３が、点欠陥を有する
絶縁膜１４を有する絶縁膜積層体１７でなり、そして、
点欠陥を有する絶縁膜１４が、その絶縁膜１４中に拡
散、遊離した電子、イオン、中性原子などを捕獲する性
質を有することから、水分を効果的に捕獲する高い能力
を有しているので、層間絶縁膜１３が形成される下地の
上面（絶縁膜１０上にゲ―ト用電極５を形成している状
態での、それらによる上面）に段差を有していてもその
段差を緩和した上面に形成される性質を有する絶縁材で
なる絶縁膜１７が種々の形で水分を含んでいるとして
も、その水分が、層間絶縁膜１３から半導体基板１側
に、それを用いて形成されている多数の半導体素子とし
てのＭＯＳ型電界効果トランジスタ乃至その近傍（例え
ばゲ―ト用絶縁膜４）にまで達するのを有効に阻止する
ことができる。このため、半導体素子としてのＭＯＳ型
電界効果トランジスタを所期の特性で動作させることが
でき、従って、半導体集積回路装置を所期の特性で動作
させることができる。The interlayer insulating film 13 is an insulating film laminated body 17 having an insulating film 14 having point defects, and
Since the insulating film 14 having point defects has a property of trapping electrons, ions, neutral atoms, etc. diffused and released in the insulating film 14, it has a high ability to trap water effectively. Therefore, even if there is a step on the upper surface of the base on which the interlayer insulating film 13 is formed (the upper surface due to those when the gate electrode 5 is formed on the insulating film 10), the step is reduced. Even if the insulating film 17 made of an insulating material having a property of being formed on the upper surface contains moisture in various forms, the moisture is formed from the interlayer insulating film 13 to the semiconductor substrate 1 side by using it. It is possible to effectively prevent reaching a MOS type field effect transistor as a large number of semiconductor elements or its vicinity (for example, the gate insulating film 4). Therefore, the MOS field effect transistor as the semiconductor element can be operated with the desired characteristics, and therefore the semiconductor integrated circuit device can be operated with the desired characteristics.

【００２６】さらに、層間絶縁膜１３が、点欠陥を有す
る絶縁膜１６を有する絶縁膜積層体１７でなるので、層
間絶縁膜１３が形成される下地の上面（絶縁膜１０上に
ゲ―ト用電極５を形成している状態での、それらによる
上面）に段差を有していてもそ段差を緩和した上面に形
成される性質（流動性）を有する絶縁膜１５が種々の形
で水分を含んでいても、その水分が、層間絶縁膜１３か
ら、その上に形成されている金属配線層１８に達するの
を有効に阻止し、よって、金属配線層１８が水分によっ
て酸化したりして変質するのを有効に回避させることが
できる。Further, since the interlayer insulating film 13 is the insulating film laminated body 17 having the insulating film 16 having the point defect, the upper surface of the base on which the interlayer insulating film 13 is formed (on the insulating film 10 for a gate) The insulating film 15 having the property (fluidity) of being formed on the upper surface with the step 5 relaxed even if there is a step on the upper surface formed by the electrodes 5 containing water in various forms. Even so, the moisture is effectively prevented from reaching the metal wiring layer 18 formed thereon from the interlayer insulating film 13, so that the metal wiring layer 18 is oxidized and altered by the moisture. Can be effectively avoided.

【００２７】ちなみに、半導体素子としてのＭＯＳ型電
界効果トランジスタを構成しているゲ―ト用電極５が、
０．５μｍの長さを有する場合において、ＭＯＳ型電界
効果トランジスタの動作時、半導体基板１に流れる電流
Ｉs とゲ―ト用電極５の幅Ｗg との比Ｉs ／Ｗg に対す
る、ＭＯＳ型電界効果トランジスタの動作開始時点から
コンダクタンスの変動が１０％に達する時間として定義
したＭＯＳ型トランジスタの寿命を測定したところ、図
２の実線で示す結果が得られた。これに対し、本発明に
よらずに、層間絶縁膜１３が、層間絶縁膜１３が形成さ
れる下地の上面に段差を有していてもその段差を緩和し
た上面に形成される性質（流動性）を有する絶縁膜１５
のみでなる場合（ただし、全体の厚さが上述した本発明
の実施例の場合と同じ）、図２の点線で示す結果が得ら
れた。このことからも、図１に示す本発明による半導体
集積回路装置の多層配線構体によれば、半導体素子とし
てのＭＯＳ型電界効果トランジスタが、所期の優れた特
性で動作することが明らかであろう。Incidentally, the gate electrode 5 constituting the MOS field effect transistor as a semiconductor element is
In the case of having a length of 0.5 μm, when the MOS type field effect transistor is operating, the ratio of the current I s flowing in the semiconductor substrate 1 to the width W g of the gate electrode 5 I s / W g with respect to the MOS The life of the MOS transistor, which is defined as the time when the change in the conductance reaches 10% from the start of the operation of the field effect transistor, was measured, and the result shown by the solid line in FIG. 2 was obtained. On the other hand, regardless of the present invention, even if the interlayer insulating film 13 has a step on the upper surface of the base on which the interlayer insulating film 13 is formed, the interlayer insulating film 13 is formed on the upper surface with reduced step (fluidity). Insulating film 15 having
In the case of only the above (however, the total thickness is the same as in the above-mentioned embodiment of the present invention), the results shown by the dotted line in FIG. 2 were obtained. From this, it will be apparent that, according to the multilayer wiring structure of the semiconductor integrated circuit device of the present invention shown in FIG. 1, the MOS field effect transistor as the semiconductor element operates with the desired excellent characteristics. ..

【００２８】なお、上述においては、層間絶縁膜１３を
構成している絶縁膜積層体１７の点欠陥を有する絶縁膜
１４及び１６が、シランＳｉＨ4 と酸素Ｏ2 とを原料ガ
スとして用いて形成されている場合につき述べたが、原
料ガスとして、シランＳｉＨ4 に代えジシランＳｉ2 Ｈ
6 を用い、また酸素Ｏ2 に代え酸化窒素Ｎ2 Ｏを用いて
点欠陥を有する絶縁膜１４及び１６を形成することもで
きる。In the above description, the insulating films 14 and 16 having point defects of the insulating film stack 17 forming the interlayer insulating film 13 are formed by using silane SiH 4 and oxygen O 2 as source gases. As described above, disilane Si 2 H is used as the source gas instead of silane SiH 4.
Alternatively, the insulating films 14 and 16 having point defects can be formed by using 6 and using nitrogen oxide N 2 O instead of oxygen O 2 .

【００２９】また、半導体基板１を用いて形成される半
導体素子がＭＯＳ型電界効果トランジスタである場合に
適用した場合を述べたが、他の半導体素子である場合に
適用することもでき、その他、本発明の精神を脱するこ
となしに、種々の変型、変更をなし得るであろう。The case where the semiconductor element formed by using the semiconductor substrate 1 is a MOS field effect transistor has been described, but the invention can also be applied to the case where the semiconductor element is another semiconductor element. Various modifications and changes may be made without departing from the spirit of the present invention.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明による半導体集積回路装置における多層
配線構体の実施例の説明に供する略線的断面図である。FIG. 1 is a schematic sectional view for explaining an embodiment of a multilayer wiring structure in a semiconductor integrated circuit device according to the present invention.

【図２】図１に示す本発明による半導体集積回路装置に
おける多層配線構体の良さを、半導体基板に流れる電流
Ｉs とゲ―ト用電極の幅Ｗg との比Ｉs ／Ｗg に対す
る、コンダクタンスの変動が１０％に達する時間で定義
したＭＯＳ型電界効果トランジスタの寿命の関係で、従
来の多層配線構体と対比して示す図である。2 is a graph showing the goodness of the multilayer wiring structure in the semiconductor integrated circuit device according to the present invention shown in FIG. 1 with respect to the ratio I s / W g of the current I s flowing in the semiconductor substrate and the width W g of the gate electrode. It is a figure shown in contrast with the conventional multilayer wiring structure in the relation of the life of the MOS field effect transistor defined by the time when the fluctuation of the conductance reaches 10%.

【符号の説明】[Explanation of symbols]

１ 半導体基板 １ａ 半導体基板１の主面 ２ 素子形成領域 ３ 素子分離用絶縁膜 ４ ゲ―ト用絶縁膜 ５ ゲ―ト用電極 ６ ソ―ス用半導体領域 ７ ドレイン用半導体領域 ８、９ 窓 １０ 絶縁膜 １１ ソ―ス用金属配線層 １２ ドレイン用金属配線層 １３ 層間絶縁膜 １４ 点欠陥を有する絶縁膜 １５ 層間絶縁膜１３が形成される下地の
上面に段差を有していてもそ段差を緩和した上面に形成
される性質（流動性）を有する絶縁膜 １６ 点欠陥を有する絶縁膜 １７ 絶縁膜積層体 １８ 金属配線層DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Main surface of semiconductor substrate 1 2 Element formation region 3 Insulation film for element isolation 4 Insulation film for gate 5 Gate electrode 6 Semiconductor region for source 7 Semiconductor region for drain 8, 9 Window 10 Insulating film 11 Metal wiring layer for source 12 Metal wiring layer for drain 13 Interlayer insulating film 14 Insulating film with point defect 15 Even if there is a step on the upper surface of the base on which the interlayer insulating film 13 is formed, the step is mitigated. Film having properties (fluidity) formed on the formed upper surface 16 Insulation film having point defects 17 Insulation film laminate 18 Metal wiring layer

フロントページの続き (72)発明者 峯岸 一茂 東京都千代田区内幸町１丁目１番６号 日 本電信電話株式会社内Front Page Continuation (72) Inventor Kazumishi Minegishi 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 多数の半導体素子を形成している半導体
基板上に、複数の金属配線層が、層間絶縁膜を介して、
多層に形成されている半導体集積回路装置における多層
配線構体において、 上記層間絶縁膜が、内部に点欠陥を有する絶縁膜と、上
記層間絶縁膜が形成される下地の上面に段差を有してい
てもその段差を緩和した上面に形成される性質を有する
絶縁材でなる絶縁膜とがそれらの順に積層させている構
成を有する絶縁膜積層体でなることを特徴とする半導体
集積回路装置における多層配線構体。1. A plurality of metal wiring layers are formed on a semiconductor substrate on which a large number of semiconductor elements are formed, with an interlayer insulating film interposed therebetween.
In a multilayer wiring structure of a semiconductor integrated circuit device formed in multiple layers, the interlayer insulating film has an insulating film having a point defect inside and a step on the upper surface of a base on which the interlayer insulating film is formed. A multi-layer wiring in a semiconductor integrated circuit device, characterized in that it is an insulating film laminate having a structure in which an insulating film made of an insulating material having a property of being formed on the upper surface of which the step is relaxed is laminated in that order. Structure.
JP11304292A 1992-01-20 1992-04-06 Multilayer interconnection structure for semiconductor integrated circuit device Pending JPH05291413A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP11304292A JPH05291413A (en) 1992-04-06 1992-04-06 Multilayer interconnection structure for semiconductor integrated circuit device
US08/005,670 US5376590A (en) 1992-01-20 1993-01-19 Semiconductor device and method of fabricating the same
US08/296,025 US5512513A (en) 1992-01-20 1994-08-25 Method of fabricating semiconductor device with water protective film
US08/594,947 US5811872A (en) 1992-01-20 1996-01-31 Semiconductor device and method of farbricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11304292A JPH05291413A (en) 1992-04-06 1992-04-06 Multilayer interconnection structure for semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH05291413A true JPH05291413A (en) 1993-11-05

Family

ID=14602017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11304292A Pending JPH05291413A (en) 1992-01-20 1992-04-06 Multilayer interconnection structure for semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH05291413A (en)

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