JPH05291412A - Production of semiconductor device - Google Patents
Production of semiconductor deviceInfo
- Publication number
- JPH05291412A JPH05291412A JP8874992A JP8874992A JPH05291412A JP H05291412 A JPH05291412 A JP H05291412A JP 8874992 A JP8874992 A JP 8874992A JP 8874992 A JP8874992 A JP 8874992A JP H05291412 A JPH05291412 A JP H05291412A
- Authority
- JP
- Japan
- Prior art keywords
- sio
- layer
- film
- sio2
- wiring layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法に関し、より詳しくは、多層配線間に形成される
絶縁膜を備えた半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an insulating film formed between multi-layer wiring and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】層間絶縁膜は、半導体集積回路内の多層
配線間の絶縁をとるために必須のもので、絶縁を補償す
るだけではなく、下地の半導体集積回路パターンを平坦
化してその上の配線パターンの段差切れを防止する働き
をする材料が要求されている。2. Description of the Related Art An interlayer insulating film is indispensable for providing insulation between multi-layered wirings in a semiconductor integrated circuit, and not only compensates for the insulation, but also flattens the underlying semiconductor integrated circuit pattern to flatten it. There is a demand for a material that functions to prevent step breaks in the wiring pattern.
【０００３】このような層間絶縁膜材料としては、濡れ
性の良い“水ＴＥＯＳ(Tetraethylorthosilicate) ”が
用いられており、これをウェハに塗布し、加熱分解する
ことによりSiO2を形成することになる。反応式は次の通
りであり、分解処理温度は６５０℃である。As such an interlayer insulating film material, "water TEOS (Tetraethylorthosilicate)" having good wettability is used, and this is applied to a wafer and thermally decomposed to form SiO 2. .. The reaction formula is as follows, and the decomposition treatment temperature is 650 ° C.
【０００４】Si(OC2H5)4 → SiO2＋4C2H4 ＋2H2OSi (OC 2 H 5 ) 4 → SiO 2 + 4C 2 H 4 + 2H 2 O
【０００５】[0005]
【発明が解決しようとする課題】しかし、SiO2は比誘電
率が４.0と大きいために、多層配線間の寄生容量も大き
くなり、時定数ＣＲにより決定される動作遅延が大きな
問題となってきている。However, since SiO 2 has a large relative dielectric constant of 4.0, the parasitic capacitance between the multi-layered wirings also becomes large, and the operation delay determined by the time constant CR becomes a big problem. Is coming.
【０００６】素子そのものの遅延スピードは、トップデ
ータは２０psecと倍々で進歩してきているが、配線での
遅延は配線長の増加とあいまって、線型でしか減少して
おらず、例えばトップデータで５００psecといった遅延
時間が現状である。Although the delay speed of the element itself has doubled to 20 psec for top data, the delay in wiring has decreased only in a linear form together with the increase in wiring length. For example, the top data is 500 psec. The current delay time is as follows.
【０００７】本発明はこのような問題に鑑みてなされた
ものであって、配線間の寄生容量を減少させることがで
きる半導体装置の製造方法を提供することを目的とす
る。The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing parasitic capacitance between wirings.
【０００８】[0008]
【課題を解決するための手段】上記した課題は、少なく
ともC60F60とSiO2の複合材料からなる層間絶縁膜を形成
する工程を含むことを特徴とする半導体装置の製造方法
により達成する。The above-mentioned problems can be achieved by a method of manufacturing a semiconductor device including a step of forming an interlayer insulating film made of at least a composite material of C 60 F 60 and SiO 2 .
【０００９】または、C60F60を水ＴＥＯＳに混合した絶
縁材を基板の上に塗布した後に、該絶縁材を加熱してC
60F60とSiO2の複合材料からなる層間絶縁膜を形成する
工程を含むことを特徴とする半導体装置の製造方法によ
り達成する。Alternatively, after coating an insulating material in which C 60 F 60 is mixed with water TEOS on a substrate, the insulating material is heated to C
It is achieved by a method for manufacturing a semiconductor device, which includes a step of forming an interlayer insulating film made of a composite material of 60 F 60 and SiO 2 .
【００１０】または、C60F60とＴＥＯＳを含む原料ガス
を反応炉内に導入し、気相成長法によりC60F60とSiO2の
複合材料からなる層間絶縁膜を形成する工程を含むこと
を特徴とする半導体装置の製造方法により達成する。Alternatively, a step of introducing a source gas containing C 60 F 60 and TEOS into a reaction furnace and forming an interlayer insulating film made of a composite material of C 60 F 60 and SiO 2 by a vapor phase growth method is included. Is achieved by a method for manufacturing a semiconductor device.
【００１１】[0011]
【作 用】本発明によれば、C60F60をSiO2に混合させて
層間絶縁膜を形成している。そのC60F60の比誘電率はSi
O2よりも小さく約１．５であり、これにより層間絶縁膜
の上下に形成される配線層間の寄生容量が低減する。[Operation] According to the present invention, C 60 F 60 is mixed with SiO 2 to form an interlayer insulating film. The relative permittivity of C 60 F 60 is Si
It is smaller than O 2 and is about 1.5, which reduces the parasitic capacitance between wiring layers formed above and below the interlayer insulating film.
【００１２】この場合、C60F60の粒子は図２に示すよう
な球体をして安定であるために、C6 0F60を水ＴＥＯＳに
混ぜてSiO2とC60F60の複合膜を形成することが容易であ
る。また、SiO2を気相成長させる際にC60F60を混合する
ことができる。[0012] In this case, C 60 for the particles of F 60 is stable with a sphere as shown in FIG. 2, the composite film of SiO 2 and C 60 F 60 mix C 6 0 F 60 in water TEOS Is easy to form. Further, C 60 F 60 can be mixed when vapor-depositing SiO 2 .
【００１３】しかも、この混合膜の耐熱温度を５００℃
程度にすることが可能であり、配線用にアルミニウムを
形成する際の基板温度によって損傷を受けない。Moreover, the heat resistant temperature of this mixed film is 500 ° C.
However, it is not damaged by the substrate temperature when forming aluminum for wiring.
【００１４】[0014]
【実施例】そこで、以下に本発明の実施例を図面に基づ
いて説明する。図１は、本発明の一実施例を示す装置の
断面図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an apparatus showing an embodiment of the present invention.
【００１５】図において符号１は、シリコンよりなる半
導体基板で、その上層部にはＰウェル２、Ｎウェル３が
設けられ、そこにはｎ型ＭＯＳＦＥＴ４、ｐ型ＭＯＳＦ
ＥＴ５がそれぞれ形成され、SiO2膜６、ＰＳＧ膜７によ
り覆われている。In the figure, reference numeral 1 is a semiconductor substrate made of silicon, and P well 2 and N well 3 are provided in the upper layer thereof, and an n-type MOSFET 4 and a p-type MOSF are provided there.
ET5 is formed and covered with the SiO 2 film 6 and the PSG film 7.
【００１６】８ａ，８ｂは、ＰＳＧ膜７の上に形成され
た下層の配線層で、SiO2膜６及びＰＳＧ膜７のコンタク
トホール９ａ，９ｂを通してＭＯＳＦＥＴ４，５のソー
ス／ドレイン層４ａ，５ａに接続されている。また、下
層の配線層８ａ，８ｂを含む全体には薄いSiO2膜１０が
形成され、また、下層の配線層８ａ，８ｂの周囲にある
凹凸は、C60F60とSiO2の複合膜１１によって平坦化され
ている。Reference numerals 8a and 8b are lower wiring layers formed on the PSG film 7, and are formed on the source / drain layers 4a and 5a of the MOSFETs 4 and 5 through the contact holes 9a and 9b of the SiO 2 film 6 and the PSG film 7. It is connected. In addition, a thin SiO 2 film 10 is formed over the entire lower wiring layers 8a and 8b, and the unevenness around the lower wiring layers 8a and 8b is a composite film 11 of C 60 F 60 and SiO 2. Have been flattened by.
【００１７】さらに、下層の配線層８ａ，８ｂと複合膜
１１の上には上層の配線層１２が形成され、この上層の
配線層１２は、コンタクトホール１３を通して下層の配
線層８ａの一つに接続し、かつ、別の下層配線層８ｂの
上に延在している。Further, an upper wiring layer 12 is formed on the lower wiring layers 8a and 8b and the composite film 11, and the upper wiring layer 12 is formed as one of the lower wiring layers 8a through the contact holes 13. They are connected to each other and extend on another lower wiring layer 8b.
【００１８】なお、図中符号１４は、上層の配線層１２
を覆うＰＳＧ膜、１５は、半導体基板１の表面に選択酸
化法により形成された素子分離用酸化膜を示している。
以上のような実施例において、上層の配線層１２とこれ
に接続しない下層の配線層８ｂとの間には、C60F60とSi
O2の複合膜１１が介在している。この複合膜１１の比誘
電率はSiO2よりも小さく、これにより配線層間の寄生容
量が低減する。In the figure, reference numeral 14 is an upper wiring layer 12.
A PSG film 15 for covering is a device isolation oxide film formed on the surface of the semiconductor substrate 1 by a selective oxidation method.
In the above-described embodiment, C 60 F 60 and Si are provided between the upper wiring layer 12 and the lower wiring layer 8b not connected thereto.
The composite film 11 of O 2 is interposed. The relative permittivity of the composite film 11 is smaller than that of SiO 2 , so that the parasitic capacitance between wiring layers is reduced.
【００１９】しかも、その耐熱温度は４００℃以上であ
り、上層の配線層１１をアルミニウムによって形成する
場合にも、損傷を受けない。ところで、フッ素（Ｆ）を
含む材料としてポリテトラフルオロエチレン（商品名；
テフロン）があるが、SiO2と混合し難い上に、その耐熱
性が２００℃以下と低いので、その後の成膜の際の基板
温度による損傷が大きい。Moreover, the heat-resistant temperature is 400 ° C. or higher, and is not damaged even when the upper wiring layer 11 is formed of aluminum. By the way, as a material containing fluorine (F), polytetrafluoroethylene (trade name;
Teflon), but it is difficult to mix with SiO 2 and its heat resistance is low at 200 ° C. or lower, so that it is largely damaged by the substrate temperature during the subsequent film formation.
【００２０】SiO2、ポリテトラフルオロエチレン、C60F
60、C60F60・SiO2複合膜のそれぞれの比誘電率と耐熱温
度は、表１のようになる。複合膜中のSiO2の含有率は約
40％である。SiO 2 , polytetrafluoroethylene, C 60 F
Table 1 shows the relative permittivity and heat resistance temperature of 60 and C 60 F 60 · SiO 2 composite films. The content of SiO 2 in the composite film is about
40%.
【００２１】[0021]
【表１】 複合膜中のC60F60の分子は図２に示すような球体をして
安定であるために、SiO2との混合が容易で、C60F60を水
ＴＥＯＳに混入させたり、SiO2を気相成長する際にC60F
60を混合させることができる。[Table 1] Since the molecules of C 60 F 60 in the composite film are spherical and stable as shown in Fig. 2, it is easy to mix with SiO 2, and C 60 F 60 can be mixed with water TEOS or SiO 2 C 60 F during vapor growth
60 can be mixed.
【００２２】そこで、次に、C60F60をSiO2に混合させる
方法を説明する。第１の方法は、図３(a) に示すよう
に、水ＴＯＥＳにC60F60を混ぜ合わせて、これを基板１
に滴下してスピンコーティングした後に、約６５０℃の
加熱処理を加えるものであり、これにより、C60F60とSi
O2の複合膜が形成される。Therefore, a method of mixing C 60 F 60 with SiO 2 will be described next. The first method is to mix water TOES with C 60 F 60 as shown in FIG.
Was added dropwise to the after spin-coating, which heat treatment is performed for about 650 ° C., thereby, C 60 F 60 and Si
A composite film of O 2 is formed.
【００２３】第２の方法は、その複合膜をＣＶＤ法によ
り形成するものである。この場合、C60F60を３００℃の
温度により加熱蒸発し、これを図３(b) に示す反応炉３
１内に導入するとともに、ＴＥＯＳをAr等のキャリアガ
スによって同じ反応炉３１内に供給する。そして、反応
炉３１内に設置された基板１をヒータ３２により４００
℃程度に加熱し、その上面に、減圧ＣＶＤ法によりC60F
60とSiO2の複合膜を形成する。The second method is to form the composite film by the CVD method. In this case, C 60 F 60 is heated and evaporated at a temperature of 300 ° C., and this is heated in the reactor 3 shown in FIG. 3 (b).
While being introduced into the reactor 1, TEOS is supplied into the same reaction furnace 31 by a carrier gas such as Ar. Then, the substrate 1 installed in the reaction furnace 31 is heated to 400 by the heater 32.
After heating to about ℃, apply C 60 F on the upper surface by low pressure CVD method.
A composite film of 60 and SiO 2 is formed.
【００２４】なお、図３(b) 中符号３３は、反応炉３１
の排気経路３４中に接続された開閉弁、３５は、開閉弁
３３よりも外方に設けられたブースタポンプ、３６はロ
ータリーポンプ、３７は真空計を示している。Reference numeral 33 in FIG. 3 (b) is the reaction furnace 31.
An on-off valve connected to the exhaust path 34 of the above, 35 is a booster pump provided outside the on-off valve 33, 36 is a rotary pump, and 37 is a vacuum gauge.
【００２５】次に、C60F60の製造方法の一例を説明す
る。図４は、C60F60の製造装置を示す断面図でで、グラ
ファイト棒４１を反応炉４２中に入れて、これに２本の
水冷電極４３，４４を接続して電圧を印加する。また、
別の管状の水冷電極４５を２つの水冷電極４３，４４の
間に入れ、その先端をグラファイト棒４１に接触させず
に近づけ、グラファイト棒４１との間にアーク放電を発
生させるように電圧を印加する。Next, an example of a method for producing C 60 F 60 will be described. FIG. 4 is a cross-sectional view showing an apparatus for producing C 60 F 60 , in which a graphite rod 41 is put in a reaction furnace 42, two water cooling electrodes 43, 44 are connected to this, and a voltage is applied. Also,
Another tubular water-cooled electrode 45 is inserted between the two water-cooled electrodes 43 and 44, the tip of the water-cooled electrode 43 is brought close to the graphite rod 41 without coming into contact with the graphite rod 41, and a voltage is applied so as to generate an arc discharge with the graphite rod 41. To do.
【００２６】また、グラファイト棒４１には水冷銅板４
６が接近して配置されており、これによりグラファイト
棒４１の表面に付着した物が凝縮するようにしてる。そ
して、この装置を使用して、まず、中央の水冷電極４５
の先端からガスを導入し、酸素を５％含んだ不揮発性ガ
スの中でシクロフロルシクロヘキサン(C6H6F 6)をアーク
放電により燃やし、グラファイト棒４１に付着したスス
を回収する。このススを液体ガスクロマト法により分離
してC60F60を抽出する。The graphite rod 41 has a water-cooled copper plate 4
6 are placed close to each other, which results in graphite
The substance attached to the surface of the rod 41 is condensed. So
Then, using this device, first, the central water-cooled electrode 45
Gas is introduced from the tip of the non-volatile gas containing 5% oxygen.
Cyclofluorocyclohexane (C6H6F 6) The arc
Soot that burns due to electric discharge and adheres to the graphite rod 41
Collect. This soot is separated by liquid gas chromatography
Then C60F60To extract.
【００２７】[0027]
【発明の効果】以上述べたように本発明によれば、比誘
電率がSiO2よりも小さいC60F60をSiO2に混合させて層間
絶縁膜を形成しているので、その上下に形成される配線
層間の寄生容量を低減することができる。According to the present invention as described above, according to the present invention, relative since dielectric constant is an interlayer insulating film by mixing a small C 60 F 60 than SiO 2 in SiO 2, formed on the upper and lower It is possible to reduce the parasitic capacitance between the wiring layers.
【００２８】この場合、C60F60の分子は球体をして安定
であるために、C60F60を水ＴＥＯＳに混ぜてSiO2とC60F
60の複合膜を形成することが容易である。また、SiO2を
気相成長させる際にC60F60を混合することができる。In this case, since the molecules of C 60 F 60 are spherical and stable, C 60 F 60 is mixed with water TEOS and SiO 2 and C 60 F 60 are mixed.
It is easy to form 60 composite films. Further, C 60 F 60 can be mixed when vapor-depositing SiO 2 .
【００２９】しかも、この複合膜の耐熱温度を５００℃
程度にすることが可能であり、配線用にアルミニウムを
形成する際の基板温度によって損傷を防止できる。Moreover, the heat resistant temperature of this composite film is 500.degree.
The damage can be prevented by the substrate temperature when forming aluminum for wiring.
【図１】本発明の一実施例を示す装置の断面図である。FIG. 1 is a sectional view of an apparatus showing an embodiment of the present invention.
【図２】本発明に用いるC60F60の分子構造図である。FIG. 2 is a molecular structure diagram of C 60 F 60 used in the present invention.
【図３】本発明に用いるC60F60・SiO2複合膜の形成方法
の一例を示す構成図である。FIG. 3 is a configuration diagram showing an example of a method for forming a C 60 F 60 · SiO 2 composite film used in the present invention.
【図４】本発明に用いるC60F60の製造装置の一例を示す
断面図である。FIG. 4 is a sectional view showing an example of a C 60 F 60 manufacturing apparatus used in the present invention.
１ 半導体基板 ２ Ｐウェル ３ Ｎウェル ４ ｐ型ＭＯＳＦＥＴ ５ ｎ型ＭＯＳＦＥＴ ６ SiO2膜 ７ ＰＳＧ膜 ８ａ、８ｂ、１２ 配線層 ９ａ、９ｂ コンタクトホール １０ SiO2膜 １１ 複合膜1 semiconductor substrate 2 P well 3 N well 4 p-type MOSFET 5 n-type MOSFET 6 SiO 2 film 7 PSG film 8a, 8b, 12 wiring layers 9a, 9b contact hole 10 SiO 2 film 11 composite film
Claims (3)
る層間絶縁膜を形成する工程を含むことを特徴とする半
導体装置の製造方法。1. A method of manufacturing a semiconductor device, comprising a step of forming an interlayer insulating film made of a composite material of at least C 60 F 60 and SiO 2 .
板の上に塗布した後に、該絶縁材を加熱してC60F60とSi
O2の複合材料からなる層間絶縁膜を形成する工程を含む
ことを特徴とする請求項１記載の半導体装置の製造方
法。2. An insulating material in which C 60 F 60 is mixed with water TEOS is applied on a substrate and then the insulating material is heated to produce C 60 F 60 and Si.
The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming an interlayer insulating film made of a composite material of O 2 .
内に導入し、気相成長法によりC60F60とSiO2の複合材料
からなる層間絶縁膜を形成する工程を含むことを特徴と
する請求項１記載の半導体装置の製造方法。3. A step of introducing a source gas containing C 60 F 60 and TEOS into a reaction furnace and forming an interlayer insulating film made of a composite material of C 60 F 60 and SiO 2 by a vapor phase growth method. The method for manufacturing a semiconductor device according to claim 1, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8874992A JPH05291412A (en) | 1992-04-09 | 1992-04-09 | Production of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8874992A JPH05291412A (en) | 1992-04-09 | 1992-04-09 | Production of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05291412A true JPH05291412A (en) | 1993-11-05 |
Family
ID=13951557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8874992A Withdrawn JPH05291412A (en) | 1992-04-09 | 1992-04-09 | Production of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05291412A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744399A (en) * | 1995-11-13 | 1998-04-28 | Lsi Logic Corporation | Process for forming low dielectric constant layers using fullerenes |
| EP1473770A1 (en) * | 2002-12-18 | 2004-11-03 | Texas Instruments Incorporated | Low dielectric constant interconnect insulator having fullerene additive |
-
1992
- 1992-04-09 JP JP8874992A patent/JPH05291412A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744399A (en) * | 1995-11-13 | 1998-04-28 | Lsi Logic Corporation | Process for forming low dielectric constant layers using fullerenes |
| EP1473770A1 (en) * | 2002-12-18 | 2004-11-03 | Texas Instruments Incorporated | Low dielectric constant interconnect insulator having fullerene additive |
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