JPH0528752Y2 - - Google Patents
Info
- Publication number
- JPH0528752Y2 JPH0528752Y2 JP12274587U JP12274587U JPH0528752Y2 JP H0528752 Y2 JPH0528752 Y2 JP H0528752Y2 JP 12274587 U JP12274587 U JP 12274587U JP 12274587 U JP12274587 U JP 12274587U JP H0528752 Y2 JPH0528752 Y2 JP H0528752Y2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- thickness
- electronic component
- terminal
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000002844 melting Methods 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 43
- 238000007747 plating Methods 0.000 description 23
- 239000011347 resin Substances 0.000 description 18
- 229920005989 resin Polymers 0.000 description 18
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 7
- 239000004332 silver Substances 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は、小さな直方体、すなわちチツプ状の
外装体の側面からリード端子が引き出され、外装
体に沿つて折り曲げられてなる構造に関し、特に
外装体の底面とほぼ同一面にくるように整形され
て、配線基板上の導電パターン面に直接はんだ等
で固着されるタイプの例えば、固体電解コンデン
サなどのチツプ型電子部品に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a structure in which a lead terminal is pulled out from the side of a small rectangular parallelepiped, that is, a chip-shaped exterior body, and is bent along the exterior body. The present invention relates to a chip-type electronic component, such as a solid electrolytic capacitor, which is shaped so that it is almost flush with the bottom surface of a body and is directly fixed to a conductive pattern surface on a wiring board by soldering or the like.
従来、この種のチツプ型電子部品は第２図ａ，
ｂの斜視図および断面図に示すように、銅系、鉄
系等の金属条材の全表面にはんだ付性を向上させ
るため電気はんだめつきを施した後所定の形状寸
法に加工したリードフレームを形成し、このリー
ドフレームに素子１を固定し、外装樹脂２にて外
装を施し、外装樹脂２より突出したリードフレー
ムを所定寸法に切断し、配線基板に実装しやすい
ように、外装樹脂２に沿つて折り曲げる端子３を
形成し、チツプ型電子部品としていた。
Conventionally, this type of chip-type electronic component is shown in Fig. 2a,
As shown in the perspective view and cross-sectional view of b, the lead is processed into a predetermined shape and size after applying electric solder to the entire surface of a copper-based, iron-based, etc. metal strip to improve solderability. A frame is formed, the element 1 is fixed to this lead frame, the element 1 is covered with an exterior resin 2, the lead frame protruding from the exterior resin 2 is cut to a predetermined size, and the exterior resin is A terminal 3 was formed to be bent along the line 2, and a chip-type electronic component was formed.
上述した従来のチツプ型電子部品は、樹脂外装
内部のリード端子面３ａにも外部端子と同一のめ
つき厚のはんだが施されているため、配線基板に
チツプ型電子部品をはんだペースト等を用い、は
んだめつきの融点よりも高い温度にて実装を行う
と、リード端子面３ａのはんだめつきが溶融し、
かつ外装樹脂２によつて素子１及び素子周辺に残
溜した空気が加熱され膨張し、リード端子面３ａ
と外装樹脂２の界面を通して溶融したはんだを押
し出しながら外装樹脂２の外部へ突出し、外装樹
脂とリード端子の付根３ｃに球状のはんだ玉４を
形成する。このはんだ玉４は振動、衝撃等で配線
基板上に落下し、配線基板の電気回路上を動くた
め回路間の短絡を生じ、電気回路に異常信号を発
生させる等、信頼性に与える影響は甚大である。
一方リード端子面３ａの裏面に当るシード端子面
３ｂは導電性接着剤等で素子１を固定するが、め
つき面のはんだが溶解すると導電性接着剤の銀中
へはんだ中の錫が拡散し、はんだめつきの層部は
空隙となり素子とリード端子面３ｂの接続が不安
定となる。これを防止するため第３図ａ，ｂの斜
視図および断面図に示すように銀等の部分メツキ
５ｂを施す工法を行うのが一般であるがリードフ
レーム材の価格が上るため特殊の場合を除き使用
されていない。
In the conventional chip-type electronic component described above, the lead terminal surface 3a inside the resin exterior is also plated with solder with the same plating thickness as the external terminal. If mounting is carried out at a temperature higher than the melting point of the solder, the solder on the lead terminal surface 3a will melt,
In addition, the air remaining in the element 1 and around the element is heated and expanded by the exterior resin 2, and the lead terminal surface 3a
The molten solder is pushed out through the interface between the exterior resin 2 and the exterior resin 2, and protrudes to the outside of the exterior resin 2, forming a spherical solder ball 4 at the base 3c of the exterior resin and the lead terminal. This solder ball 4 falls onto the wiring board due to vibration, shock, etc., and moves on the electrical circuit of the wiring board, causing a short circuit between the circuits and generating an abnormal signal in the electrical circuit, which has a huge impact on reliability. It is.
On the other hand, the seed terminal surface 3b, which is the back surface of the lead terminal surface 3a, fixes the element 1 with a conductive adhesive or the like, but when the solder on the plating surface melts, the tin in the solder diffuses into the silver of the conductive adhesive. , the soldered layer portions create voids, making the connection between the element and the lead terminal surface 3b unstable. To prevent this, it is common practice to apply partial plating 5b of silver or the like as shown in the perspective view and cross-sectional view of Figures 3a and 3b, but since the price of the lead frame material increases, special cases are required. Not used except.
上述した従来のチツプ型電子部品に対し、本考
案はコンデンサ素子の接合される端子面のはんだ
めつき厚を2μm以下と薄くかつ実装に必要な端子
部のはんだめつき厚を4μm以上と厚くする、即ち
外装樹脂内のはんだめつきを薄くし外装樹脂外部
の端子部のはんだめつきを厚くする二重構造のめ
つき端子を用いる相違点を有する。 In contrast to the conventional chip-type electronic components described above, the present invention reduces the solder thickness of the terminal surface to which the capacitor element is bonded to 2 μm or less, and the solder thickness of the terminal portion necessary for mounting to 4 μm or more. The difference is that a double-layer plated terminal is used, in which the solder is thicker, that is, the solder inside the outer resin is thinner, and the solder on the terminal outside the outer resin is thicker.
上記問題点に対し本考案では、はんだ、錫等の
低融点金属を金属板の表面に施してなる、リード
端子を有する電子部品素子を絶縁体で外装を施し
た電子部品において、電子部品素子と接合し、か
つ外装の内部に位置するリード端子の低融点金属
の厚さを2μm以下とし、かつ外装の外部の少なく
とも一部のリード端子表面の低融点金属の厚さを
4μm以上とする、すなわち厚さに段差をもつ端子
構造を有するチツプ型電子部品を供給することに
ある。
To solve the above problems, the present invention provides an electronic component in which an electronic component element having a lead terminal is coated with an insulator and is made by applying a low melting point metal such as solder or tin to the surface of a metal plate. The thickness of the low melting point metal of the lead terminals that are bonded and located inside the sheath shall be 2 μm or less, and the thickness of the low melting point metal on the surface of at least part of the lead terminals outside the sheath shall be 2 μm or less.
The purpose of the present invention is to provide a chip-type electronic component having a terminal structure with a thickness of 4 μm or more, that is, a step in thickness.
次に本考案を実施例による説明する。 Next, the present invention will be explained using examples.
第１図ａは本考案の一実施例の破断面の斜視図
であり、第１図ｂは本考案の第１図ａの断面図で
ある。 FIG. 1a is a perspective cutaway view of one embodiment of the present invention, and FIG. 1b is a cross-sectional view of FIG. 1a of the present invention.
第１図ａにおいて、固体タンタル電解コンデン
サなどのコンデンサ素子１（以下素子と省略す
る）をはんだめつきが施されたフレーム状の金属
端子３に、陽極側は溶接にて接合し、陰極側は銀
ペーストなどの導電性接着剤にて接合するが、こ
のフレーム状リード端子の素子接合部及びモール
ド外装に入る大部分の端子表面のメツキを2μm以
下のSn85％以上含有する組成のはんだめつきを
施しかつモールド外装部の端子表面のメツキを
4μm以上のはんだ組成のめつきを施す、すなわち
一体となつたフレーム状端子に段差めつきを施し
たものを用いる。 In Fig. 1a, a capacitor element 1 (hereinafter abbreviated as element) such as a solid tantalum electrolytic capacitor is connected to a frame-shaped metal terminal 3 with soldering, the anode side is joined by welding, and the cathode side is welded. are bonded using a conductive adhesive such as silver paste, but the plating on the element joints of this frame-shaped lead terminal and the surface of most of the terminals that go into the mold exterior is soldered with a composition of 2 μm or less and containing 85% or more Sn. The surface of the terminal on the mold exterior is plated.
Apply plating with a solder composition of 4 μm or more, that is, use a step plating applied to an integrated frame-shaped terminal.
以上により接合の完了したフレーム体をトラン
スフアーモールド成形により外装樹脂２に封止
し、素子１に接合したリード端子３を外装樹脂２
の側面から外部に引き出し、側面に沿つて下方に
折り曲げ、さらに実装ができるように外装樹脂２
の底面に沿つて折り曲げる。 The frame body that has been joined as described above is sealed in the exterior resin 2 by transfer molding, and the lead terminal 3 joined to the element 1 is sealed in the exterior resin 2.
Exterior resin 2
Fold it along the bottom of the
以上説明したように本考案は、はんだめつき等
の低融点金属を電気めつき等によりリード端子３
の表面に形成し素子１を接合後モールド等の外装
樹脂２を施したチツプ型電子部品において、リー
ド端子３の素子接続部及びモールド外装に入る大
部分の端子表面のメツキを2μm以下のSn85％以
上含有する組成のはんだめつきを施し、かつモー
ルド外装部の端子表面に4μm以上のはんだめつき
を施した物を用いることにより、実装に伴うモー
ルドとリード端子付根４にはんだ玉４の発生を防
止できかつ確実なはんだ付が可能である。
As explained above, in the present invention, the lead terminal 3 is formed by electroplating a low melting point metal such as solder.
In chip-type electronic components that are formed on the surface of a mold and are coated with an exterior resin 2 such as a mold after the element 1 is bonded, the plating on the element connection part of the lead terminal 3 and the surface of most of the terminals that enter the mold exterior is made of 85% Sn of 2 μm or less. By using a solder plate with a composition containing the above and a solder plate with a thickness of 4 μm or more on the terminal surface of the mold exterior, it is possible to prevent solder balls 4 from forming on the mold and lead terminal base 4 during mounting. This can be prevented and reliable soldering can be performed.
第４図は、はんだめつき厚とはんだ玉の関係を
示す実験結果である。 FIG. 4 shows experimental results showing the relationship between solder plating thickness and solder balls.
はんだめつき厚が厚くなると、はんだ玉の発生
が著しくなることを示す。 The graph shows that as the solder plating thickness increases, the occurrence of solder balls becomes more pronounced.
はんだめつき厚を2μm以下とするこてではんだ
玉の発生を押える事が可能である。 It is possible to suppress the generation of solder balls by using a soldering iron with a solder plating thickness of 2 μm or less.
第５図は素子とリード端子を接続するために導
電性接着剤（銀系ペースト）５を用いた場合の、
はんだめつき厚とはんだめつきの錫の銀中への拡
散が生じるはんだ喰れの発生率についての実験結
果である。 Figure 5 shows the case where a conductive adhesive (silver paste) 5 is used to connect the element and the lead terminals.
These are experimental results regarding the thickness of solder plating and the incidence of solder bite caused by diffusion of tin into silver in solder plating.
はんだめつき厚が厚くなると喰れが著しくなる
事を示しており、この接合ではめつき厚を3μm以
下とする必要がある。即ちはんだ玉及びはんだ喰
れから素子との接合面でのめつき厚は2μm以下と
する必要がある。 This indicates that the thicker the solder plating, the more noticeable the corrosion, and the plating thickness must be 3 μm or less for this bonding. That is, the thickness of the plating at the joint surface with the element must be 2 μm or less from solder balls and solder bite.
第６図は、はんだめつき厚と部品実装時のはん
だぬれ性について、はんだぬれ性のゼロクロス時
間（JIS−Ｃ−0053はんだ付試験方法の図２中の
t0からＡ点までに要する時間）をグラフ化した結
果である、この結果より外部端子のめつき厚は４
〜5μm以上とする必要がある。 Figure 6 shows the zero cross time of solderability (JIS-C-0053 soldering test method in Figure 2) regarding the solder thickness and solderability during component mounting.
From this result , the plating thickness of the external terminal is 4.
It needs to be ~5 μm or more.
以上よりモールド外装内部のめつき厚を2μm以
下としモールド外装より突出した端子部のめつき
厚を４〜5μm以上とすることで、はんだ玉の発
生、はんだ喰れによる接続不安定及び実装性の問
題を解決する事が出来る。 From the above, by setting the plating thickness inside the mold exterior to 2 μm or less and the plating thickness at the terminal portion protruding from the mold exterior to 4 to 5 μm or more, it is possible to prevent the generation of solder balls, unstable connections due to solder erosion, and mounting performance. Can solve problems.
第１図ａおよびｂはそれぞれ本考案の一実施例
を示す破断斜視図及び断面図であり樹脂外装２の
内部のはんだめつき端子３ａ，３ｂを外装樹脂よ
り突出しているリード端子面のめつき厚さと段差
を付けた図である。第２図ａおよびｂは従来品の
斜視図および断面図、第３図ａおよびｂは端子面
３ｂの表面よりはんだめつきを取り除き銀メツキ
を施した物の破断斜視図および断面図、第４図は
本考案に関する、はんだめつき厚とはんだ玉発生
率の関係を示すグラフである。第５図は本考案に
関する、はんだめつき厚と接合面のはんだ喰れ発
生率の関係を示すグラフである。第６図は本考案
に関する、はんだめつき厚とはんだぬれ性の関係
を示すグラフである。
１……コンデンサ素子、２……外装樹脂、３…
…端子、３ａ……上部端子面、３ｂ……素子との
接合する端子面、４……はんだ玉、５……導電性
接着剤、５ｂ……銀メツキ。
Figures 1a and 1b are a cut away perspective view and a cross-sectional view, respectively, showing an embodiment of the present invention, in which solder-plated terminals 3a and 3b inside the resin sheath 2 are connected to the lead terminal surface protruding from the sheath resin. It is a diagram showing the thickness and level difference. Figures 2a and b are a perspective view and a sectional view of a conventional product, Figures 3a and b are a broken perspective view and a sectional view of a product in which solder has been removed from the surface of the terminal surface 3b and silver plating has been applied. FIG. 4 is a graph showing the relationship between solder plating thickness and solder ball generation rate according to the present invention. FIG. 5 is a graph showing the relationship between the solder plating thickness and the incidence of solder erosion on the joint surface, according to the present invention. FIG. 6 is a graph showing the relationship between solder plating thickness and solder wettability regarding the present invention. 1...Capacitor element, 2...Exterior resin, 3...
...Terminal, 3a... Upper terminal surface, 3b... Terminal surface to be joined to the element, 4... Solder ball, 5... Conductive adhesive, 5b... Silver plating.
Claims (1)
ド端子を有する電子部品素子を絶縁体で外装を施
した電子部品において、電子部品素子と接合し、
かつ外装の内部に位置するリード端子の低融点金
属の厚さを2μm以下としかつ外装の外部のリード
端子表面の低融点金属の厚さを4μm以上とする、
厚みに段差をもつ端子構造を有するチツプ型電子
部品。 In an electronic component in which an electronic component element having a lead terminal formed by applying a low melting point metal to the surface of a metal plate is sheathed with an insulator, the electronic component element is joined to the electronic component element,
and the thickness of the low melting point metal of the lead terminal located inside the sheath is 2 μm or less, and the thickness of the low melting point metal on the surface of the lead terminal outside the sheath is 4 μm or more,
A chip-type electronic component that has a terminal structure with steps in thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12274587U JPH0528752Y2 (en) | 1987-08-10 | 1987-08-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12274587U JPH0528752Y2 (en) | 1987-08-10 | 1987-08-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6426826U JPS6426826U (en) | 1989-02-15 |
| JPH0528752Y2 true JPH0528752Y2 (en) | 1993-07-23 |
Family
ID=31370961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12274587U Expired - Lifetime JPH0528752Y2 (en) | 1987-08-10 | 1987-08-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0528752Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2927196B2 (en) * | 1994-11-25 | 1999-07-28 | 日本電気株式会社 | Chip-type electronic component and method of manufacturing the same |
| WO2004093353A1 (en) | 2003-04-15 | 2004-10-28 | Fujitsu Limited | Optical splitter |
-
1987
- 1987-08-10 JP JP12274587U patent/JPH0528752Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6426826U (en) | 1989-02-15 |
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