JPH05275611A - Multichip module - Google Patents

Multichip module

Info

Publication number
JPH05275611A
JPH05275611A JP4074085A JP7408592A JPH05275611A JP H05275611 A JPH05275611 A JP H05275611A JP 4074085 A JP4074085 A JP 4074085A JP 7408592 A JP7408592 A JP 7408592A JP H05275611 A JPH05275611 A JP H05275611A
Authority
JP
Japan
Prior art keywords
semiconductor chips
chip module
insulating substrate
electrically insulating
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4074085A
Other languages
Japanese (ja)
Other versions
JP2823029B2 (en
Inventor
Hiromori Tobase
浩守 鳥羽瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4074085A priority Critical patent/JP2823029B2/en
Publication of JPH05275611A publication Critical patent/JPH05275611A/en
Application granted granted Critical
Publication of JP2823029B2 publication Critical patent/JP2823029B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve mounting density, to shorten the line length of an electric wiring, to cut down the period of propagation of a signal, and to accomplish high-speed operation of a multichip. CONSTITUTION:In a multichip module which is formed by housing a plurality of semiconductor chips 4 and electrically connected to an electrically insulated substrate 1 having prescribed electric wiring pattern 2, a multistage-formed recessed part is formed on the electrically insulted a substrate 1, and each semiconductor chip 4 are housed in the recessed part in such a manner that they are separated with each other in vertical direction.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
複数の半導体チップが、収納されるマルチチップモジュ
ールの構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a multi-chip module in which a plurality of semiconductor chips are housed.

【０００２】[0002]

【従来の技術】従来のマルチチップモジュールは第５図
の断面図に示すように、複数の半導体チップ４が電気配
線パターン（図示せず）を有する電気絶縁基板の同一面
上に収納されており、前記電気絶縁基板１と前記半導体
チップ４とは、金属細線１０によって電気的に接続さ
れ、前記電気絶縁基板１の電気配線パターンは、外部リ
ード６によって電気的に接続されている。2. Description of the Related Art In a conventional multi-chip module, as shown in the sectional view of FIG. 5, a plurality of semiconductor chips 4 are housed on the same surface of an electrically insulating substrate having an electrical wiring pattern (not shown). The electrically insulating substrate 1 and the semiconductor chip 4 are electrically connected by a thin metal wire 10, and the electrical wiring pattern of the electrically insulating substrate 1 is electrically connected by an external lead 6.

【０００３】この従来構造で例えば、ＣＰＵ（Ｃｅｎｔ
ｒａｌ Ｐｒｏｃｅｓｓｉｎｇ Ｕｎｉｔ）１個, ＦＰ
Ｕ（Ｆｌｏｔｉｎｇ Ｐｒｏｃｅｓｓｉｎｇ Ｕｎｉ
ｔ）１個, ＢＩＵ（Ｂｕｔｈ Ｉｎｔｅｒｆａｃｅ Ｕ
ｎｉｔ）１個, キャッシュメモリ６個の合計９個の半導
体チップで構成されるマルチチップモジュールであれ
ば、電気絶縁基板の大きさは、約８５ｍｍ角となる。In this conventional structure, for example, a CPU (Cent)
ral Processing Unit) 1 piece, FP
U (Floating Processing Uni)
t) 1 unit, BIU (Buth Interface U)
If the multi-chip module is composed of a total of nine semiconductor chips, one nit and six cache memories, the size of the electrically insulating substrate is about 85 mm square.

【０００４】[0004]

【発明が解決しようとする課題】ところで、この従来の
マルチチップモジュールでは、半導体チップ４が電気絶
縁基板１の同一面のみに収納されているため、半導体チ
ップの収納数が増えると電気絶縁基板の大きさも大きく
ならざるを得ない。従って電気配線の線路長が長くな
る。By the way, in this conventional multi-chip module, the semiconductor chips 4 are housed only on the same surface of the electrically insulating substrate 1. Therefore, if the number of semiconductor chips accommodated increases, There is no choice but to increase the size. Therefore, the line length of the electric wiring becomes long.

【０００５】このように、電気配線の線路長が長くなる
と、配線の持つキャパシタンスが大きくなり、信号の伝
播遅延時間が大きくなる。このため、マルチチップモジ
ュールを高速動作させようとした場合、１つのクロック
の時間内に信号が戻らなくなり、マルチチップモジュー
ルが高速動作しなくなるといった問題があった。As described above, when the line length of the electric wiring becomes long, the capacitance of the wiring becomes large and the signal propagation delay time becomes long. Therefore, when trying to operate the multi-chip module at high speed, there is a problem that the signal does not return within the time of one clock and the multi-chip module does not operate at high speed.

【０００６】この問題は、非常に大きな問題であり、高
速動作すればするほど信号の処理スピードが上がるのに
対し、高速動作ができないという問題があった。This problem is very serious, and the higher the speed of operation, the faster the signal processing speed, but there is the problem that high speed operation is not possible.

【０００７】この発明はこのような従来技術の課題に鑑
みて提案されたもので、フリップチップ接続等のマルチ
チップモジュールにおいて、実装密度の向上および電気
配線の線路長を短くし、上記従来技術の欠点を除去する
ことを目的とする。The present invention has been proposed in view of the problems of the prior art described above. In a multi-chip module such as a flip chip connection, the mounting density is improved and the line length of electric wiring is shortened to achieve the above-mentioned prior art. The purpose is to eliminate defects.

【０００８】[0008]

【課題を解決するための手段】本発明によれば、複数の
半導体チップを収納し、前記半導体チップがバンプによ
り所定の電気配線パターンを有する電気絶縁基板に電気
的に接続されてなるマルチチップモジュールにおいて、
前記電気絶縁基板には多段式凹部が形成されており、か
つ、前記各半導体チップが該凹部に上下方向に相互に離
間して収容されていることを特徴とするマルチチップモ
ジュールが得られる。According to the present invention, a multi-chip module that houses a plurality of semiconductor chips and is electrically connected to an electrically insulating substrate having a predetermined electrical wiring pattern by bumps is provided. At
A multi-chip module is obtained in which a multi-stage recess is formed in the electrically insulating substrate, and the semiconductor chips are housed in the recess so as to be vertically separated from each other.

【０００９】[0009]

【実施例】まず、本発明の第１実施例のマルチチップモ
ジュールについて説明する。図１に示すように、半導体
チップ４は、電気配線パターン２を有する電気絶縁基板
１に設けられた多段の凹部にそれぞれ離間並行に上下方
向多段式に収容されている。そして半導体チップ４を載
置する段部にはバンプ３が形成されている。各半導体チ
ップ４はこのバンプ３上に載置されており、電気配線パ
ターン２にて、任意の半導体チップ同士、あるいは、外
部リード６と接続されている。First, a multi-chip module according to a first embodiment of the present invention will be described. As shown in FIG. 1, the semiconductor chips 4 are housed in the multi-tiered recesses provided in the electrically insulating substrate 1 having the electrical wiring pattern 2 in parallel with each other in a vertical multi-tier manner. The bumps 3 are formed on the step portion on which the semiconductor chip 4 is placed. The semiconductor chips 4 are mounted on the bumps 3 and are connected to each other by the electric wiring pattern 2 or to the external leads 6.

【００１０】この場合、半導体チップ４として、チップ
コンデンサ等の搭載も可能である。なお、図中５はキャ
ップ、７は封止材である。In this case, a chip capacitor or the like can be mounted as the semiconductor chip 4. In the figure, 5 is a cap and 7 is a sealing material.

【００１１】次に、本発明の第２実施例のマルチチップ
モジュールについて説明する。第２実施例のマルチチッ
プモジュールは図２に示すように、水平方向にも半導体
チップ４を並列させるように凹部の半導体チップ載置部
を形成しておくものである。なお、このような縦方向の
みではなく横方向への半導体チップ４の配置や数は図示
のものに限定されるものでないことはいうまでもない。Next, the multi-chip module of the second embodiment of the present invention will be described. In the multi-chip module of the second embodiment, as shown in FIG. 2, the semiconductor chip mounting portion of the recess is formed so that the semiconductor chips 4 are arranged in parallel also in the horizontal direction. Needless to say, the arrangement and number of the semiconductor chips 4 not only in the vertical direction but also in the horizontal direction are not limited to those shown in the drawings.

【００１２】第１実施例の半導体チップ４の配置によれ
ば、上方に行くにしたがって半導体チップの大きさが大
きくならざるを得ず、同じ大きさの半導体チップ４を同
一基板に配置することができなかったが、この第２実施
例の配置にすることにより、搭載される半導体チップ４
の大きさ多種多様であっても対応させることが可能とな
る。According to the arrangement of the semiconductor chips 4 of the first embodiment, the size of the semiconductor chips inevitably increases as they go upward, and the semiconductor chips 4 of the same size can be arranged on the same substrate. Although it was not possible, the semiconductor chip 4 mounted by the arrangement of the second embodiment is mounted.
It is possible to support a wide variety of sizes.

【００１３】次に、本発明のマルチチップモジュールに
ヒートシンクを取り付ける場合について説明する。図３
は第１実施例のマルチチップモジュールにヒートシンク
９を取り付けた場合の断面図である。ヒートシンク９を
発熱性の高い半導体チップを最上部に接続し、前記半導
体チップとヒートシンク９を高熱伝導性接着材８を介し
て接着したものである。Next, a case where a heat sink is attached to the multi-chip module of the present invention will be described. Figure 3
FIG. 4 is a cross-sectional view of a multi-chip module of the first embodiment with a heat sink 9 attached. A heat sink 9 is connected to a semiconductor chip having a high heat generating property at the uppermost portion, and the semiconductor chip and the heat sink 9 are bonded to each other via a high thermal conductive adhesive 8.

【００１４】図４は、本発明の第２実施例のマルチチッ
プモジュールにヒートシンク９を取り付けた場合の断面
図である。発熱性の高い半導体チップを複数収納する場
合、本実施例のように電気絶縁基板の凹部の最上部に前
記複数の半導体チップを接続することで、複数の半導体
チップにヒートシンクを接着可能となる。FIG. 4 is a sectional view of the multi-chip module of the second embodiment of the present invention in which a heat sink 9 is attached. When accommodating a plurality of semiconductor chips having a high heat generating property, the heat sink can be bonded to the plurality of semiconductor chips by connecting the plurality of semiconductor chips to the uppermost part of the recess of the electrically insulating substrate as in the present embodiment.

【００１５】なお、上記電気絶縁基板１の材料として
は、アルミナ基板及びガラスエポキシ基板等が従来より
用いられているが、フリップチップ実装の信頼性から考
えると半導体チップと熱膨張率の整合のとれたイビデン
（株）より市販されているセラコム基板という商品名の
基板を用いるのが適切である。Alumina substrates and glass epoxy substrates have been conventionally used as materials for the electrically insulating substrate 1. However, considering the reliability of flip chip mounting, the coefficient of thermal expansion can be matched with that of the semiconductor chip. It is appropriate to use a board having a trade name of Ceracom board sold by Ibiden Co., Ltd.

【００１６】セラコム基板においてのフリップチップ実
装評価実績として、１２５℃〜−６５℃の温度サイクル
試験にて１０００サイクルで断線の発生なしという結果
が得られている。As a result of flip-chip mounting evaluation on a Ceracom board, a result that a disconnection does not occur in 1000 cycles in a temperature cycle test of 125 ° C. to −65 ° C. is obtained.

【００１７】上記本発明の各実施例によれば、従来技術
で電気絶縁基板の大きさが約８５ｍｍ角必要であるもの
を、約５０ｍｍ角程度まで小さくすることが可能であ
る。According to the embodiments of the present invention described above, it is possible to reduce the size of an electrically insulating substrate of about 85 mm square in the prior art to about 50 mm square.

【００１８】[0018]

【発明の効果】以上説明したように本発明は、電気配線
パターンを有する電気絶縁基板に設けられた多段の凹部
に半導体チップを離間並行して縦方向に収容して接続す
ることで、搭載される半導体チップの大きさや数による
制限を受けることなく、電気絶縁基板を小さくすること
ができ、実装密度の向上および電気配線の線路長を短く
して信号伝播遅延時間を短くでき、マルチチップモジュ
ールの高速動作を可能ならしめるという効果がある。As described above, according to the present invention, semiconductor chips are mounted by connecting them in parallel in the vertical direction in a multi-step recess provided in an electrically insulating substrate having an electric wiring pattern. It is possible to reduce the size of the electrically insulating substrate without being limited by the size and number of semiconductor chips to be mounted, improve the packaging density, and shorten the line length of electrical wiring to shorten the signal propagation delay time. This has the effect of enabling high-speed operation.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１実施例を示す断面図である。FIG. 1 is a sectional view showing a first embodiment of the present invention.

【図２】本発明の第２実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the present invention.

【図３】本発明の第１実施例にヒートシンクを取り付け
た場合の断面図である。FIG. 3 is a cross-sectional view when a heat sink is attached to the first embodiment of the present invention.

【図４】本発明の第２実施例にヒートシンクを取り付け
た場合の断面図である。FIG. 4 is a cross-sectional view when a heat sink is attached to the second embodiment of the present invention.

【図５】従来のヒートシンク付マルチチップモジュール
を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional multi-chip module with heat sink.

【符号の説明】[Explanation of symbols]

１ 電気絶縁基板 ２ 電気配線パターン ３ バンプ ４ 半導体チップ ５ キャップ ６ 外部リード ７ 封止材 ８ 高熱伝導性接着材 ９ ヒートシンク １０ 金属細線 1 Electrical Insulating Substrate 2 Electrical Wiring Pattern 3 Bump 4 Semiconductor Chip 5 Cap 6 External Lead 7 Sealing Material 8 High Thermal Conductive Adhesive 9 Heat Sink 10 Metal Wire

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 複数の半導体チップを収納し、前記半導
体チップがバンプにより所定の電気配線パターンを有す
る電気絶縁基板に電気的に接続されてなるマルチチップ
モジュールにおいて、前記電気絶縁基板には多段式凹部
が形成されており、かつ、前記各半導体チップが該凹部
に上下方向に相互に離間して収容されていることを特徴
とするマルチチップモジュール。1. A multi-chip module containing a plurality of semiconductor chips, the semiconductor chips being electrically connected by bumps to an electrically insulating substrate having a predetermined electrical wiring pattern, wherein the electrically insulating substrate is of a multi-stage type. A multi-chip module, wherein a recess is formed, and the respective semiconductor chips are housed in the recess so as to be vertically separated from each other. 【請求項２】 前記電気絶縁基板に形成された凹部内に
おいて、水平方向に単段および・または復段の凹部が複
数形成されて多段式凹部を形成し、これらの凹部に前記
半導体チップが収容されていることを特徴とする請求項
１に記載のマルチチップモジュール。2. A plurality of single-stage and / or double-stage recesses are horizontally formed in the recess formed in the electrically insulating substrate to form a multi-stage recess, and the semiconductor chip is accommodated in these recesses. The multi-chip module according to claim 1, wherein the multi-chip module is provided.
JP4074085A 1992-03-30 1992-03-30 Multi-chip module Expired - Fee Related JP2823029B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4074085A JP2823029B2 (en) 1992-03-30 1992-03-30 Multi-chip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4074085A JP2823029B2 (en) 1992-03-30 1992-03-30 Multi-chip module

Publications (2)

Publication Number Publication Date
JPH05275611A true JPH05275611A (en) 1993-10-22
JP2823029B2 JP2823029B2 (en) 1998-11-11

Family

ID=13536985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4074085A Expired - Fee Related JP2823029B2 (en) 1992-03-30 1992-03-30 Multi-chip module

Country Status (1)

Country Link
JP (1) JP2823029B2 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5728972A (en) * 1996-04-22 1998-03-17 United Microelectronics Corporation Multiple chip module for packaging integrated circuits
JPH10107188A (en) * 1996-09-27 1998-04-24 Kyocera Corp Semiconductor device
US6031279A (en) * 1996-09-02 2000-02-29 Siemens Aktiengesellschaft Power semiconductor component
US6324067B1 (en) 1995-11-16 2001-11-27 Matsushita Electric Industrial Co., Ltd. Printed wiring board and assembly of the same
US6469395B1 (en) 1999-11-25 2002-10-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
KR100368607B1 (en) * 2000-04-17 2003-01-24 주식회사 케이이씨 semiconductor package
US6717251B2 (en) 2000-09-28 2004-04-06 Kabushiki Kaisha Toshiba Stacked type semiconductor device
US6890798B2 (en) 1999-06-08 2005-05-10 Intel Corporation Stacked chip packaging
JP2008521213A (en) * 2004-11-16 2008-06-19 インターナショナル・ビジネス・マシーンズ・コーポレーション Devices and methods for making double-sided SOI wafer scale packages with through-via connections
JP2008211126A (en) * 2007-02-28 2008-09-11 Matsushita Electric Ind Co Ltd Semiconductor module and card type information device
JP2010238923A (en) * 2009-03-31 2010-10-21 Tdk Corp Module with built-in electronic component
JP2014209091A (en) * 2013-03-25 2014-11-06 ローム株式会社 Semiconductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6324067B1 (en) 1995-11-16 2001-11-27 Matsushita Electric Industrial Co., Ltd. Printed wiring board and assembly of the same
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