JPH0524668B2 - - Google Patents
Info
- Publication number
- JPH0524668B2 JPH0524668B2 JP57231931A JP23193182A JPH0524668B2 JP H0524668 B2 JPH0524668 B2 JP H0524668B2 JP 57231931 A JP57231931 A JP 57231931A JP 23193182 A JP23193182 A JP 23193182A JP H0524668 B2 JPH0524668 B2 JP H0524668B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- signal
- scanning
- inspection
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000007689 inspection Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 17
- 238000003384 imaging method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000010355 oscillation Effects 0.000 description 4
- 230000004069 differentiation Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 208000032005 Spinocerebellar ataxia with axonal neuropathy type 2 Diseases 0.000 description 1
- 208000033361 autosomal recessive with axonal neuropathy 2 spinocerebellar ataxia Diseases 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明はパターン保証検査方法、換言すればマ
スク面上のパターン個数を自動的にカウント（数
える）する方法を含む検査方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a pattern guarantee inspection method, in other words, an inspection method including a method of automatically counting the number of patterns on a mask surface.
(b) 従来技術と問題点
半導体集積回路（IC）を製造するに際し、半
導体ウエハー上に多数のパターンを各工程におい
て繰り返えし焼き付けるフオトプロセスが用いら
れており、この各工程で焼き付けるパターンを設
けた基板をマスクと呼んでいる。(b) Prior art and problems When manufacturing semiconductor integrated circuits (ICs), a photo process is used in which a large number of patterns are repeatedly printed on a semiconductor wafer in each process. The provided substrate is called a mask.
したがつて、マスクの品質はIC製造に極めて
重要な影響を与えるもので、従来よりこのような
マスクについて厳重な検査がおこなわれていて、
従前は目視検査であつたが、検査見逃しをなくし
て検査の精度を高くするため自動検査方法が提案
され（特願昭55−10539号その他）、それに基づい
た自動検査装置も市販されている（日本自動制御
KK、マスク欠陥検査装置など）。 Therefore, the quality of masks has an extremely important impact on IC manufacturing, and strict inspections have been carried out on such masks for a long time.
Previously, inspection was done visually, but in order to eliminate missed inspections and increase inspection accuracy, automatic inspection methods have been proposed (Japanese Patent Application No. 10539/1983 and others), and automatic inspection devices based on this method are also commercially available ( japan automatic control
KK, mask defect inspection equipment, etc.).
したがつて、このような自動検査装置によつて
高精度に検査がなされると、それに従つてマスク
の品質も次第に向上してきた。ところが、このよ
うに検査精度が向上してくれば、更に検査処理ス
ピードを速くして一層早い製造と検査との応答が
望まれて、そうすることによつて品質が更に向上
して、コストダウンがはかれる。 Therefore, as inspections are performed with high accuracy using such automatic inspection devices, the quality of masks has gradually improved accordingly. However, as inspection accuracy improves in this way, it is desirable to further speed up the inspection processing speed and achieve a faster response between manufacturing and inspection, which will further improve quality and reduce costs. is measured.
一方、上記のようにマスク品質が向上して安定
してくると、複雑な形状のパターンは別として矩
形や正方形のような単純形状のパターンはその個
数を数える（カウントする）だけで充分の品質と
なつている。 On the other hand, as the mask quality improves and becomes stable as described above, apart from complex-shaped patterns, simple-shaped patterns such as rectangles and squares can be of sufficient quality just by counting the number of them. It is becoming.
(c) 発明の目的
本発明はこのような観点からパターン個数をカ
ウントする検査方法を含むパターン保証検査方法
を提案し、検査の高速化をはからんとするもので
ある。(c) Purpose of the Invention From this viewpoint, the present invention proposes a pattern guarantee inspection method including an inspection method for counting the number of patterns, and aims to speed up inspection.
(d) 発明の構成
その目的は、設計パターンデータのパターン信
号に基づいて作成されたパターンを光学撮像し光
電変換して得られる走査パターン信号の波形エツ
ジが一方向に変化する回数をカウントしそのカウ
ント数と、該走査パターン信号に対応する前記設
計パターンデータのパターン信号の一方向に変化
するカウント数との一致あるいは不一致を比較照
合する工程を含み作成パターンの合否判定を行う
パターン保証検査方法によつて達成することがで
きる。(d) Structure of the Invention The purpose is to optically image a pattern created based on a pattern signal of design pattern data and perform photoelectric conversion to count the number of times the waveform edge of a scanning pattern signal changes in one direction. A pattern guarantee inspection method for determining pass/fail of a created pattern, including the step of comparing and matching the count number and the count number changing in one direction of the pattern signal of the design pattern data corresponding to the scanning pattern signal. This can be achieved by doing so.
(e) 発明の実施例
以下、レチクルを一実施例として図面を参照し
て詳細に説明する。第１図は本発明にかゝる個数
カウント方法の処理フロー図を示し、第２図はレ
チクルの部分平面図である。通常、レチクル全面
には1000個近いパターンが設けられているが、判
り易くするために第２図に示す単純な平面図を参
照する。(e) Embodiments of the Invention Hereinafter, a reticle will be described in detail as an embodiment with reference to the drawings. FIG. 1 shows a processing flow diagram of a number counting method according to the present invention, and FIG. 2 is a partial plan view of a reticle. Normally, nearly 1000 patterns are provided on the entire surface of the reticle, but for ease of understanding, a simple plan view shown in FIG. 2 will be referred to.
LSIでは、CADシステムを利用してレチクル上
の作成するパターンをレイアウト設計する。その
設計パターンデータはメモリ、例えば磁気テープ
に蓄えられている。このような設計マスクデータ
１、即ち設計パターンデータはパターンを電気的
信号に変換し、例えばＸ方向走査の信号線として
メモリに収納されている。一方、このメモリ情報
に基づいて作成されたレチクルは光投射装置にセ
ツトされて、裏面より光を照射し、このレチクル
の全パターン像を、拡大してテレビカメラに写出
する。このようなテレビカメラ面上を上記のメモ
リに収納されている走査信号線と同じ間隙をも
ち、且つ同じ速度をもつた光線で走査２する。し
かし、基準とすべき設計マスクデータ１と同等の
光線走査２ができなければ、メモリからえられる
走査信号線を変換３する。この変換３は例えば信
号線を１つ毎に間引いて半分の走査信号線とした
り、また走査速度を変化させることで、フイルタ
回路や遅延回路から構成される変換回路である。 LSI uses a CAD system to design the layout of the pattern to be created on the reticle. The design pattern data is stored in a memory, such as a magnetic tape. Such design mask data 1, ie, design pattern data, is a pattern converted into an electrical signal and stored in a memory as, for example, a signal line for scanning in the X direction. On the other hand, the reticle created based on this memory information is set in a light projection device and irradiated with light from the back side, and the entire pattern image of this reticle is enlarged and projected onto a television camera. The surface of such a television camera is scanned 2 with a light beam having the same gap and the same speed as the scanning signal line stored in the memory. However, if it is not possible to perform a beam scan 2 equivalent to the design mask data 1 to be used as a reference, the scan signal line obtained from the memory is converted 3. This conversion 3 is a conversion circuit composed of a filter circuit and a delay circuit, for example, by thinning the signal lines one by one to make half the scanning signal lines, or by changing the scanning speed.
かようにしてえられた走査信号線の基準信号
（メモリから入力した信号を基準信号と称する）
を信号処理４してカウント５する一方、レチクル
を光線走査２してえられた光信号線を光電変換６
して、同様の電気信号とし同じくその信号線を信
号処理７してカウント８する。信号処理７は、例
えば第２図に示す走査線L1を光電変換して、第
３図に示す信号線ａがえられると、この信号線ａ
を微分回路とアナログ比較回路とによつて、パタ
ーンの存在する点Ｐ、即ち黒い面内の白いパター
ンと走査線L1とが交わる点を示す、信号線ａの
パルス波形の一方向に変化する立ち上がりエツジ
Ｐの回数をカウント８しこの信号線ａはカウント
２つとする。また前記の基準信号は第３図に示す
信号線S1であり、同じく微分回路とアナログ比較
回路とで構成される信号処理４によつて処理し、
カウント５する。かくしてカウント５は２つであ
つたとすれば、上記カウント８の２つと同じであ
るからデイジタル比較回路によつて比較９され、
それが出力１０され、カウント数が一致している
ことが表示される。 The reference signal of the scanning signal line obtained in this way (the signal input from the memory is called the reference signal)
is subjected to signal processing 4 and counted 5, while the optical signal line obtained by scanning the reticle with light beam 2 is subjected to photoelectric conversion 6.
Then, as a similar electrical signal, the signal line is processed 7 and counted 8. The signal processing 7 photoelectrically converts the scanning line L1 shown in FIG. 2 to obtain the signal line a shown in FIG.
is changed in one direction by the differentiating circuit and the analog comparing circuit, and the pulse waveform of the signal line a, which indicates the point P where the pattern exists, that is, the point where the white pattern in the black surface intersects with the scanning line L1 , is changed in one direction. The number of rising edges P is counted 8, and this signal line a is counted 2. Further, the reference signal is the signal line S1 shown in FIG.
Count to 5. Thus, if count 5 is two, it is the same as count 8, which is two, so it is compared 9 by the digital comparison circuit,
This is output as 10, and it is displayed that the counts match.
しかしながら、基準信号は第３図に示す信号線
S2となると、カウント８は３つとなり、第２図に
示すレチクルにはパターンが１つ欠けたことが比
較されて判かり、不一致が出力される。このよう
にして、レチクルを走査線L2，L3，L4で次々に
光線走査して一致・不一致が出力され、もし不一
致があればパターン欠損となつていることが判か
る。この場合、パターン欠損だけでなく、余分の
付着部分があれば、同様に不一致となり、比較回
路から出力する際、パターン欠損あるいは余分の
付着を区別し、出力することも可能である。 However, the reference signal is the signal line shown in Figure 3.
At S 2 , the count 8 becomes three, and it is compared and found that one pattern is missing from the reticle shown in FIG. 2, and a mismatch is output. In this way, the reticle is sequentially scanned by the light beams using the scanning lines L 2 , L 3 , and L 4 to output a match/mismatch, and if there is a match, it can be seen that the pattern is missing. In this case, if there is not only a missing pattern but also an extra adhered portion, a mismatch will occur as well, and when outputting from the comparison circuit, it is possible to distinguish between the missing pattern or the extra attached portion and output it.
本発明によれば上記のＸ方向走査による信号線
を比較するのみで、充分にパターン個数を検出す
ることができるが、Ｘ方向の走査と同時にＹ方向
に走査点を記録して検査精度を更に向上させるこ
ともできる。それはシフトレジスタなどからなる
画面メモリにＸ方向の走査信号線を蓄えておい
て、例えば第４図に示す信号処理フロー図によつ
てＹ方向に信号変化数をカウントする。すなわ
ち、Ｙ方向においては、１つ前の走査信号に遅延
回路１１を設けて時間軸をほゞ合致させ、隣接し
た信号とを比較するもので、パターン有無の信号
変化をうけると、微分回路１２が働き、一方信号
線のスタート信号１３によつて発振回路１４を一
定に発振させておき、上記の微分回路１２からの
信号入力で発振パルスをストツプ又はスタートさ
せて、その変化数をカウンタ１５でカウントし、
両方の走査信号を比較１６してその変化点を出力
１７する。第５図はその走査信号を示す図で、片
方の走査信号線ｂはスタート信号１３によつて一
定パルスを発振して変化していないが、他方の走
査信号線ｃは微分回路からの信号S3によつてパル
スが一定期間ストツプすることを示している。そ
の変化点Q1，Q2がカウンタ１５でカウントされ、
上記したＸ方向の信号線とこのＹ方向の信号の変
化点が一致したところをパターン有とみなすもの
である。このようにすれば、検査精度が向上す
る。 According to the present invention, the number of patterns can be detected sufficiently by simply comparing the signal lines scanned in the X direction, but inspection accuracy can be further improved by recording scanning points in the Y direction at the same time as scanning in the X direction. It can also be improved. In this method, scanning signal lines in the X direction are stored in a screen memory such as a shift register, and the number of signal changes in the Y direction is counted according to the signal processing flow diagram shown in FIG. 4, for example. That is, in the Y direction, a delay circuit 11 is provided for the previous scanning signal so that the time axes almost match, and adjacent signals are compared. On the other hand, the oscillation circuit 14 is kept in constant oscillation by the start signal 13 on the signal line, and the oscillation pulse is stopped or started by the signal input from the differentiation circuit 12, and the number of changes is counted by the counter 15. count and
Both scanning signals are compared 16 and the change point is output 17. FIG. 5 is a diagram showing the scanning signals. One scanning signal line b oscillates a constant pulse in response to the start signal 13 and remains unchanged, while the other scanning signal line c receives the signal S from the differentiating circuit. 3 indicates that the pulse is stopped for a certain period of time. The change points Q 1 and Q 2 are counted by the counter 15,
A pattern is considered to be present when the above-mentioned X-direction signal line and this Y-direction signal change point coincide. In this way, inspection accuracy is improved.
以上の実施例のような本発明にかゝる検査方法
を、従来のパターン検査方式即ち基準パターンデ
ータからの走査信号とレチクル上のパターンを走
査してえた走査信号を比較照合（例えば信号クロ
ツク数を比較照合）して、高精度にパターン検査
する方式に附加する。そして、単純形状のパター
ンの場合には切り換えて本発明による検査方法を
適用し、検査処理スピードの向上をはかる。 The inspection method according to the present invention as described in the above embodiments is applied to a conventional pattern inspection method, that is, by comparing and comparing the scanning signal from the reference pattern data with the scanning signal obtained by scanning the pattern on the reticle (for example, the number of signal clocks). This is an addition to the method for highly accurate pattern inspection. Then, in the case of a pattern with a simple shape, the inspection method according to the present invention is applied in order to improve the inspection processing speed.
(f) 発明の効果
このようにすれば、パターン検査が効率的にな
つて、製造ミスによる損失が最小となり、工数低
減にもつながる。したがつて、本発明は検査工数
の削減の他、設計や製造の工数減少にも役立つも
のである。(f) Effects of the invention By doing so, pattern inspection becomes efficient, losses due to manufacturing errors are minimized, and the number of man-hours is reduced. Therefore, the present invention is useful in reducing not only the number of inspection steps but also the number of design and manufacturing steps.
尚、上記例はレチクルで説明したが、他のコピ
ーマスクにも適用できることは当然である。 Note that although the above example has been explained using a reticle, it is of course applicable to other copy masks as well.
第１図は本発明にかゝるＸ方向走査信号線の処
理フロー図、第２図はレチクルの部分平面図、第
３図は走査信号線を示す図、第４図はＹ方向走査
信号の信号処理フロー図、第５図はその走査信号
線の例図である。
図中、１は設計マスクデータ、２はレチクルの
光線走査、３は変換系、４，７は走査信号処理
系、５，８はカウント系、６は光電変換系、９は
比較系、１０は出力、１１は遅延回路、１２は微
分回路、１３はスタート信号、１４は発振回路、
１５はカウンタ、１６は比較系、１７は出力、
L1〜L4は走査線、ａ，ｂ，ｃ，S1，S2，S3は信
号線を示す。
Fig. 1 is a processing flow diagram of the X-direction scanning signal line according to the present invention, Fig. 2 is a partial plan view of the reticle, Fig. 3 is a diagram showing the scanning signal line, and Fig. 4 is a diagram of the Y-direction scanning signal. The signal processing flowchart, FIG. 5, is an example diagram of the scanning signal line. In the figure, 1 is design mask data, 2 is reticle beam scanning, 3 is a conversion system, 4 and 7 are scanning signal processing systems, 5 and 8 are count systems, 6 is a photoelectric conversion system, 9 is a comparison system, and 10 is a Output, 11 is a delay circuit, 12 is a differentiation circuit, 13 is a start signal, 14 is an oscillation circuit,
15 is a counter, 16 is a comparison system, 17 is an output,
L1 to L4 are scanning lines, and a, b, c, S1 , S2 , and S3 are signal lines.
Claims (1)
て作成されたパターンを光学撮像し光電変換して
得られる走査パターン信号の波形エツジが一方向
に変化する回数をカウントしそのカウント数と、
該走査パターン信号に対応する前記設計パターン
データのパターン信号の一方向に変化するカウン
ト数との一致あるいは不一致を比較照合する工程
を含み作成パターンの合否判定を行うことを特徴
とするパターン保証検査方法。1 Count the number of times the waveform edge of a scanning pattern signal obtained by optically imaging and photoelectrically converting a pattern created based on a pattern signal of design pattern data changes in one direction, and calculate the number of times the waveform edge changes in one direction.
A pattern guarantee inspection method comprising the step of comparing and matching the count number changing in one direction of the pattern signal of the design pattern data corresponding to the scanning pattern signal, and determining the pass/fail of the created pattern. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23193182A JPS59124139A (en) | 1982-12-29 | 1982-12-29 | Assured pattern inspection process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23193182A JPS59124139A (en) | 1982-12-29 | 1982-12-29 | Assured pattern inspection process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59124139A JPS59124139A (en) | 1984-07-18 |
| JPH0524668B2 true JPH0524668B2 (en) | 1993-04-08 |
Family
ID=16931301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23193182A Granted JPS59124139A (en) | 1982-12-29 | 1982-12-29 | Assured pattern inspection process |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59124139A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50140272A (en) * | 1974-04-27 | 1975-11-10 |
-
1982
- 1982-12-29 JP JP23193182A patent/JPS59124139A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50140272A (en) * | 1974-04-27 | 1975-11-10 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59124139A (en) | 1984-07-18 |
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