JPH0522179A - Received signal intensity detecting circuit - Google Patents
Received signal intensity detecting circuitInfo
- Publication number
- JPH0522179A JPH0522179A JP19829291A JP19829291A JPH0522179A JP H0522179 A JPH0522179 A JP H0522179A JP 19829291 A JP19829291 A JP 19829291A JP 19829291 A JP19829291 A JP 19829291A JP H0522179 A JPH0522179 A JP H0522179A
- Authority
- JP
- Japan
- Prior art keywords
- agc
- converter
- signal
- amplifier
- agc voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、無線通信機に用いら
れ、受信信号強度を検出する受信信号強度検出回路に関
し、特に、ＡＧＣ増幅器を有する受信機の受信信号強度
検出回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a received signal strength detection circuit used in a wireless communication device for detecting received signal strength, and more particularly to a received signal strength detection circuit for a receiver having an AGC amplifier.
【０００２】[0002]
【従来の技術】無線機等の受信系において、受信入力が
高入力時の特性確保のため高周波段に高入力時に動作す
るＡＧＣ増幅器が設けられている場合、中間周波段以降
での入力信号強度を示す検出値は高周波段のＡＧＣによ
る利得変化分だけ低い値となる。これを避けるため、高
周波段のＡＧＣ増幅器の前で入力信号を分配して信号強
度検出回路を設けられている。図３はこのような従来技
術での受信機の構成例図である。この受信機の受信入力
強度検出回路について説明する。2. Description of the Related Art In a receiving system of a radio device or the like, when an AGC amplifier which operates at a high input is provided in a high frequency stage in order to secure a characteristic when a high input is received, an input signal strength after an intermediate frequency stage is provided. The detected value indicating is low by the gain change due to the AGC in the high frequency stage. In order to avoid this, a signal strength detection circuit is provided by distributing the input signal in front of the AGC amplifier in the high frequency stage. FIG. 3 is a diagram showing a configuration example of a receiver according to such a conventional technique. The reception input strength detection circuit of this receiver will be described.
【０００３】検出の対象となる入力信号は、帯域フィル
タ３１で帯域制限され、高周波ＡＧＣ増幅器３２に入力
される以前で入力信号強度の検出を行なわなければなら
ないため分配器３３により入力信号を分配し、高周波増
幅器３４により増幅され、周波数変換器３５で局発信号
と混合されて中間周波信号となる。中間周波信号は帯域
フィルタ３６を経て中間周波増幅器３７で増幅され、検
波器３８の出力電圧により、信号強度検出器３９で信号
強度を検出して出力される。The input signal to be detected is band-limited by the band filter 31, and the input signal strength must be detected before it is input to the high frequency AGC amplifier 32, so that the input signal is distributed by the distributor 33. The signal is amplified by the high frequency amplifier 34 and mixed with the local oscillation signal by the frequency converter 35 to form an intermediate frequency signal. The intermediate frequency signal is amplified by the intermediate frequency amplifier 37 after passing through the bandpass filter 36, and the signal strength is detected by the signal strength detector 39 by the output voltage of the detector 38 and output.
【０００４】[0004]
【発明が解決しようとする課題】上述のような受信信号
強度検出回路は、回路構成が複雑であるため、小型化，
経済性の点で問題となる。本発明が解決しようとする課
題は、ＡＧＣ増幅器が設けられた受信機において、ＡＧ
Ｃ（自動利得制御）の影響を受けることなく正確な入力
受信信号強度を検出し、かつ、回路構成を簡易にして経
済性の効果を得ることである。The received signal strength detection circuit as described above has a complicated circuit structure, and therefore is downsized.
It becomes a problem in terms of economy. The problem to be solved by the present invention is to solve the problem in a receiver provided with an AGC amplifier.
An accurate input reception signal strength is detected without being affected by C (automatic gain control), and the circuit configuration is simplified to obtain an economical effect.
【０００５】[0005]
【課題を解決するための手段】本発明の受信信号強度検
出回路は、高周波段と中間周波段とにそれぞれＡＧＣ増
幅器を有し受信復調信号を出力する無線受信機の受信信
号強度を検出するために、前記高周波段のＡＧＣ電圧を
ディジタル信号に変換する第１のＡ／Ｄコンバータと、
前記中間周波段のＡＧＣ電圧をディジタル信号に変換す
る第２のＡ／Ｄコンバータと、前記高周波段のＡＧＣ電
圧と前記中間周波段のＡＧＣ電圧とにそれぞれ対応して
それぞれ相殺するような複数段階の補正データが予め記
憶され、前記第１および第２のＡ／Ｄコンバータからの
ディジタル信号に対応する該補正データを読み出して出
力するメモリと、該メモリからの出力をアナログ信号に
変換するＤ／Ａコンバータと、該Ｄ／Ａコンバータから
のアナログ信号により前記受信復調信号を補正すること
により前記ＡＧＣ増幅器のＡＧＣによる利得変化の影響
を受けない前記受信信号強度を示す出力を得る補正回路
とを備えたことを特徴とするものである。すなわち、本
発明では、ＡＧＣ増幅器のＡＧＣ電圧と利得特性との関
係とを予めメモリに記憶する手段と、信号強度検出時の
ＡＧＣ電圧に対応してメモリから読出したデータにより
信号強度の補正を行なう手段を設けたことを要旨とする
ものである。この時、ＡＧＣ応答速度に比較して、メモ
リ読出し速度を速くすることにより、ＡＧＣ増幅器を経
た信号の正確な受信信号強度検出をすることができる。
以下本発明の詳細を説明する。The received signal strength detection circuit of the present invention detects the received signal strength of a radio receiver which has an AGC amplifier in each of a high frequency stage and an intermediate frequency stage and outputs a received demodulated signal. And a first A / D converter for converting the AGC voltage of the high frequency stage into a digital signal,
A second A / D converter for converting the AGC voltage of the intermediate frequency stage into a digital signal, and a plurality of stages for canceling the AGC voltage of the high frequency stage and the AGC voltage of the intermediate frequency stage respectively corresponding to each other. Correction data is stored in advance, a memory for reading and outputting the correction data corresponding to the digital signals from the first and second A / D converters, and a D / A for converting the output from the memory into an analog signal A converter and a correction circuit for correcting the received demodulated signal with an analog signal from the D / A converter to obtain an output indicating the received signal strength that is not affected by a gain change due to AGC of the AGC amplifier. It is characterized by that. That is, in the present invention, the signal strength is corrected by means for storing the relationship between the AGC voltage of the AGC amplifier and the gain characteristic in the memory in advance and the data read from the memory corresponding to the AGC voltage at the time of detecting the signal strength. The purpose is to provide means. At this time, by increasing the memory reading speed as compared with the AGC response speed, it is possible to accurately detect the received signal strength of the signal that has passed through the AGC amplifier.
The details of the present invention will be described below.
【０００６】[0006]
【実施例】図１は本発明の実施例を示す構成例図であ
る。信号強度検出の対象となる入力信号は、帯域フィル
タ１で帯域制限され、高周波ＡＧＣ増幅器２で増幅さ
れ、周波数変換器３で局発信号と混合されて中間周波信
号に変換される。中間周波信号は帯域フィルタ４を経て
中間周波ＡＧＣ増幅器５で増幅され復調器６で復調さ
れ、低域フィルタ７を経て増幅器８で増幅され出力され
るとともに補正回路９へも出力される。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a structural example diagram showing an embodiment of the present invention. The input signal, which is the target of signal strength detection, is band-limited by the band filter 1, amplified by the high frequency AGC amplifier 2, mixed with the local oscillation signal by the frequency converter 3 and converted into an intermediate frequency signal. The intermediate frequency signal passes through the bandpass filter 4, is amplified by the intermediate frequency AGC amplifier 5, is demodulated by the demodulator 6, is amplified by the amplifier 8 through the low pass filter 7, is output, and is also output to the correction circuit 9.
【００１０】入力信号が高入力となると高周波ＡＧＣ増
幅器２はＡＧＣ電圧発生回路１０からのＡＧＣ電圧によ
り利得制限されるが、このＡＧＣ電圧をＡ／Ｄコンバー
タ１１によりディジタル信号に変換する。また中間周波
ＡＧＣ増幅器５はＡＧＣ電圧発生回路１２からのＡＧＣ
電圧により利得制限され、このＡＧＣ電圧をＡ／Ｄコン
バータ１３によりディジタル信号に変換する。ＲＯＭ１
４には、予めそれぞれのＡＧＣ電圧に対する補正信号の
データが記憶されており、各ＡＧＣ電圧によりＡＧＣ増
幅器２および５の利得を相殺する補正信号がＤ／Ａコン
バータ１５より補正回路９に与えられ、補正回路９から
はＡＧＣによる利得変化に関係なく入力信号の強度を示
す電圧が出力される。When the input signal becomes a high input, the high frequency AGC amplifier 2 is gain-limited by the AGC voltage from the AGC voltage generating circuit 10. The AGC voltage is converted into a digital signal by the A / D converter 11. Further, the intermediate frequency AGC amplifier 5 uses the AGC from the AGC voltage generating circuit 12.
The gain is limited by the voltage, and this AGC voltage is converted into a digital signal by the A / D converter 13. ROM1
Data of a correction signal for each AGC voltage is stored in advance in 4, and a correction signal for canceling the gains of the AGC amplifiers 2 and 5 by each AGC voltage is given from the D / A converter 15 to the correction circuit 9. The correction circuit 9 outputs a voltage indicating the strength of the input signal regardless of the gain change due to the AGC.
【００１１】次に具体的な動作について述べる。図２は
図１の各点における電圧または電力の入力電力に対する
特性図である。高周波ＡＧＣ増幅器２はある入力電圧値
Ａを越えると図２（ａ）に示すＡＧＣ電圧が与えられ一
定の電力を出力する。また中間周波ＡＧＣ増幅器５は図
２（ｂ）に示すＡＧＣ電圧により利得が制御され、図１
のｃ点では、ＡＧＣ範囲内では入力電力に対して図２
（ｃ）に示すように一定の信号電力となる。ａ点のＡＧ
Ｃ電圧とｂ点のＡＧＣ電圧をＡ／Ｄ変換したディジタル
値をＲＯＭ１４のアドレスとし、アドレスに対応するデ
ータとしては、ｄ点の特性が入力電力に対してＡＧＣ特
性を相殺して図２（ｄ）に示すように、入力電力に対し
比例して変化する補正信号となるようにＤ／Ａコンバー
タ１５で変換されるようなディジタル値を書込んでお
く。予めこのような操作でＲＯＭ１４を準備しておくこ
とにより、ＡＧＣ電圧に対応した補正電圧を発生させる
ことができるため、ＡＧＣ増幅器２及び５により制御さ
れた利得変化に関係なく入力信号の強度を検出すること
ができる。この例では、Ａ／Ｄ変換，Ｄ／Ａ変換の分解
能を上げることにより、入力信号の検出強度の精度を向
上することができるNext, a specific operation will be described. FIG. 2 is a characteristic diagram of voltage or power at each point in FIG. 1 with respect to input power. The high frequency AGC amplifier 2 is supplied with the AGC voltage shown in FIG. 2A when a certain input voltage value A is exceeded, and outputs a constant power. The gain of the intermediate frequency AGC amplifier 5 is controlled by the AGC voltage shown in FIG.
At point c in Fig. 2, the input power is shown in Fig. 2 within the AGC range.
The signal power is constant as shown in (c). AG at point a
A digital value obtained by A / D converting the C voltage and the AGC voltage at the point b is used as the address of the ROM 14, and as the data corresponding to the address, the characteristic at the point d cancels the AGC characteristic with respect to the input power, and the characteristic shown in FIG. ), A digital value that is converted by the D / A converter 15 is written so as to obtain a correction signal that changes in proportion to the input power. Since the correction voltage corresponding to the AGC voltage can be generated by preparing the ROM 14 in advance by such an operation, the strength of the input signal is detected regardless of the gain change controlled by the AGC amplifiers 2 and 5. can do. In this example, the accuracy of the detection intensity of the input signal can be improved by increasing the resolution of A / D conversion and D / A conversion.
【００１２】[0012]
【発明の効果】本発明は比較的簡易な回路で構成するこ
とができるため、ＡＧＣ機能を有する無線機等に実施す
ることによって大きな経済的・物理的利点を得ることが
できる。また、メモリに記憶するデータ量を増やすこと
より、より正確な受信信号強度を検出することが可能と
なる。Since the present invention can be configured by a relatively simple circuit, it can be applied to a radio having an AGC function or the like to obtain great economic and physical advantages. Further, by increasing the amount of data stored in the memory, it becomes possible to detect the received signal strength more accurately.
【図１】本発明の実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.
【図２】図１の各点における入力信号に対する特性図で
ある。FIG. 2 is a characteristic diagram for an input signal at each point in FIG.
【図３】従来の実施例を示すブロック図である。FIG. 3 is a block diagram showing a conventional example.
１ 帯域フィルタ ２ 高周波ＡＧＣ増幅器 ３ 周波数変換回路 ４ 帯域フィルタ ５ 中間周波ＡＧＣ増幅器 ６ 復調器 ７ 低域フィルタ ８ 増幅器 ９ 補正回路 １０，１２ ＡＧＣ電圧発生回路 １１，１３ Ａ／Ｄコンバータ １４ ＲＯＭ １５ Ｄ／Ａコンバータ ３１，３６ 帯域フィルタ ３２ 高周波ＡＧＣ増幅器 ３３ 分配器 ３４ 高周波増幅器 ３５ 周波数変換器 ３７ 中間周波増幅器 ３８ 検波器 ３９ 検出器 1 band filter 2 high frequency AGC amplifier 3 frequency conversion circuit 4 band filter 5 intermediate frequency AGC amplifier 6 demodulator 7 low pass filter 8 amplifier 9 correction circuit 10, 12 AGC voltage generation circuit 11, 13 A / D converter 14 ROM 15 D / A converter 31, 36 Band filter 32 High frequency AGC amplifier 33 Distributor 34 High frequency amplifier 35 Frequency converter 37 Intermediate frequency amplifier 38 Detector 39 Detector
Claims (1)
Ｃ増幅器を有し受信復調信号を出力する無線受信機の受
信信号強度を検出するために、 前記高周波段のＡＧＣ電圧をディジタル信号に変換する
第１のＡ／Ｄコンバータと、 前記中間周波段のＡＧＣ電圧をディジタル信号に変換す
る第２のＡ／Ｄコンバータと、 前記高周波段のＡＧＣ電圧と前記中間周波段のＡＧＣ電
圧とにそれぞれ対応してそれぞれ相殺するような複数段
階の補正データが予め記憶され、前記第１および第２の
Ａ／Ｄコンバータからのディジタル信号に対応する該補
正データを読み出して出力するメモリと、 該メモリからの出力をアナログ信号に変換するＤ／Ａコ
ンバータと、 該Ｄ／Ａコンバータからのアナログ信号により前記受信
復調信号を補正することにより前記ＡＧＣ増幅器のＡＧ
Ｃによる利得変化の影響を受けない前記受信信号強度を
示す出力を得る補正回路とを備えた受信信号強度検出回
路。Claims: 1. A high frequency stage and an intermediate frequency stage are each provided with an AG.
A first A / D converter for converting the AGC voltage of the high frequency stage into a digital signal in order to detect the received signal strength of a radio receiver which has a C amplifier and outputs a received demodulated signal; A second A / D converter for converting the AGC voltage into a digital signal, and a plurality of stages of correction data for preliminarily storing the AGC voltage of the high-frequency stage and the AGC voltage of the intermediate-frequency stage, which cancel each other. A memory for reading and outputting the correction data corresponding to the digital signals from the first and second A / D converters; a D / A converter for converting the output from the memory into an analog signal; Of the AGC amplifier by correcting the received demodulated signal with the analog signal from the A / A converter.
A received signal strength detection circuit comprising: a correction circuit that obtains an output indicating the received signal strength that is not affected by a gain change due to C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19829291A JPH0522179A (en) | 1991-07-15 | 1991-07-15 | Received signal intensity detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19829291A JPH0522179A (en) | 1991-07-15 | 1991-07-15 | Received signal intensity detecting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0522179A true JPH0522179A (en) | 1993-01-29 |
Family
ID=16388704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19829291A Pending JPH0522179A (en) | 1991-07-15 | 1991-07-15 | Received signal intensity detecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0522179A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007174099A (en) * | 2005-12-20 | 2007-07-05 | Alps Electric Co Ltd | Television tuner for mobile |
-
1991
- 1991-07-15 JP JP19829291A patent/JPH0522179A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007174099A (en) * | 2005-12-20 | 2007-07-05 | Alps Electric Co Ltd | Television tuner for mobile |
| JP4603480B2 (en) * | 2005-12-20 | 2010-12-22 | アルプス電気株式会社 | Mobile TV tuner |
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