JPH0522077A - Differential amplifier circuit with built-in low pass filter - Google Patents
Differential amplifier circuit with built-in low pass filterInfo
- Publication number
- JPH0522077A JPH0522077A JP3171303A JP17130391A JPH0522077A JP H0522077 A JPH0522077 A JP H0522077A JP 3171303 A JP3171303 A JP 3171303A JP 17130391 A JP17130391 A JP 17130391A JP H0522077 A JPH0522077 A JP H0522077A
- Authority
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- Prior art keywords
- resistor
- capacitor
- resistors
- operational amplifier
- input terminal
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＣＤ（コンパクトディ
スク）オーディオ装置に適用して好適なローパスフィル
タ内蔵差動増幅回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit with a built-in low-pass filter, which is suitable for use in a CD (Compact Disc) audio device.
【０００２】[0002]
【従来の技術】近時、多用される１ビットデジタル・ア
ナログコンバータ（以下、１ｂｉｔＤＡＣと記載する）
等のＰＷＭ（パルス幅変調）回路の後段の差動入力回路
には、平均化（積分）アナログ信号を得るための、抵抗
器Ｒ、コンデンサＣからなる積分回路と、演算増幅器を
用いた差動増幅回路と、同様に演算増幅器を用いたノイ
ズ除去用のローパスフィルタ（以下、必要に応じてＬＰ
Ｆと記載する）が設けられるのが一般的である。2. Description of the Related Art Recently, a 1-bit digital-analog converter (hereinafter referred to as 1-bit DAC) which is frequently used.
In the differential input circuit in the subsequent stage of the PWM (pulse width modulation) circuit such as, for example, a differential circuit using an operational amplifier and an integrating circuit including a resistor R and a capacitor C to obtain an averaged (integrated) analog signal. A low-pass filter for noise removal that uses an amplifier circuit and an operational amplifier in the same manner (hereinafter referred to as LP if necessary).
(Denoted as F) is generally provided.
【０００３】[0003]
【発明が解決しようとする課題】ところで上記従来例の
差動増幅回路をＣＤオーディオ装置に利用する場合、最
低でも差動増幅器およびＬＰＦに用いる二つの演算増幅
器が必要である。この場合、部品数が多くなり、構成が
複雑化して製造コストが嵩み、さらに製造工程における
不良率が上昇するという不都合がある。また信号処理規
模も大きくなり消費電流が増大してしまう。When the differential amplifier circuit of the above conventional example is used in a CD audio device, at least two operational amplifiers used for the differential amplifier and the LPF are required. In this case, there are inconveniences that the number of parts increases, the configuration becomes complicated, the manufacturing cost increases, and the defect rate in the manufacturing process increases. In addition, the signal processing scale becomes large and the current consumption increases.
【０００４】本発明は上述の点に鑑みてなされ、演算増
幅器の数が低減し、その構成が簡素化されるととともに
信号処理規模が縮小されて、消費電流が低減できる優れ
たＬＰＦ内蔵差動増幅回路を提供することを目的とす
る。The present invention has been made in view of the above points, and the number of operational amplifiers is reduced, the configuration is simplified, the signal processing scale is reduced, and the current consumption is reduced. An object is to provide an amplifier circuit.
【０００５】[0005]
【課題を解決するための手段】一方の入力端子（Ｔi1）
を第１及び第２の抵抗器（Ｒ1 ，Ｒ3 ）の直列回路を介
して演算増幅器（２）の非反転入力端に接続し、上記第
１及び第２の抵抗器（Ｒ1 ，Ｒ3 ）の接続点を第１のコ
ンデンサ（Ｃ1 ）を介して上記演算増幅器（２）の出力
端に接続し、上記演算増幅器（２）の非反転入力端を第
３の抵抗器（Ｒ 5 ）及び第２のコンデンサ（Ｃ3 ）の並
列回路を介して接地すると共に他方の入力端子（Ｔi2）
を上記第１の抵抗器（Ｒ1 ）と抵抗値の等しい第４の抵
抗器（Ｒ 2 ）及び上記第２の抵抗器（Ｒ3 ）と抵抗値の
等しい第５の抵抗器（Ｒ4 ）の直列回路を介して上記演
算増幅器（２）の反転入力端に接続し、上記第４及び第
５の抵抗器（Ｒ2 ，Ｒ4 ）の接続点を上記第１のコンデ
ンサ（Ｃ1 ）と容量値の等しい第３のコンデンサ
（Ｃ2 ）を介して接地し、上記演算増幅器（２）の反転
入力端を上記第３の抵抗器（Ｒ5 ）と抵抗値の等しい第
６の抵抗器（Ｒ6 ）及び上記第２のコンデンサ（Ｃ3 ）
と容量値の等しい第４のコンデンサ（Ｃ4 ）の並列回路
を介して上記演算増幅器（２）の出力端に接続し、増幅
率、遮断周波数及びＱ値を定めて上記各抵抗器及びコン
デンサの大小関係を決定するようにしたことを特徴とす
るローパスフィルタ内蔵差動増幅回路。Means for Solving the Problems One input terminal (Ti1)
The first and second resistors (R1, R3) Series circuit
Connected to the non-inverting input terminal of the operational amplifier (2),
1st and 2nd resistor (R1, R3) Connection point to the first
Capacitor (C1Output of the operational amplifier (2) via
And the non-inverting input terminal of the operational amplifier (2) is connected to the
3 resistors (R Five) And the second capacitor (C3)
The other input terminal (Ti2)
Is the first resistor (R1) And the fourth resistance with the same resistance value
Responder (R 2) And the second resistor (R3) And the resistance
Equal fifth resistor (RFour) Through the series circuit
Connected to the inverting input terminal of the operational amplifier (2),
5 resistors (R2, RFour) Connection point to the first
Sensor (C1) And a third capacitor having the same capacitance value as
(C2) To ground, and the operational amplifier (2) is inverted
The input end is connected to the third resistor (RFive) With the same resistance
6 resistors (R6) And the second capacitor (C3)
And a fourth capacitor (CFour) Parallel circuit
Connected to the output terminal of the operational amplifier (2) via
Rate, cut-off frequency and Q value are set, and the above resistors and capacitors are
It is characterized in that the size relationship of Densa is decided
Differential amplifier circuit with built-in low-pass filter.
【０００６】[0006]
【作用】本発明のＬＰＦ内蔵差動増幅回路によれば、差
動増幅器に正帰還をかけた抵抗器およびコンデンサから
なるアクティブＬＰＦが設けられているため、従来、こ
のＬＰＦを構成していた演算増幅器が不要になり、その
演算増幅器の数が低減して、構成が簡素化されるととも
に信号処理規模が縮小して消費電流が低減できる。According to the differential amplifier circuit with a built-in LPF of the present invention, an active LPF composed of a resistor and a capacitor for positive feedback is provided in the differential amplifier. Amplifiers are not required, the number of operational amplifiers is reduced, the configuration is simplified, and the signal processing scale is reduced, so that current consumption can be reduced.
【０００７】[0007]
【実施例】以下、本発明のＬＰＦ内蔵差動増幅回路の一
実施例について図面を参照して説明する。図１は第１の
実施例の構成を示している。この例は、入力信号（電
圧）ＶA が入力端子Ｔi1に接続された抵抗器Ｒ1の一端
に供給される。この抵抗器Ｒ1 の他端に抵抗器Ｒ3 の一
端が接続されるとともに、抵抗器Ｒ3 の他端が演算増幅
器２の正極入力端（＋非反転入力端）に接続されてい
る。抵抗器Ｒ1 と抵抗器Ｒ3 との接続点にコンデンサＣ
1 の一端が接続され、この他端が演算増幅器２の出力端
に接続されている。さらに、演算増幅器２の正極入力端
（＋）に、並列接続した抵抗器Ｒ5 とコンデンサＣ3 の
夫々の一端が接続され、夫々の他端が接地されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the LPF built-in differential amplifier circuit of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the first embodiment. In this example, an input signal (voltage) V A is supplied to one end of a resistor R 1 connected to an input terminal T i1 . One end of the resistor R 3 is connected to the other end of the resistor R 1, the other end of the resistor R 3 is connected to the positive input terminal of the operational amplifier 2 (+ non-inverting input terminal). A capacitor C is provided at the connection point between the resistors R 1 and R 3.
One end of 1 is connected, and the other end is connected to the output end of the operational amplifier 2. Further, the positive input terminal (+) of the operational amplifier 2 is connected to one ends of a resistor R 5 and a capacitor C 3 which are connected in parallel, and the other ends thereof are grounded.
【０００８】入力信号（電圧）ＶB が入力端子Ｔi2に接
続された抵抗器Ｒ2 の一端に供給されている。この抵抗
器Ｒ2の他端に抵抗器Ｒ4 の一端が接続されるとともに
抵抗器Ｒ4 の他端が演算増幅器２のマイナス（−反転入
力端）入力端に接続されている。抵抗器Ｒ2 と抵抗器Ｒ
4 との接続点にコンデンサＣ2 の一端が接続され、さら
に他端が接地されている。また、演算増幅器２のマイナ
ス入力端に、並列接続した抵抗器Ｒ6 とコンデンサＣ4
の夫々の一端が接続され、さらに夫々の他端が演算増幅
器２の出力端に接続されている。この出力端から入力端
子ＴO を通じて出力信号（電圧）ＶO が得られる。The input signal (voltage) V B is supplied to one end of the resistor R 2 connected to the input terminal T i2 . The resistor R 2 at the other end to a resistor minus the other end of the resistor R 4 is an operational amplifier 2 with one end of the R 4 is connected - is connected to the (inverting input terminal) input. Resistor R 2 and resistor R
One end of the capacitor C 2 is connected to the connection point with 4, and the other end is grounded. Further, the negative input terminal of the operational amplifier 2 is connected in parallel with a resistor R 6 and a capacitor C 4
Are connected to one end, and the other ends are connected to the output end of the operational amplifier 2. An output signal (voltage) V O is obtained from this output terminal through the input terminal T O.
【０００９】次に、第１の実施例における動作について
説明する。ここで、各抵抗器（Ｒ1 乃至Ｒ6 ）コンデン
サ（Ｃ1 乃至Ｃ4 ）の関係を、Ｒ 1 ＝Ｒ2 ＝ＲA 、Ｒ3
＝Ｒ4 ＝ＲB 、Ｒ5 ＝Ｒ6 ＝ＲC 、Ｃ1 ＝Ｃ2 ＝ＣA、
Ｃ 3 ＝Ｃ4 ＝ＣB 、Ｓは複数変数（ラプラス演算子）と
し、この場合の各接点において節点方程式を立て、ラプ
ラス変換を行い伝達関数を求めると、この伝達関数は、Next, the operation in the first embodiment
explain. Here, each resistor (R1Through R6) Conden
Service (C1To CFour), R 1= R2= RA, R3
= RFour= RB, RFive= R6= RC, C1= C2= CA,
C 3= CFour= CB, S are multiple variables (Laplace operator)
Then, a node equation is established at each contact in this case, and
When the transfer function is obtained by performing the Lath transform, this transfer function is
【００１０】[0010]
【数１】 [Equation 1]
【００１１】で表される。この（数１）は、次に示す一
般の２次のＬＰＦの式で表わされる。It is represented by This (Equation 1) is expressed by the following general second-order LPF equation.
【００１２】[0012]
【数２】 [Equation 2]
【００１３】上記式においてIn the above equation
【００１４】[0014]
【数３】 [Equation 3]
【００１５】となり、そのＱ値は、And the Q value is
【００１６】[0016]
【数４】 [Equation 4]
【００１７】となる。[0017]
【００１８】このように、抵抗器Ｒ1 と抵抗器Ｒ2 、抵
抗器Ｒ3 と抵抗器Ｒ4 および抵抗器Ｒ5 と抵抗器Ｒ6 を
夫々等しい抵抗値にし、さらにコンデンサＣ1 とコンデ
ンサＣ2 、コンデンサＣ3 とコンデンサＣ4 を夫々等し
い容量とする正帰還アクティブＬＰＦが演算増幅器２に
設けられて、この回路の増幅率、遮断周波数およびＱ値
を定めて、各素子の大小値関係を決定している。Thus, the resistors R 1 and R 2 , the resistors R 3 and R 4, and the resistors R 5 and R 6 have the same resistance value, and the capacitors C 1 and C 2 , a positive feedback active LPF having the same capacitance as the capacitor C 3 and the capacitor C 4 is provided in the operational amplifier 2, and the amplification factor, cutoff frequency and Q value of this circuit are determined to determine the magnitude relationship between the respective elements. I have decided.
【００１９】この場合、従来ＬＰＦを構成していた演算
増幅器の数が低減し、その構成が簡素化されるとととも
に信号処理規模が縮小されて消費電流が減少することに
なる。In this case, the number of operational amplifiers that have conventionally constituted the LPF is reduced, the configuration is simplified, the signal processing scale is reduced, and the current consumption is reduced.
【００２０】図２は、第２の実施例の構成を示してい
る。この例は、例えば、ＣＤオーディオ装置に適用する
場合の実施例であり、１ｂｉｔＤＡＣから、入力端子Ｔ
i1，Ｔi2に夫々ＰＷＭプラス・マイナス信号が供給され
ている。１ｂｉｔＤＡＣは時間軸方向に高精度な分解能
を有するＰＷＭ（パルス幅変調）方式を採用しており、
アナログ信号に変換する積分回路が必要である。またオ
ーバーサンプリング技術とノイズシェーピング技術を用
いて１６ｂｉｔのデータを数ｂｉｔにｂｉｔ圧縮しなが
ら量子化ノイズを可聴周波数から高周波数に形成してい
るため、ノイズ除去用のＬＰＦが必要となる。FIG. 2 shows the configuration of the second embodiment. This example is an example in the case of being applied to a CD audio device, for example, from the 1-bit DAC to the input terminal T
PWM plus / minus signals are supplied to i1 and T i2 , respectively. The 1-bit DAC uses a PWM (pulse width modulation) method that has a highly accurate resolution in the time axis direction,
An integrating circuit for converting into an analog signal is required. Further, since the quantization noise is formed from the audible frequency to the high frequency while compressing 16-bit data into several bits by using the oversampling technique and the noise shaping technique, an LPF for noise removal is required.
【００２１】このため、図２に示すように、第１の実施
例の構成（図１）の前段に、ＰＷＭプラス・マイナス信
号が入力端子Ｔi1、Ｔi2を通じて、夫々の一端に供給さ
れる抵抗器Ｒ8 、抵抗器Ｒ9 を設けるとともに、これら
の他端間にコンデンサＣ5 （ＣX ）を接続した構成の積
分回路４を付加している。この場合、Ｒ8 ＝Ｒ9 ＝Ｒ X
とし、全体として３次のＬＰＦで構成されており、演算
増幅器２から出力端子ＴO を通じてオーディオ出力信号
ＶAOが出力される。For this reason, as shown in FIG.
The PWM plus / minus signal is added before the example configuration (Fig. 1).
No. is the input terminal Ti1, Ti2Through one end of each
Resistor R8, Resistor R9Together with these
Between the other end of the capacitor CFive(CX) Connected configurations
The branch circuit 4 is added. In this case, R8= R9= R X
And is composed of a third-order LPF as a whole,
Output terminal T from amplifier 2OThrough audio output signal
VAOIs output.
【００２２】次に、第２の実施例における動作について
説明する。この回路の伝達関数は、Next, the operation of the second embodiment will be described. The transfer function of this circuit is
【００２３】[0023]
【数５】 [Equation 5]
【００２４】で表される。遮断周波数は、可聴周波数よ
り高く設定するため可聴帯域内での伝達関数は、It is represented by Since the cutoff frequency is set higher than the audible frequency, the transfer function in the audible band is
【００２５】[0025]
【数６】 [Equation 6]
【００２６】で表され、利得はＲX ，ＲA ，ＲB の和と
ＲC の比で任意に設定することができる。The gain can be arbitrarily set by the ratio of the sum of R X , R A and R B and R C.
【００２７】このように、例えば、携帯用ＣＤオーディ
オ装置における１ｂｉｔＤＡＣからのＰＷＭプラス・マ
イナス信号を処理する際に、積分およびノイズ除去が夫
々できることになる。この場合、回路を構成する素子数
が低減されるため信号劣化が生じ難くなり、音質が向上
するとともに消費電流ならびに部品点数が減少して小型
化および長時間使用が可能となり、携帯の利便性が向上
するものとなる。Thus, for example, when processing the PWM plus / minus signal from the 1-bit DAC in a portable CD audio device, integration and noise removal can be performed respectively. In this case, since the number of elements constituting the circuit is reduced, signal deterioration is less likely to occur, the sound quality is improved, and the current consumption and the number of parts are reduced, which enables downsizing and long-term use, which is convenient for carrying. It will be improved.
【００２８】[0028]
【発明の効果】上記説明から理解されるように、本発明
のＬＰＦ内蔵差動増幅回路によれば、差動増幅器に正帰
還をかけた抵抗器及びコンデンサからなるアクティブＬ
ＰＦが設けられているため、演算増幅器の数が低減し、
その構成が簡素化できるととともに信号処理規模が縮小
されて、消費電流が低減できるという効果を有する。As can be understood from the above description, according to the differential amplifier circuit with a built-in LPF of the present invention, an active L comprising a resistor and a capacitor in which positive feedback is applied to the differential amplifier.
Since the PF is provided, the number of operational amplifiers is reduced,
This has the effect that the configuration can be simplified, the signal processing scale can be reduced, and the current consumption can be reduced.
【００２９】加えて、当該ＬＰＦ内蔵差動増幅回路を携
帯用ＣＤオーディオ装置等に適用する場合、回路を構成
する素子数が低減されるため信号波形の劣化が生じ難く
なり、音質が向上するとともに消費電流ならびに部品点
数が減少して小型化および長時間使用が可能となり、携
帯の利便性が向上するという効果を有する。In addition, when the LPF built-in differential amplifier circuit is applied to a portable CD audio device or the like, the number of elements constituting the circuit is reduced, so that the signal waveform is less likely to deteriorate and the sound quality is improved. The current consumption and the number of parts are reduced, which enables miniaturization and long-time use, and has the effect of improving the convenience of carrying.
【図１】本発明のＬＰＦ内蔵差動増幅回路の第１の実施
例の構成を示す回路図である。FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a differential amplifier circuit with a built-in LPF of the present invention.
【図２】本発明のＬＰＦ内蔵差動増幅回路の第２の実施
例の構成を示す回路図である。FIG. 2 is a circuit diagram showing a configuration of a second embodiment of an LPF built-in differential amplifier circuit of the present invention.
２ 演算増幅器 Ｃ1 、Ｃ2 、Ｃ3 、Ｃ4 、Ｃ5 コンデンサ Ｒ1 、Ｒ2 、Ｒ3 、Ｒ4 、Ｒ5、Ｒ6 、Ｒ8 、Ｒ9 抵
抗器 ＶA 、ＶB 入力信号（電圧） ＶO 出力信号（電圧）Second operational amplifier C 1, C 2, C 3 , C 4, C 5 capacitors R 1, R 2, R 3 , R 4, R 5, R 6, R 8, R 9 resistors V A, V B input signal (Voltage) VO output signal (Voltage)
Claims (1)
の直列回路を介して演算増幅器の非反転入力端に接続
し、上記第１及び第２の抵抗器の接続点を第１のコンデ
ンサを介して上記演算増幅器の出力端に接続し、上記演
算増幅器の非反転入力端を第３の抵抗器及び第２のコン
デンサの並列回路を介して接地すると共に他方の入力端
子を上記第１の抵抗器と抵抗値の等しい第４の抵抗器及
び上記第２の抵抗器と抵抗値の等しい第５の抵抗器の直
列回路を介して上記演算増幅器の反転入力端に接続し、
上記第４及び第５の抵抗器の接続点を上記第１のコンデ
ンサと容量値の等しい第３のコンデンサを介して接地
し、上記演算増幅器の反転入力端を上記第３の抵抗器と
抵抗値の等しい第６の抵抗器及び上記第２のコンデンサ
と容量値の等しい第４のコンデンサの並列回路を介して
上記演算増幅器の出力端に接続し、増幅率、遮断周波数
及びＱ値を定めて上記各抵抗器及びコンデンサの大小関
係を決定するようにしたことを特徴とするローパスフィ
ルタ内蔵差動増幅回路。Claim: What is claimed is: 1. One input terminal is connected to a non-inverting input terminal of an operational amplifier via a series circuit of first and second resistors, and the first and second resistors are connected. Is connected to the output terminal of the operational amplifier via the first capacitor, and the non-inverting input terminal of the operational amplifier is grounded via the parallel circuit of the third resistor and the second capacitor and The input terminal of the operational amplifier is connected through a series circuit of a fourth resistor having the same resistance value as the first resistor and a fifth resistor having the same resistance value as the second resistor. Connect to
The connection point of the fourth and fifth resistors is grounded via a third capacitor having the same capacitance value as the first capacitor, and the inverting input terminal of the operational amplifier is connected to the third resistor and the resistance value. Is connected to the output terminal of the operational amplifier through a parallel circuit of a sixth resistor having the same value and a fourth capacitor having the same value as the second capacitor, and the amplification factor, cutoff frequency and Q value are determined and A differential amplifier circuit with a built-in low-pass filter, wherein the magnitude relationship between each resistor and capacitor is determined.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3171303A JP3060611B2 (en) | 1991-07-11 | 1991-07-11 | Differential amplifier circuit with built-in low-pass filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3171303A JP3060611B2 (en) | 1991-07-11 | 1991-07-11 | Differential amplifier circuit with built-in low-pass filter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0522077A true JPH0522077A (en) | 1993-01-29 |
| JP3060611B2 JP3060611B2 (en) | 2000-07-10 |
Family
ID=15920784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3171303A Expired - Fee Related JP3060611B2 (en) | 1991-07-11 | 1991-07-11 | Differential amplifier circuit with built-in low-pass filter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3060611B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7482871B2 (en) | 2006-01-09 | 2009-01-27 | Samsung Electronics Co., Ltd. | CMOS amplifier of filter for ultra wideband application and method of the same |
| JP2011130318A (en) * | 2009-12-21 | 2011-06-30 | Onkyo Corp | Filter circuit |
| JP2015111153A (en) * | 2015-03-03 | 2015-06-18 | プライムアースＥｖエナジー株式会社 | Voltage detection circuit |
-
1991
- 1991-07-11 JP JP3171303A patent/JP3060611B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7482871B2 (en) | 2006-01-09 | 2009-01-27 | Samsung Electronics Co., Ltd. | CMOS amplifier of filter for ultra wideband application and method of the same |
| JP2011130318A (en) * | 2009-12-21 | 2011-06-30 | Onkyo Corp | Filter circuit |
| US8018273B2 (en) | 2009-12-21 | 2011-09-13 | Onkyo Corporation | Filter circuit |
| JP2015111153A (en) * | 2015-03-03 | 2015-06-18 | プライムアースＥｖエナジー株式会社 | Voltage detection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3060611B2 (en) | 2000-07-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |