JPH05218796A - Carrier balance conversion circuit - Google Patents

Carrier balance conversion circuit

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Publication number
JPH05218796A
JPH05218796A JP1968592A JP1968592A JPH05218796A JP H05218796 A JPH05218796 A JP H05218796A JP 1968592 A JP1968592 A JP 1968592A JP 1968592 A JP1968592 A JP 1968592A JP H05218796 A JPH05218796 A JP H05218796A
Authority
JP
Japan
Prior art keywords
conversion circuit
carrier balance
phase
circuit
balance conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1968592A
Other languages
Japanese (ja)
Inventor
Masao Mineo
将穂 峰尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1968592A priority Critical patent/JPH05218796A/en
Publication of JPH05218796A publication Critical patent/JPH05218796A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To eliminate the need for phase correction due to application of an offset voltage or the like. CONSTITUTION:A wire pattern 80 on an IC chip is a wire pattern for signal lines through which one of bipolar signals outputted from the carrier balance conversion circuit passes to a multiplier circuit and a wire pattern 90 is a wire pattern for signal lines used to supply the other of the bipolar signals to the multiplier circuit. Then the former is shorter than the latter, the width of the pattern of the former is wider and the area of both the patterns is equal to each other. Thus, the parasitic capacitance of the wire patterns 80, 90 is equal to each other, then the bipolar signal with excellent balance is fed to the multiplier circuit and it is not required to apply phase correction through the application of the offset voltage different from a conventional conversion circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、単相信号を入力とし、
位相差が180度の両相信号を出力するIC化キャリア
バランス変換回路に関するものである。
BACKGROUND OF THE INVENTION The present invention uses a single-phase signal as an input,
The present invention relates to an IC carrier balance conversion circuit that outputs a two-phase signal having a phase difference of 180 degrees.

【0002】[0002]

【従来の技術】図3にこの種の従来のキャリアバランス
変換回路を用いたアナログ乗算回路の一例を示す。この
回路は、キャリアバランス変換回路10と、乗算器回路
20とによって構成されている。キャリアバランス変換
回路10は、端子1より入力された単相の局部信号をも
とに、位相差が180度の両相信号を生成し、その両相
信号の各信号を信号線6,7を通じて乗算器回路20に
出力する。そして、乗算器回路20は、端子2から入力
されたベースバンド信号と、キャリアバランス変換回路
10からの上記両相信号とを乗算し、乗算信号を端子5
に出力する。
2. Description of the Related Art FIG. 3 shows an example of an analog multiplication circuit using a conventional carrier balance conversion circuit of this type. This circuit is composed of a carrier balance conversion circuit 10 and a multiplier circuit 20. The carrier balance conversion circuit 10 generates a two-phase signal having a phase difference of 180 degrees based on the single-phase local signal input from the terminal 1, and outputs each signal of the both-phase signals through the signal lines 6 and 7. Output to the multiplier circuit 20. Then, the multiplier circuit 20 multiplies the baseband signal input from the terminal 2 by the two-phase signal from the carrier balance conversion circuit 10 and outputs the multiplication signal to the terminal 5
Output to.

【0003】このアナログ乗算回路では、回路の対称性
にもかかわらず、ICチップ上の回路パターンは必ずし
も対称となっていない。例えば、点A,A’を結ぶ信号
線6の配線パターン、および点B,B’を結ぶ信号線7
の配線パターンは、ICチップ上ではそれぞれ図4に示
すパターン8,9のようになっている。パターンの長さ
がこのように異なると、それに付随する寄生容量Cの値
も異なったものとなり、その結果、信号のバランスがく
ずれ、キャリアバランス変換回路10から乗算器回路2
0に与えられる両相信号の質が低下する。
In this analog multiplication circuit, the circuit pattern on the IC chip is not always symmetrical, despite the symmetry of the circuit. For example, the wiring pattern of the signal line 6 connecting the points A and A ′ and the signal line 7 connecting the points B and B ′
On the IC chip, the wiring patterns of are as shown in patterns 8 and 9 of FIG. 4, respectively. If the pattern lengths differ in this way, the values of the parasitic capacitances C associated therewith also become different, and as a result, the signal balance is lost, and the carrier balance conversion circuit 10 to the multiplier circuit 2
The quality of the two-phase signal given to 0 deteriorates.

【0004】配線パターン8,9の寄生容量Cの値がそ
れぞれ266fF,304fFであるとし、ベースバン
ド信号を直流電圧として、図3のアナログ乗算回路の振
幅位相特性をシミュレーションによる求めると、結果は
図5のグラフようになる。このグラフから分かるよう
に、ベースバンド電圧が正の場合と負の場合とで0−π
位相のずれが生じている。一方、図6のグラフは、配線
パターン8,9に寄生容量がないとした場合のシミュレ
ーション結果であり、ベースバンド電圧が正および負の
場合で、振幅特性および位相特性に差はない。ただし、
いずれの場合も局部信号の周波数は1.5GHzとし
た。
When the parasitic capacitances C of the wiring patterns 8 and 9 are 266 fF and 304 fF, respectively, and the baseband signal is a DC voltage, the amplitude / phase characteristic of the analog multiplication circuit of FIG. It becomes like the graph of 5. As can be seen from this graph, 0-π depending on whether the baseband voltage is positive or negative.
There is a phase shift. On the other hand, the graph of FIG. 6 is a simulation result when there is no parasitic capacitance in the wiring patterns 8 and 9, and there is no difference in amplitude characteristic and phase characteristic when the baseband voltage is positive and negative. However,
In each case, the frequency of the local signal was 1.5 GHz.

【0005】[0005]

【発明が解決しようとする課題】従来は、このような寄
生容量の値の差に伴う特性の劣化を防止するため、局部
信号の入力端子4、あるいはベースバンド信号の入力端
子2,3に、図3のように、オフセット電圧を加えてト
ランジスタの動作点を変え、バイアスバランスを崩して
位相補正を行っていた。特に高周波においてはこのよう
な位相補正が必要であった。
Conventionally, in order to prevent the characteristic deterioration due to the difference in the value of the parasitic capacitance, the local signal input terminal 4 or the baseband signal input terminals 2 and 3 are provided with As shown in FIG. 3, the offset voltage is applied to change the operating point of the transistor, and the bias balance is destroyed to perform the phase correction. Especially at high frequencies, such phase correction was necessary.

【0006】本発明の目的は、このような問題を解決
し、位相補正を行う必要のないキャリアバランス変換回
路を提供することにある。
An object of the present invention is to solve such a problem and to provide a carrier balance conversion circuit which does not require phase correction.

【0007】[0007]

【課題を解決するための手段】本発明は、単相信号を入
力とし、位相差が180度の両相信号を出力するIC化
キャリアバランス変換回路において、前記両相信号の各
信号がそれぞれ通過する回路部分に関連した寄生容量の
値を実質的に等しくしたことを特徴とする。
According to the present invention, in an IC carrier balance conversion circuit which inputs a single-phase signal and outputs a two-phase signal having a phase difference of 180 degrees, each of the two-phase signals passes through. It is characterized in that the values of the parasitic capacitances related to the circuit parts to be made substantially equal.

【0008】[0008]

【実施例】次に本発明の実施例について図面を参照して
説明する。図1に本発明によるキャリアバランス変換回
路のICチップにおける配線パターンの一部を示す。キ
ャリアバランス変換回路の回路そのものは図3の回路と
同一であり、キャリアバランス変換回路10が出力する
両相信号の各信号は、それぞれ信号線6,7を通じて乗
算器回路20に供給される。そして、このキャリアバラ
ンス変換回路では、点Aおよび点A’を接続する信号線
6の配線パターン80は、点Bおよび点B’を接続する
信号線7の配線パターン90より太くなっており、両配
線パターンの面積は一致している。そのため、配線パタ
ーン80の寄生容量の値と配線パターン90の寄生容量
の値も一致している。従って、このキャリアバランス変
換回路では、信号のバランスが崩れることがなく、質の
高い両相信号が乗算器回路20に供給される。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows a part of a wiring pattern in an IC chip of a carrier balance conversion circuit according to the present invention. The circuit itself of the carrier balance conversion circuit is the same as the circuit of FIG. 3, and the respective signals of the two-phase signals output from the carrier balance conversion circuit 10 are supplied to the multiplier circuit 20 through the signal lines 6 and 7, respectively. In this carrier balance conversion circuit, the wiring pattern 80 of the signal line 6 connecting the points A and A ′ is thicker than the wiring pattern 90 of the signal line 7 connecting the points B and B ′. The areas of the wiring patterns are the same. Therefore, the value of the parasitic capacitance of the wiring pattern 80 and the value of the parasitic capacitance of the wiring pattern 90 also match. Therefore, in this carrier balance conversion circuit, high-quality two-phase signals are supplied to the multiplier circuit 20 without losing the signal balance.

【0009】例えば、配線パターン80,90の寄生容
量の値を304fFに一致させ、ベースバンド信号を直
流電圧として、図3のアナログ乗算回路の振幅位相特性
をシミュレーションによる求めると、結果は図2のグラ
フようになる。すなわち、ベースバンド電圧が正の場合
と負の場合とで0−π位相のずれが縮小し、図6に示し
た寄生容量が無いとした場合の位相振幅特性とほぼ同じ
結果となっている。従って、本実施例のキャリアバラン
ス変換回路では、高周波まで両相信号のバランス性が保
たれ、オフセット電圧の印加などによる位相補正は不要
となる。
For example, when the parasitic capacitance values of the wiring patterns 80 and 90 are made equal to 304 fF and the baseband signal is a DC voltage, the amplitude / phase characteristic of the analog multiplication circuit of FIG. 3 is obtained by simulation, and the result is shown in FIG. It looks like a graph. That is, the 0-π phase shift is reduced depending on whether the baseband voltage is positive or negative, and the result is substantially the same as the phase amplitude characteristic in the case where there is no parasitic capacitance shown in FIG. Therefore, in the carrier balance conversion circuit of the present embodiment, the balance property of both phase signals is maintained up to a high frequency, and the phase correction by applying the offset voltage or the like becomes unnecessary.

【0010】[0010]

【発明の効果】以上説明したように本発明のキャリアバ
ランス変換回路では、両相信号の各信号がそれぞれ通過
する回路部分に関連した寄生容量の値を実質的に等しく
したので、高周波まで両相信号のバランス性が保たれ、
配線パターンに寄生容量がないとした場合と同様の特性
が得られる。従って、オフセット電圧の印加などによる
位相補正は不要となる。
As described above, in the carrier balance conversion circuit of the present invention, the values of the parasitic capacitances related to the circuit portions through which the respective signals of the two-phase signals pass are made substantially equal, so that the two-phase signals up to a high frequency can be obtained. Signal balance is maintained,
The same characteristics as when the wiring pattern has no parasitic capacitance are obtained. Therefore, it is not necessary to correct the phase by applying an offset voltage or the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明によるキャリアバランス変換回路のIC
チップにおける配線パターンの一部を示す平面図であ
る。
FIG. 1 is an IC of a carrier balance conversion circuit according to the present invention.
It is a top view which shows a part of wiring pattern in a chip.

【図2】本発明の一実施例のキャリアバランス変換回路
を用いて構成したアナログ乗算回路の位相振幅特性をシ
ミュレーションにより求めた結果を示すグラフである。
FIG. 2 is a graph showing a result obtained by simulating a phase amplitude characteristic of an analog multiplication circuit configured using the carrier balance conversion circuit according to the exemplary embodiment of the present invention.

【図3】キャリアバランス変換回路を用いて構成したア
ナログ乗算回路の一例を示す回路図である。
FIG. 3 is a circuit diagram showing an example of an analog multiplication circuit configured using a carrier balance conversion circuit.

【図4】従来のキャリアバランス変換回路のICチップ
における配線パターンの一部を示す平面図である。
FIG. 4 is a plan view showing a part of a wiring pattern in an IC chip of a conventional carrier balance conversion circuit.

【図5】従来のキャリアバランス変換回路を用いて構成
したアナログ乗算回路の位相振幅特性をシミュレーショ
ンにより求めた結果を示すグラフである。
FIG. 5 is a graph showing a result obtained by simulating a phase amplitude characteristic of an analog multiplication circuit configured using a conventional carrier balance conversion circuit.

【図6】キャリアバランス変換回路を用いて構成したア
ナログ乗算回路の位相振幅特性を理想条件でシミュレー
ションにより求めた結果を示すグラフである。
FIG. 6 is a graph showing a result obtained by simulating the phase-amplitude characteristics of an analog multiplication circuit configured using a carrier balance conversion circuit under ideal conditions.

【符号の説明】[Explanation of symbols]

1〜5 端子 6,7 信号線 10 キャリアバランス変換回路 20 乗算器回路 80,90 配線パターン 1 to 5 terminals 6, 7 signal line 10 carrier balance conversion circuit 20 multiplier circuit 80, 90 wiring pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】単相信号を入力とし、位相差が180度の
両相信号を出力するIC化キャリアバランス変換回路に
おいて、 前記両相信号の各信号がそれぞれ通過する回路部分に関
連した寄生容量の値を実質的に等しくしたことを特徴と
するキャリアバランス変換回路。
1. An IC carrier balance conversion circuit for inputting a single-phase signal and outputting both-phase signals having a phase difference of 180 degrees, wherein a parasitic capacitance associated with a circuit portion through which each of the two-phase signals passes. A carrier balance conversion circuit characterized in that the values of are substantially equal.
JP1968592A 1992-02-05 1992-02-05 Carrier balance conversion circuit Pending JPH05218796A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1968592A JPH05218796A (en) 1992-02-05 1992-02-05 Carrier balance conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1968592A JPH05218796A (en) 1992-02-05 1992-02-05 Carrier balance conversion circuit

Publications (1)

Publication Number Publication Date
JPH05218796A true JPH05218796A (en) 1993-08-27

Family

ID=12006096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1968592A Pending JPH05218796A (en) 1992-02-05 1992-02-05 Carrier balance conversion circuit

Country Status (1)

Country Link
JP (1) JPH05218796A (en)

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