JPH05218263A - Lead frame and resin-molded semiconductor device using same - Google Patents

Lead frame and resin-molded semiconductor device using same

Info

Publication number
JPH05218263A
JPH05218263A JP1640992A JP1640992A JPH05218263A JP H05218263 A JPH05218263 A JP H05218263A JP 1640992 A JP1640992 A JP 1640992A JP 1640992 A JP1640992 A JP 1640992A JP H05218263 A JPH05218263 A JP H05218263A
Authority
JP
Japan
Prior art keywords
resin
die pad
lead frame
semiconductor device
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1640992A
Other languages
Japanese (ja)
Other versions
JP3134445B2 (en
Inventor
Kinshi Kako
欣志 加来
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP1640992A priority Critical patent/JP3134445B2/en
Publication of JPH05218263A publication Critical patent/JPH05218263A/en
Application granted granted Critical
Publication of JP3134445B2 publication Critical patent/JP3134445B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent generation of package cracks. CONSTITUTION:A lead frame 3A constituted of a die pad 4 and inner leads 5 and outer leads 6 which are formed in the peripheral part of the die pad 4. A thin stripe protrusion 20 is formed between the inner leads 5. The protrusion 20 is so exposed that the same surface as the side surface of a package 11 formed by sealing resin 10 is constituted, and forms a vapor pressure reducing means. Since the die pad is exposed to the outer space via the thin stripe protrusion, the pressure of water vapor which is generated by heating water content existing in the vicinity of the die pad when a resin-molded semiconductor device is packaged can be reduced. Hence generation of package crack due to vapor pressure can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、水蒸気によるパッケ
ージクラックの発生を防止する対策が施された樹脂封止
型半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device provided with measures for preventing the occurrence of package cracks due to water vapor.

【0002】[0002]

【従来の技術】図4及び図5を用いて従来技術のリード
フレーム及び樹脂封止型半導体装置を説明する。図4は
従来技術の一構成単位のリードフレームの平面図を示
し、図5は図4に示したリードフレームを用い、A−A
線上から見た従来技術の樹脂封止型半導体装置の断面図
を示す。
2. Description of the Related Art A conventional lead frame and resin-sealed semiconductor device will be described with reference to FIGS. FIG. 4 is a plan view of a lead frame which is one structural unit of the prior art, and FIG. 5 uses the lead frame shown in FIG.
1 is a cross-sectional view of a conventional resin-encapsulated semiconductor device viewed from above.

【0003】従来技術のリードフレーム3は、ダイパッ
ド4と、この周辺部に所定の配列で配置されたインナー
リード5と、これらに対応したアウターリード6などと
を一構成単位とし、この一単位を複数形成して構成され
ている。符号7はダイパッド4の両端を各ステー8に接
続している吊りであって、これらの吊り7の斜線を施し
た部分で折り曲げられ、ダイパッド4はディプレスされ
ている。
The lead frame 3 of the prior art has a die pad 4, an inner lead 5 arranged in a predetermined arrangement around the die pad 4, an outer lead 6 corresponding to the die pad 4, and the like as one unit. It is configured by forming a plurality. Reference numeral 7 is a suspension that connects both ends of the die pad 4 to each stay 8, and is bent at the shaded portions of these suspensions 7, and the die pad 4 is depressed.

【0004】このようなリードフレーム3のダイパッド
4に半導体チップ2を銀ペーストなどを用いてダイボン
ドし、図示していないが半導体チップ2の各電極を各イ
ンナーリード5に金、アルミなどのワイヤ9で接続し、
エポキシ樹脂のような封止樹脂10でモールドし、硬化
させ、パッケージ11としている。封止樹脂10が硬化
した後、ステー8を吊り7の部分で切断し、同時に各ア
ウターリード6を所定の長さ及び形状に切断し、曲げ加
工を施すと、図5に示したような構成の樹脂封止型半導
体装置1となる。
The semiconductor chip 2 is die-bonded to the die pad 4 of the lead frame 3 using silver paste or the like, and each electrode of the semiconductor chip 2 is connected to each inner lead 5 by a wire 9 of gold, aluminum or the like, which is not shown. Connect with
A package 11 is obtained by molding with a sealing resin 10 such as epoxy resin and curing. After the sealing resin 10 is hardened, the stay 8 is cut at the portion of the suspension 7, and at the same time, each outer lead 6 is cut into a predetermined length and shape, and subjected to a bending process. The resin-encapsulated semiconductor device 1 is obtained.

【0005】[0005]

【発明が解決しようとする課題】しかし、このような樹
脂封止型半導体装置1は、外界から吸湿した水分等が封
止樹脂10内を拡散により広がり、ダイパッド4の裏面
に集まり、このような状態の樹脂封止型半導体装置1を
電気回路配線基板に実装すると、その際に加えられる熱
によって、その水分等が蒸気となり、その蒸気圧が高ま
り、その蒸気がパッケージ11を破壊する、所謂パッケ
ージクラックが発生する。この発明では、このようなパ
ッケージクラックの発生を防止することを目的とするも
のである。
However, in such a resin-encapsulated semiconductor device 1, moisture absorbed from the outside spreads in the encapsulation resin 10 by diffusion and collects on the back surface of the die pad 4, When the resin-encapsulated semiconductor device 1 in the state is mounted on an electric circuit wiring board, the heat applied at that time causes the moisture or the like to turn into steam, and the steam pressure increases, so that the steam destroys the package 11. Cracks occur. The present invention aims to prevent the occurrence of such package cracks.

【0006】[0006]

【課題を解決するための手段】それ故、この発明の樹脂
封止型半導体装置では、ダイパッドとその周辺に配置し
た複数のインナーリードとこれらと対応したアウターリ
ードとそれらのインナーリードの間に複数の細条突起か
らなる蒸気減圧手段を形成したリードフレームの、前記
ダイパッドに半導体チップを搭載して、封止樹脂でパッ
ケージした場合に、前記蒸気減圧手段がそのパッケージ
の表面に露出させるように構成した。
Therefore, in the resin-sealed semiconductor device of the present invention, a plurality of inner leads arranged around the die pad, outer leads corresponding to these die pads, and the inner leads are provided. When the semiconductor chip is mounted on the die pad of the lead frame having the vapor pressure reducing means composed of the striped protrusions and packaged with the sealing resin, the vapor pressure reducing means is exposed on the surface of the package. did.

【0007】[0007]

【作用】従って、前記の蒸気をこれらの露出した蒸気減
圧手段を通じて減圧することができる。
Therefore, the vapor can be decompressed through these exposed vapor decompressing means.

【0008】[0008]

【実施例】以下、この発明のリードフレーム及び樹脂封
止型半導体装置を図を用いて説明する。図1はこの発明
の一構成単位のリードフレームの一実施例を示した平面
図であり、図2は図1に示したリードフレームを用い、
A−A線上から見たこの発明の樹脂封止型半導体装置の
断面図であり、そして図3は図1のリードフレームに搭
載した半導体チップを樹脂封止する場合の状態を説明す
るための断面図である。なお、図4及び図5に示したリ
ードフレーム及び樹脂封止型半導体装置と同一の構成部
分には同一の符号を付し、それらの構成及び説明を省略
する。そして、この実施例ではSOP型樹脂封止型半導
体装置を採り挙げたが、この発明はQFP型等のものに
も適用できることを付言しておく。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A lead frame and a resin-sealed semiconductor device of the present invention will be described below with reference to the drawings. 1 is a plan view showing an embodiment of a lead frame which is one structural unit of the present invention, and FIG. 2 uses the lead frame shown in FIG.
FIG. 3 is a cross-sectional view of the resin-encapsulated semiconductor device of the present invention seen from the AA line, and FIG. 3 is a cross-section for explaining the state when the semiconductor chip mounted on the lead frame of FIG. 1 is resin-encapsulated. It is a figure. The same components as those of the lead frame and the resin-sealed semiconductor device shown in FIGS. 4 and 5 are designated by the same reference numerals, and their configuration and description will be omitted. Although the SOP type resin-encapsulated semiconductor device is used in this embodiment, it should be added that the present invention can be applied to QFP type devices.

【0009】先ず、この発明の一つのリードフレーム3
Aを説明する。この発明のリードフレーム3Aにおいて
は、図1に示したように、インナーリード5の間に位置
するように、ダイパッド4に連なって細条突起20を形
成した。細条突起20はできるだけ多く形成することが
望ましく、この実施例では吊り7の近傍に形成されたイ
ンナーリード5を除いた他のダイパッド4の側縁部に等
間隔で配列されたインナーリード5の全ての間に形成し
た。
First, one lead frame 3 of the present invention.
A will be described. In the lead frame 3A of the present invention, as shown in FIG. 1, the strip projections 20 are formed so as to be located between the inner leads 5 so as to be continuous with the die pad 4. It is desirable to form as many strip protrusions 20 as possible, and in this embodiment, the inner leads 5 arranged at equal intervals on the side edges of the other die pads 4 except the inner leads 5 formed near the suspension 7. Formed between all.

【0010】この細条突起20はできるだけ弱く構成す
ることが望ましく、細くそしてハーフエッチングすると
よい。細条突起20のダイパッド4と連なっている基部
21はV字型に形成して、その細条突起20をしっかり
保持する構造にした。
It is desirable that the strip projections 20 are made as weak as possible, and they are preferably thin and half-etched. The base portion 21 of the strip projection 20 which is continuous with the die pad 4 is formed in a V shape so as to firmly hold the strip projection 20.

【0011】また、細条突起20の長さは、後述するよ
うに樹脂封止すると、その先端部22が多少撓んでパッ
ケージ11の表面12と同一面を形成するように露出で
きる長さとし、特別に切断する必要がないように構成し
た。このように構成すると、リードフレームの構成を変
更するだけで、従来技術で使用された各種設備を流用す
ることができる。この細条突起20はダイパッド4を外
界に晒すものであれば、形状、構造は問わない。
Further, the length of the strip projection 20 is such that, when it is sealed with resin as will be described later, the tip portion 22 of the strip projection 20 is slightly bent so that it can be exposed so as to form the same surface as the surface 12 of the package 11. Configured so that there is no need to disconnect. With this configuration, it is possible to use the various equipment used in the related art simply by changing the configuration of the lead frame. The strip projection 20 may have any shape and structure as long as it exposes the die pad 4 to the outside.

【0012】このようなリードフレーム3Aのダイパッ
ド4に半導体チップ2を銀ペースト等でダイボンドし、
半導体チップ2の各電極を各インナーリード5にワイヤ
9で接続し、封止樹脂10でモールドする。
The semiconductor chip 2 is die-bonded to the die pad 4 of the lead frame 3A with silver paste or the like,
Each electrode of the semiconductor chip 2 is connected to each inner lead 5 with a wire 9, and is molded with a sealing resin 10.

【0013】この場合、図3に示したように、下金型3
0の内側壁32に細条突起20が当接するように、半導
体チップ2を搭載したリードフレーム3Aを下金型30
に入れる。細条突起20は前述のような長さ等の構造に
定めてあるので、これらの細条突起20は、殆ど全体の
自重で下がり、細条突起20は上方に僅かに撓む。
In this case, as shown in FIG. 3, the lower mold 3
The lead frame 3A on which the semiconductor chip 2 is mounted is attached to the lower mold 30 so that the strip protrusions 20 come into contact with the inner wall 32 of the lower mold 30.
Put in. Since the strip projections 20 are defined by the structure such as the length as described above, the strip projections 20 are lowered by almost the entire weight of the strip projections 20 and the strip projections 20 are slightly bent upward.

【0014】このように配置した後、上金型31を被せ
て、この金型に封止樹脂10を注入し、トランスファー
モールドする。モールドの範囲は、図1の2点鎖線Lで
囲んだ内部である。
After arranging as described above, the upper mold 31 is covered, and the sealing resin 10 is injected into this mold and transfer molding is performed. The range of the mold is the inside surrounded by the chain double-dashed line L in FIG.

【0015】そうすると、前記細条突起20の先端部2
2はパッケージ11の側面12と同一面を形成し、外界
に露出するので、ダイパッド4を外界に晒す状態になる
ので、前記水分等による蒸気をダイパッド4及び複数の
細条突起20と封止樹脂10との極僅かな隙間を通じて
外界に放出することができる。この実施例ではこの細条
突起20とこのパッケージ11の側面12とで蒸気減圧
手段が構成されている。
Then, the tip portion 2 of the strip projection 20 is formed.
2 forms the same surface as the side surface 12 of the package 11 and is exposed to the outside world, so that the die pad 4 is exposed to the outside world. Therefore, the vapor due to the moisture or the like is used for the die pad 4 and the plurality of strip projections 20 and the sealing resin. It can be released to the outside through a very small gap with 10. In this embodiment, the strip projection 20 and the side surface 12 of the package 11 constitute a vapor pressure reducing means.

【0016】封止樹脂10が硬化すると、アウターリー
ド6を所定の長さ及び形状に切断し、曲げ加工を施す
と、この発明の樹脂封止型半導体装置1Aを得ることが
できる。
When the encapsulating resin 10 is hardened, the outer leads 6 are cut into a predetermined length and shape and subjected to a bending process to obtain the resin-encapsulated semiconductor device 1A of the present invention.

【0017】[0017]

【発明の効果】以上の説明から明らかなように、この発
明の樹脂封止型半導体装置は、外界から吸湿した水分等
が封止樹脂内を拡散によりダイパッドの裏面に集めら
れ、このような樹脂封止型半導体装置を電気回路配線基
板に実装した場合に、その時の熱でその水分等が加熱さ
れ、水蒸気となり、圧力が高められたとしても、前記蒸
気減圧手段により減圧することができ、従来技術に見ら
れたようなパッケージクラックが発生しにくくなる。ま
た、この発明では、リードフレームの構成を変更するだ
けで、従来技術に用いた製造設備を流用することができ
るので、製造コストには響かないなどという優れた効果
がある。
As is apparent from the above description, in the resin-encapsulated semiconductor device of the present invention, moisture or the like absorbed from the outside is diffused in the encapsulating resin and collected on the back surface of the die pad. When the encapsulated semiconductor device is mounted on an electric circuit wiring board, the moisture and the like are heated by the heat at that time to become water vapor, and even if the pressure is increased, the pressure can be reduced by the vapor pressure reducing means. The package cracks as seen in the technology are less likely to occur. Further, according to the present invention, since the manufacturing equipment used in the prior art can be used simply by changing the structure of the lead frame, there is an excellent effect that it does not affect the manufacturing cost.

【0018】[0018]

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一構成単位のリードフレームの一実
施例を示した平面図である。
FIG. 1 is a plan view showing an embodiment of a lead frame which is one structural unit of the present invention.

【図2】図1に示したリードフレームを用い、A−A線
上から見たこの発明の樹脂封止型半導体装置の断面図で
ある。
FIG. 2 is a cross-sectional view of the resin-sealed semiconductor device of the present invention seen from the line AA using the lead frame shown in FIG.

【図3】図1のリードフレームに搭載した半導体チップ
を樹脂封止する場合の状態を説明するための断面図であ
る。
FIG. 3 is a cross-sectional view for explaining a state in which a semiconductor chip mounted on the lead frame of FIG. 1 is resin-sealed.

【図4】従来技術の一構成単位のリードフレームを示し
た平面図である。
FIG. 4 is a plan view showing a lead frame which is one structural unit of the prior art.

【図5】図4に示したリードフレームを用い、A−A線
上から見た従来技術の樹脂封止型半導体装置の断面図で
ある。
5 is a cross-sectional view of a conventional resin-sealed semiconductor device using the lead frame shown in FIG. 4 as seen from the line AA.

【符号の説明】[Explanation of symbols]

1A 樹脂封止型半導体装置 2 半導体チップ 3A リードフレーム 4 ダイパッド 5 インナーリード 6 アウターリード 7 吊り 8 ステー 9 ワイヤ 10 封止樹脂 11 パッケージ 12 側面 20 細条突起 22 先端部 30 下金型 32 内側壁 1A Resin-encapsulated semiconductor device 2 Semiconductor chip 3A Lead frame 4 Die pad 5 Inner lead 6 Outer lead 7 Hanging 8 Stay 9 Wire 10 Encapsulating resin 11 Package 12 Side surface 20 Fine protrusion 22 Tip part 30 Lower die 32 Inner wall

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】ダイパッドとその周辺に配置した複数のイ
ンナーリードとこれらと対応したアウターリードとから
なるリードフレームにおいて、該インナーリードの間に
細条突起を形成したことを特徴とするリードフレーム。
1. A lead frame composed of a die pad, a plurality of inner leads arranged around the die pad, and outer leads corresponding to the die pads, wherein strip protrusions are formed between the inner leads.
【請求項2】外界に露出した蒸気減圧手段を具備した樹
脂封止型半導体装置。
2. A resin-sealed semiconductor device provided with vapor pressure reducing means exposed to the outside.
【請求項3】前記蒸気減圧手段は請求項1に記載した細
条突起で構成されていることを特徴とする請求項2に記
載の樹脂封止型半導体装置。
3. The resin-encapsulated semiconductor device according to claim 2, wherein the vapor pressure reducing means is composed of the strip projection described in claim 1.
JP1640992A 1992-01-31 1992-01-31 Resin-sealed semiconductor device Expired - Fee Related JP3134445B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1640992A JP3134445B2 (en) 1992-01-31 1992-01-31 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1640992A JP3134445B2 (en) 1992-01-31 1992-01-31 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPH05218263A true JPH05218263A (en) 1993-08-27
JP3134445B2 JP3134445B2 (en) 2001-02-13

Family

ID=11915444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1640992A Expired - Fee Related JP3134445B2 (en) 1992-01-31 1992-01-31 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JP3134445B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129808A (en) * 1995-10-31 1997-05-16 Nec Corp Plastic molded semiconductor device and its manufacture
KR100476667B1 (en) * 1997-09-25 2005-08-10 삼성전자주식회사 Lead frame and semiconductor chip package using the same
JP2007251217A (en) * 2007-07-06 2007-09-27 Renesas Technology Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129808A (en) * 1995-10-31 1997-05-16 Nec Corp Plastic molded semiconductor device and its manufacture
KR100252737B1 (en) * 1995-10-31 2000-04-15 가네꼬 히사시 Resin-sealed semiconductor device and its manufacture
KR100476667B1 (en) * 1997-09-25 2005-08-10 삼성전자주식회사 Lead frame and semiconductor chip package using the same
JP2007251217A (en) * 2007-07-06 2007-09-27 Renesas Technology Corp Semiconductor device

Also Published As

Publication number Publication date
JP3134445B2 (en) 2001-02-13

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