JPH05218134A - Mounting structure for flip chip - Google Patents
Mounting structure for flip chipInfo
- Publication number
- JPH05218134A JPH05218134A JP4040242A JP4024292A JPH05218134A JP H05218134 A JPH05218134 A JP H05218134A JP 4040242 A JP4040242 A JP 4040242A JP 4024292 A JP4024292 A JP 4024292A JP H05218134 A JPH05218134 A JP H05218134A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- board
- solder
- ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10165—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、裸のＩＣチップを基板
に直接フェイスダウンで接続するフリップチップの実装
構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip mounting structure for directly connecting a bare IC chip to a substrate facedown.
【０００２】[0002]
【従来の技術】近年、基板の高密度化、ＩＣの高集積化
によるＩＣチップの多ピン化、実装間隔の狭ピッチ化に
伴い、樹脂封止をしていない裸のＩＣチップを直接フェ
イスダウンで接続するフリップチップ実装が注目されて
いる。このフリップチップ実装の従来のプロセスは、ま
ず図５に示すようにＩＣチップ１の電極パッド２に半田
バンプ３を接着し、電極パッド２と基板４上に形成され
たランド５とを位置合わせする。次に図６に示すように
半田バンプ３をランド５上にマウントして加熱し、リフ
ローを行なって半田バンプ３を溶融し、電極パッド２と
ランド５とを接合する。2. Description of the Related Art In recent years, a bare IC chip that is not resin-sealed is directly faced down as the number of pins of the IC chip increases and the pitch of the mounting interval becomes narrower due to the higher density of the substrate, the higher integration of the IC. Flip-chip mounting, which is connected with, is drawing attention. In the conventional flip-chip mounting process, first, as shown in FIG. 5, solder bumps 3 are bonded to the electrode pads 2 of the IC chip 1 and the electrode pads 2 and the lands 5 formed on the substrate 4 are aligned with each other. .. Next, as shown in FIG. 6, the solder bumps 3 are mounted on the lands 5 and heated, and reflow is performed to melt the solder bumps 3 to bond the electrode pads 2 and the lands 5.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記の
ような従来のフリップチップ実装プロセスによると、リ
フロー時に半田バンプ３が完全に溶融する温度に設定す
ると、ＩＣチップ１が自重で沈み込み、図７の左側に示
すように半田接合部が横に広がる。このときＩＣチップ
１の自重が重かったり、電極パッド２間のピッチが例え
ば８０μｍ乃至１５０μｍと狭い場合には、図７の右側
に示すように半田接合部にブリッジが生ずる。また半田
接合部の高さも半田が横に広がるために確保できず、例
えば電極パッド２間のピッチが１５０μｍの場合２０μ
ｍ乃至３０μｍとかなり薄くなる。However, according to the conventional flip-chip mounting process as described above, when the temperature is set so that the solder bumps 3 are completely melted during the reflow, the IC chip 1 sinks under its own weight, and as shown in FIG. The solder joint expands laterally as shown on the left side of FIG. At this time, if the weight of the IC chip 1 is heavy or the pitch between the electrode pads 2 is narrow, for example, 80 μm to 150 μm, a bridge occurs at the solder joint portion as shown on the right side of FIG. Further, the height of the solder joint portion cannot be ensured because the solder spreads laterally. For example, if the pitch between the electrode pads 2 is 150 μm, it is 20 μm.
It becomes considerably thin as m to 30 μm.
【０００４】一方ＩＣチップ１のサイズが大きい場合に
は、ＩＣチップ１と基板４との熱膨張係数が異なるた
め、熱による伸縮が不整合となる。このため接合部であ
る半田バンプ３に応力が加わるので、半田接合部の高さ
は高いほうが熱サイクルに対する寿命は長くなる。従っ
て前述したように半田接合部が薄いとこの部分の信頼性
を確保することができない。逆に半田接合部の高さを確
保するために、半田が半溶融状態になるようにリフロー
温度を設定すると、ＩＣチップ１の自重による沈み込み
はある程度防止できるが、基板４に対する半田コートが
均一にならず、基板４の反りなどによる未半田部分が発
生するおそれがある。このような未半田部分の発生を防
止するためには、基板４側及びＩＣチップ１側の半田バ
ンプ３の高さを均一にしなければならず、高度の技術が
必要となる。On the other hand, when the size of the IC chip 1 is large, the expansion and contraction due to heat are mismatched because the IC chip 1 and the substrate 4 have different thermal expansion coefficients. For this reason, stress is applied to the solder bumps 3 that are the joints, so that the higher the height of the solder joints, the longer the life for the thermal cycle. Therefore, as described above, if the solder joint portion is thin, the reliability of this portion cannot be secured. On the contrary, if the reflow temperature is set so that the solder is in a semi-molten state in order to secure the height of the solder joint portion, it is possible to prevent the IC chip 1 from sinking due to its own weight to some extent, but the solder coat on the substrate 4 is uniform. However, the unsoldered portion may be generated due to the warp of the substrate 4. In order to prevent the occurrence of such unsoldered portions, it is necessary to make the heights of the solder bumps 3 on the substrate 4 side and the IC chip 1 side uniform, and a high level technique is required.
【０００５】本発明はこのような状況に鑑みてなされた
ものであり、ＩＣチップと基板との半田接合部の高さを
確保し、接合の信頼性を向上させることのできるフリッ
プチップの実装構造を提供することを目的とする。The present invention has been made in view of the above circumstances, and has a flip chip mounting structure capable of ensuring the height of a solder joint between an IC chip and a substrate and improving the reliability of the joint. The purpose is to provide.
【０００６】[0006]
【課題を解決するための手段】本発明のフリップチップ
の実装構造は、ＩＣチップ１に設けられた電極パッド２
を基板４に対向させ、半田バンプ３を介して電極パッド
２と基板４上に形成されたランド５とを接続するフリッ
プチップの実装構造において、ＩＣチップ１と基板４と
の間隔を所定の距離に規制する規制部材としてのボール
１１を、ＩＣチップ１の実装部分の基板４上に固定した
ことを特徴とする。The flip-chip mounting structure of the present invention has an electrode pad 2 provided on an IC chip 1.
In a flip-chip mounting structure in which the electrodes are opposed to the substrate 4 and the electrode pads 2 are connected to the lands 5 formed on the substrate 4 via the solder bumps 3, the IC chip 1 and the substrate 4 are separated by a predetermined distance. It is characterized in that the ball 11 as a regulation member for regulating the above is fixed on the substrate 4 on which the IC chip 1 is mounted.
【０００７】[0007]
【作用】上記構成のフリップチップの実装構造において
は、リフロー時にＩＣチップ１が自重で沈み込んだとき
に、ボール１１がスペーサとして作用し、ＩＣチップ１
と基板４との間隔がボール１１の直径に等しい距離に規
制される。従って半田接合部が横に広がることを防止で
き、狭ピッチのランド５間のブリッジの発生を防ぐこと
ができる。また半田を完全に溶融することができ未半田
部分の発生も防止できる。In the flip chip mounting structure having the above structure, when the IC chip 1 sinks under its own weight during reflow, the ball 11 acts as a spacer, and the IC chip 1
The distance between the substrate 4 and the substrate 4 is regulated to a distance equal to the diameter of the ball 11. Therefore, it is possible to prevent the solder joint portion from spreading laterally and prevent the generation of the bridge between the lands 5 having a narrow pitch. Further, the solder can be completely melted and the generation of unsoldered parts can be prevented.
【０００８】[0008]
【実施例】以下、本発明のフリップチップの実装構造の
一実施例を図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the flip chip mounting structure of the present invention will be described below with reference to the drawings.
【０００９】図１に本発明の一実施例の構成を示す。図
１において図６に示す従来例の部分と対応する部分には
同一の符号を付してあり、その説明は適宜省略する。本
実施例の特徴は半田バンプ３を介して実装されたＩＣチ
ップ１と基板４との間に所定の等しい直径を有する複数
個のボール１１を装着し、ボール１１を接着剤１２で固
定した点にある。FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, parts corresponding to those of the conventional example shown in FIG. 6 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. The feature of this embodiment is that a plurality of balls 11 having a predetermined equal diameter are mounted between the IC chip 1 and the substrate 4 mounted via the solder bumps 3, and the balls 11 are fixed with an adhesive 12. It is in.
【００１０】図２乃至図４及び図１に本実施例によるＩ
Ｃチップ１の実装手順を示す。まず図２に示すように基
板４上のＩＣチップ１の実装部分であるランド５の間に
予め定められた直径の複数個のボール１１を載置し、接
着剤１２で基板４に固定する。次に図３に示すように電
極パッド２に半田バンプ３が塗布されたＩＣチップ１
を、半田バンプ３とランド５とを対向させて基板４に対
して位置決めし、図４に示すようにＩＣチップ１を基板
４上にマウントする。次に半田バンプ３を加熱によりリ
フローさせ、ＩＣチップ１を自重により沈み込ませ、ボ
ール１１に当接させて図１に示す状態とする。FIGS. 2 to 4 and 1 show the I according to the present embodiment.
The mounting procedure of the C chip 1 is shown. First, as shown in FIG. 2, a plurality of balls 11 having a predetermined diameter are placed between the lands 5 which are mounting portions of the IC chip 1 on the substrate 4, and are fixed to the substrate 4 with an adhesive 12. Next, as shown in FIG. 3, the IC chip 1 in which the solder bumps 3 are applied to the electrode pads 2
Are positioned with respect to the substrate 4 with the solder bumps 3 and the lands 5 facing each other, and the IC chip 1 is mounted on the substrate 4 as shown in FIG. Next, the solder bumps 3 are reflowed by heating, the IC chip 1 is sunk by its own weight, and brought into contact with the balls 11 to obtain the state shown in FIG.
【００１１】本実施例によれば、半田バンプ３のリフロ
ー時にボール１１がスペーサの作用をなし、ＩＣチップ
１と基板４との間の間隔をボール１１の直径で決まる所
定の距離に規制することができる。従って半田接合部が
横に広がることを防止でき、ランド５間のピッチが狭い
場合でもブリッジの発生を防止できる。また半田を完全
に溶融することができるので、半田バンプ３の高さのば
らつきを吸収することができ、未半田部分の発生も防止
できる。さらにボール１１の直径を変化させることによ
り半田接合高さを制御することができ、適切なボール径
と適切な半田供給量を選択することにより、ＩＣチップ
１の基板４への実装の信頼性を確保することができる。
また半田接合部の厚さを厚くすることにより熱サイクル
に対する寿命を長くすることもできる。According to the present embodiment, the balls 11 function as spacers when the solder bumps 3 are reflowed, and the distance between the IC chip 1 and the substrate 4 is restricted to a predetermined distance determined by the diameter of the balls 11. You can Therefore, it is possible to prevent the solder joint portion from expanding laterally, and to prevent the occurrence of a bridge even when the pitch between the lands 5 is narrow. Further, since the solder can be completely melted, variations in the height of the solder bumps 3 can be absorbed, and the occurrence of unsoldered portions can be prevented. Further, the solder joint height can be controlled by changing the diameter of the ball 11, and the reliability of mounting the IC chip 1 on the substrate 4 can be improved by selecting an appropriate ball diameter and an appropriate solder supply amount. Can be secured.
Further, by increasing the thickness of the solder joint portion, it is possible to prolong the life for the thermal cycle.
【００１２】上記実施例ではＩＣチップ１と基板４との
間隔を規制する規制部材がボール１１である場合につい
て説明したが、規制部材はボール１１に限定されず、厚
さの均一な棒状部材やシート部材などであってもよい。
また半田バンプ３は基板４のランド５に設けてもよい。In the above embodiment, the case where the regulating member for regulating the distance between the IC chip 1 and the substrate 4 is the ball 11 has been described, but the regulating member is not limited to the ball 11, and a bar-shaped member having a uniform thickness or It may be a sheet member or the like.
The solder bumps 3 may be provided on the lands 5 of the substrate 4.
【００１３】[0013]
【発明の効果】以上説明したように、本発明のフリップ
チップの実装構造によれば、ＩＣチップと基板との間に
その間隔を規制する規制部材を設けたので、半田接合部
の厚さを所定の厚さとすることができ、ランド間のピッ
チが狭い場合でも半田ブリッジの発生を防止でき、熱サ
イクルに対する半田バンプの寿命を長くすることができ
る。さらに半田を完全に溶融することができるので未半
田部分の発生も防止できる。As described above, according to the flip chip mounting structure of the present invention, since the regulating member for regulating the gap between the IC chip and the substrate is provided, the thickness of the solder joint portion can be reduced. The thickness can be set to a predetermined value, the occurrence of solder bridges can be prevented even when the pitch between lands is narrow, and the life of solder bumps with respect to a thermal cycle can be extended. Furthermore, since the solder can be completely melted, the generation of unsoldered parts can be prevented.
【図１】本発明のフリップチップの実装構造の一実施例
の構成を示す側面図である。FIG. 1 is a side view showing a configuration of an embodiment of a flip chip mounting structure of the present invention.
【図２】図１の基板へのボール接着工程を示す側面図で
ある。FIG. 2 is a side view showing a step of bonding balls to the substrate of FIG.
【図３】図１のＩＣチップと基板との位置合わせの工程
を示す側面図である。FIG. 3 is a side view showing a process of aligning the IC chip and the substrate of FIG.
【図４】図１のＩＣチップの基板へのマウント工程を示
す側面図である。FIG. 4 is a side view showing a step of mounting the IC chip of FIG. 1 on a substrate.
【図５】従来のフリップチップの実装方法の一例のＩＣ
チップと基板との位置合わせの工程を示す側面図であ
る。FIG. 5 is an IC of an example of a conventional flip-chip mounting method.
It is a side view which shows the process of alignment of a chip | tip and a board | substrate.
【図６】図５のＩＣチップの基板へのマウント工程を示
す側面図である。6 is a side view showing a step of mounting the IC chip of FIG. 5 on a substrate.
【図７】図５の半田リフロー時の状態を示す側面図であ
る。FIG. 7 is a side view showing a state during solder reflow in FIG.
１ ＩＣチップ ２ 電極パッド ３ 半田バンプ ４ 基板 ５ ランド １１ ボール（規制部材） 1 IC chip 2 Electrode pad 3 Solder bump 4 Substrate 5 Land 11 Ball (regulating member)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 田原 浩樹 東京都品川区北品川６丁目７番35号 ソニ ー株式会社内 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiroki Tahara 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation
Claims (1)
板に対向させ、半田バンプを介して前記電極パッドと前
記基板上に形成されたランドとを接続するフリップチッ
プの実装構造において、 前記ＩＣチップと前記基板との間隔を所定の距離に規制
する規制部材を、前記ＩＣチップの実装部分の前記基板
上に固定したことを特徴とするフリップチップの実装構
造。1. A flip chip mounting structure in which an electrode pad provided on an IC chip is opposed to a substrate, and the electrode pad and a land formed on the substrate are connected to each other via a solder bump. A flip-chip mounting structure, characterized in that a regulating member for regulating a distance between the substrate and the substrate to a predetermined distance is fixed on the substrate in a mounting portion of the IC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4040242A JPH05218134A (en) | 1992-01-30 | 1992-01-30 | Mounting structure for flip chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4040242A JPH05218134A (en) | 1992-01-30 | 1992-01-30 | Mounting structure for flip chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05218134A true JPH05218134A (en) | 1993-08-27 |
Family
ID=12575249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4040242A Pending JPH05218134A (en) | 1992-01-30 | 1992-01-30 | Mounting structure for flip chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05218134A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0854520A2 (en) * | 1997-01-20 | 1998-07-22 | Oki Electric Industry Co., Ltd. | Method for mounting optical semiconductor device on supporting substrate |
| US6060780A (en) * | 1996-02-23 | 2000-05-09 | Denson Corporation | Surface mount type unit and transducer assembly using same |
| EP2492959A1 (en) * | 2011-02-22 | 2012-08-29 | Micro Systems Engineering GmbH | Electrical component having an electrical connection arrangement and method for the manufacture thereof |
-
1992
- 1992-01-30 JP JP4040242A patent/JPH05218134A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060780A (en) * | 1996-02-23 | 2000-05-09 | Denson Corporation | Surface mount type unit and transducer assembly using same |
| EP0854520A2 (en) * | 1997-01-20 | 1998-07-22 | Oki Electric Industry Co., Ltd. | Method for mounting optical semiconductor device on supporting substrate |
| EP0854520A3 (en) * | 1997-01-20 | 1999-06-16 | Oki Electric Industry Co., Ltd. | Method for mounting optical semiconductor device on supporting substrate |
| US6087194A (en) * | 1997-01-20 | 2000-07-11 | Oki Electric Industry Co., Ltd. | Composite unit of optical semiconductor device and supporting substrate and method for mounting optical semiconductor device on supporting substrate |
| EP2492959A1 (en) * | 2011-02-22 | 2012-08-29 | Micro Systems Engineering GmbH | Electrical component having an electrical connection arrangement and method for the manufacture thereof |
| US8923005B2 (en) | 2011-02-22 | 2014-12-30 | Micro Systems Engineering Gmbh | Electrical component having an electrical connection arrangement and method for the manufacture thereof |
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Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20010627 |