JPH05206098A - Method of etching ceramic basic material having metallic multilayer film - Google Patents

Method of etching ceramic basic material having metallic multilayer film

Info

Publication number
JPH05206098A
JPH05206098A JP4012685A JP1268592A JPH05206098A JP H05206098 A JPH05206098 A JP H05206098A JP 4012685 A JP4012685 A JP 4012685A JP 1268592 A JP1268592 A JP 1268592A JP H05206098 A JPH05206098 A JP H05206098A
Authority
JP
Japan
Prior art keywords
etching
film
metal
multilayer film
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4012685A
Other languages
Japanese (ja)
Inventor
Yutaka Kubo
裕 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Proterial Ltd
Original Assignee
Hitachi Metals Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Metals Ltd filed Critical Hitachi Metals Ltd
Priority to JP4012685A priority Critical patent/JPH05206098A/en
Publication of JPH05206098A publication Critical patent/JPH05206098A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Landscapes

  • ing And Chemical Polishing (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To provide an etching method for a substrate having a metallic multilayer film in which conventionally unavoidable side etching is suppressed. CONSTITUTION:In an etching method of a basic material having a metallic multilayer film in which 2 kinds of metal or alloy, e.g. metal A and metal B which is electrochemically nobler than metal A are laminated in order of A, B on the basic material, film B is first removed by using a first etching fluid for preferentially etching B to A, and next film A is removed by using a second etching fluid for preferentially etching A to B. The etching method of a ceramic basic material having a metallic multilayer film is characterized by subsequently removing the film B on the part projecting higher than the A film by using a third etching fluid for preferentially etching B to A.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体用基板、パッケ
ージ等に用いられる金属多層膜を有する基材の金属部分
のエッチング除去方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching and removing a metal portion of a base material having a metal multilayer film used for semiconductor substrates, packages and the like.

【０００２】[0002]

【従来の技術】ＬＳＩの高速、高密度化に伴い、発熱量
は増加の一途をたどっており、基板材料として求められ
る性質として高熱伝導率、耐熱性などの特性が特に重視
されるようになってきている。これに対応できるものと
して、ガラス基板、セラミックス基板、低温焼成基板な
どが注目されている。これら材料はいずれも絶縁体であ
り、はんだ等のろう材を直接使用できないため、ＬＳＩ
と接合しようとする場合、表面に金属膜を形成する、い
わゆるメタライズが必要となる。また、ＬＳＩのパッケ
ージの基板部と蓋部の接合にも基板部と蓋部それぞれの
接合部分に予めメタライズが必要となる。このメタライ
ズの方法としては、（１）導体ペースト、抵抗ペースト
をスクリーン印刷法によって基板上にパターン状に塗布
し、焼付ける厚膜法、（２）導体ペーストを焼成前の基
板にスクリーン印刷し、焼成と同時にメタライズを行な
う同時焼成法、（３）スパッタ、イオンプレーティン
グ、蒸着などによりメタライズ膜を形成する薄膜法など
が知られている。これらのうち、薄膜法は緻密な高純度
な膜を形成することが可能なことから、メタライズの高
信頼化においては不可欠なものであり、今後とも多く用
いられる技術であることが予想される。薄膜法によりメ
タライズ膜を形成した場合には、通常マスキング、エッ
チングの工程により、パターンを形成する。エッチング
の方法には、ガスなどを吹き付けてエッチングを行なう
ドライエッチング法およびエッチング液によりエッチン
グを行なうウェットエッチング法の２種類が用いられて
いる。このうち、ウェットエッチング法は、エッチング
対象材料の表面形状に左右されにくいという特徴がある
ため、特に３次元形状品にはウェットエッチングが用い
られる。2. Description of the Related Art With the increase in the speed and density of LSIs, the amount of heat generated has been increasing, and characteristics such as high thermal conductivity and heat resistance have come to be particularly emphasized as properties required for a substrate material. Is coming. Glass substrates, ceramics substrates, low temperature firing substrates, and the like have been attracting attention as materials that can meet this demand. Since all of these materials are insulators and brazing materials such as solder cannot be used directly,
In the case of joining with, a so-called metallization for forming a metal film on the surface is required. In addition, in order to bond the substrate portion and the lid portion of the LSI package, metallization is required in advance at the joint portions of the substrate portion and the lid portion. The metallizing method includes (1) a thick film method in which a conductor paste and a resistance paste are applied in a pattern on a substrate by screen printing and baking, and (2) the conductor paste is screen-printed on a substrate before baking, A co-firing method in which metallization is performed simultaneously with firing, and (3) a thin film method in which a metallized film is formed by sputtering, ion plating, vapor deposition, or the like are known. Among these, the thin film method is capable of forming a dense and highly pure film, and thus is indispensable for increasing the reliability of metallization and is expected to be a technique that will be used frequently in the future. When the metallized film is formed by the thin film method, the pattern is usually formed by masking and etching steps. Two types of etching methods are used: a dry etching method in which a gas or the like is blown for etching and a wet etching method in which etching is performed with an etching solution. Among them, the wet etching method is characterized in that it is unlikely to be influenced by the surface shape of the material to be etched, and therefore wet etching is used particularly for a three-dimensional shape product.

【０００３】[0003]

【発明が解決しようとする課題】基板とＬＳＩとの接合
はあるいはＬＳＩのパッケージの基板部と蓋部との接合
は、通常はんだにより行なわれることが多いが、はんだ
付用のメタライズ膜としては、基板との反応性、密着強
度、はんだ付時の食われ性、はんだとの反応性、濡れ性
等を考慮して２層あるいはそれ以上の多層膜が用いられ
ることが多く、これら多層膜をそれぞれの境界でサイド
エッチなしにエッチングを行ない、エッチングの端部を
完全に揃えることは極めて難しく、大きな課題となって
いた。例えば通常２層の場合には、特定の層のエッチン
グのみが進行しないように各層を優先的に溶解する２種
類のエッチング液を用いて、１層ごとに順番に溶解する
方法が用いられるが、各層の局部電池等の作用によりエ
ッチング端部を完全に揃えること、すなわちジャストエ
ッチングの状態にすることは非常に困難であった。本発
明の目的は、金属多層膜を有する基材の金属多層膜をエ
ッチングにより除去する際に２種の金属層間のエッチン
グ端を揃えることが可能となるエッチング方法を提供す
ることである。The joining of the substrate and the LSI or the joining of the substrate portion and the lid portion of the LSI package is usually performed by solder in many cases. However, as a metallized film for soldering, A multilayer film of two layers or more is often used in consideration of reactivity with the substrate, adhesion strength, erosion during soldering, reactivity with solder, wettability, etc. It was extremely difficult to perform etching without side etching at the boundary of, and it was extremely difficult to completely align the end of etching, which was a big problem. For example, in the case of usually two layers, a method of sequentially dissolving each layer by using two kinds of etching liquids that preferentially dissolves each layer so that etching of a specific layer does not proceed is used. It has been very difficult to perfectly align the etching end portions, that is, to just-etch by the action of the local battery of each layer. An object of the present invention is to provide an etching method capable of aligning the etching edges between two types of metal layers when removing the metal multilayer film of a substrate having a metal multilayer film by etching.

【０００４】[0004]

【課題を解決するための手段】本発明者は、金属多層膜
の各層間の電気化学的性質とエッチングの進行状況を観
察し、本発明に到達した。すなわち、本発明は、Ａより
Ｂの方が電気化学的に貴である２種の金属あるいは合金
を基材上にＡ，Ｂの順で積層させた金属多層膜を有する
基材のエッチング方法において、まずＡよりもＢを優先
的にエッチングする第１のエッチング液を用いてＢ膜を
除去し、次にＢよりもＡを優先的にエッチングする第２
のエッチング液を用いてＡ膜を除去し、その後Ａよりも
Ｂを優先的にエッチングする第３のエッチング液を用い
てＡ膜よりも突出した部分のＢ膜を除去することを特徴
とする金属多層膜を有するセラミックス基材のエッチン
グ方法である。The present inventors arrived at the present invention by observing the electrochemical properties between layers of a metal multilayer film and the progress of etching. That is, the present invention relates to an etching method for a substrate having a metal multilayer film in which two metals or alloys in which B is electrochemically nobler than A is laminated on the substrate in the order A and B. First, the B film is removed by using the first etching liquid that preferentially etches B over A, and then the second etchant preferentially etches A over B.
Metal for removing the A film by using the etching solution described above, and then removing the B film at a portion protruding from the A film by using a third etching solution that preferentially etches the B film over the A film. A method for etching a ceramic substrate having a multilayer film.

【０００５】以下に本発明を詳しく説明する。上記の課
題を解決するために本発明者は、下側の膜より上側の膜
が電気化学的に貴、すなわち標準電極電位が大きい場合
のメタライズ端部でのエッチングの進行につき詳細に調
査した。エッチングの各段階における断面の模式図を図
１に示す。ここでＢはＡより電気化学的に貴な金属また
は合金とし、パターニングのためもレジスト剤にてマス
キングした状態から、エッチングの各段階での断面図を
示す。（１）は基板上にＡ層、Ｂ層の順に成膜し、マス
キング用のレジストを塗布した状態、（２）はＢ層を優
先的にエッチングする第１のエッチング液にて、Ｂ層を
エッチングした状態、（３）〜（６）は、Ａ層を優先的
にエッチングする第２のエッチング液にて、Ａ層をエッ
チングする課程の状態の変化を示す。The present invention will be described in detail below. In order to solve the above-mentioned problems, the present inventor investigated in detail the progress of etching at the metallized end when the upper film is electrochemically noble than the lower film, that is, when the standard electrode potential is large. FIG. 1 shows a schematic view of a cross section at each stage of etching. Here, B is a metal or alloy that is electrochemically more noble than A, and cross-sectional views are shown at each stage of etching from the state of being masked with a resist agent for patterning. (1) is a state in which a layer A and a layer B are formed in this order on a substrate and a resist for masking is applied, and (2) is a first etching liquid for preferentially etching the layer B. The etched states (3) to (6) show changes in the state of the process of etching the A layer with the second etching liquid that preferentially etches the A layer.

【０００６】図１の（３)〜(５）においては、Ａ層のエ
ッチングは、Ｂ層と接触している部分で局部電池の作用
が働くため、Ｂ層と接触していない部分に比べ進行速度
が大きくなる。そのため、Ａ層の除去が終了した段階
（６）において、長さａのサイドエッチが生じＡ層とＢ
層の先端部分は揃わず、エッチング液の濃度、温度、エ
ッチング時間を種々調整しても、上記のサイドエッチを
なくすことはできない。そこで、さらに検討を行なった
結果、ついて本発明者は解決方法を見出すに至った。す
なわち、上述したエッチング過程のＡ層の除去が終了し
てから、さらにＢ層を優先的にエッチングする第３のエ
ッチング液にてＢ層の突出した部分をエッチングし、こ
れによりＡ層、Ｂ層端部の揃った、サイドエッチのない
エッチング状態（７）を得ることができる。In (3) to (5) of FIG. 1, the etching of the A layer progresses as compared with the portion not in contact with the B layer because the action of the local battery works in the portion in contact with the B layer. The speed increases. Therefore, at the stage (6) when the removal of the A layer is completed, side etching of the length a occurs and the A layer and the B layer are removed.
The tip portions of the layers are not aligned, and the side etching cannot be eliminated by variously adjusting the concentration, temperature, and etching time of the etching solution. Then, as a result of further study, the inventor has finally found a solution. That is, after the removal of the A layer in the above-described etching process is completed, the protruding portion of the B layer is etched with a third etching solution that preferentially etches the B layer, and thus the A layer and the B layer are etched. It is possible to obtain an etching state (7) in which the edges are aligned and side etching is not performed.

【０００７】本発明に使用する第１のエッチング液およ
び第３のエッチング液は、ＡよりもＢを優先的にエッチ
ングするものであれば同一のものでもよいし、エッチン
グ液の濃度や種類を変えてもよい。なお、本発明による
エッチング方法は、基板上に直接Ａ層およびＢ層が積層
されているものに限定されるものではなく、Ａ層と基材
との間に金属および／または非金属層が介在しても同等
の効果が得られる。また、半導体用基板およびパッケー
ジに要求される特性である高い耐熱性、耐熱性を有する
アルミナ、窒化アルミニウムはそのままではそれぞれの
接合およびＬＳＩとの接合が不可能であり、メタライズ
が必須である。半導体用途の部材に使用する場合、微少
な形状不良が製品自体の不良につながるため、アルミ
ナ、窒化アルミニウムを半導体用基板およびパッケージ
といった半導体用途に使用する場合、本発明のサイドエ
ッチの少ないエッチング形状が得られる本発明の方法
は、極めて有効である。The first etching liquid and the third etching liquid used in the present invention may be the same as long as they preferentially etch B over A, or the concentrations and types of the etching liquids may be changed. May be. The etching method according to the present invention is not limited to the method in which the A layer and the B layer are directly laminated on the substrate, and a metal and / or a non-metal layer is interposed between the A layer and the base material. Even if the same effect is obtained. Further, alumina and aluminum nitride, which have high heat resistance and heat resistance, which are characteristics required for a semiconductor substrate and a package, cannot be directly bonded to each other or to an LSI, and metallization is essential. When used as a member for semiconductor applications, minute shape defects lead to defects in the product itself.Therefore, when using alumina or aluminum nitride for semiconductor applications such as semiconductor substrates and packages, the etching shape with less side etching of the present invention is used. The resulting method of the present invention is extremely effective.

【０００８】[0008]

【実施例】本発明を実施例に基づいてさらに詳しく説明
する。 （実施例１）アルミナ基板上にＣuおよびＡuをそれぞれ
0.8μm、0.3μmにイオンプレーティング法にて成膜し
た。マスキング用レジストにてパターニングした後、10
%ＫＣＮ溶液にてＡu、20%ＦeＣl3溶液にてＣuをエッチ
ングした。その後、10%ＫＣＮ溶液により再度エッチン
グを行なった。結果を表１に示す。また、比較例として
エッチング時間を変えて10%ＫＣＮ溶液でＡu、20%ＦeＣ
l3溶液でＣuをエッチングした場合を表１に示す。EXAMPLES The present invention will be described in more detail based on examples. (Example 1) Cu and Au were respectively deposited on an alumina substrate.
Films were formed at 0.8 μm and 0.3 μm by the ion plating method. After patterning with a masking resist, 10
% Of the KCN solution and Cu in the 20% FeCl 3 solution. Then, etching was performed again with a 10% KCN solution. The results are shown in Table 1. In addition, as a comparative example, the etching time was changed and Au and 20% FeC were used with 10% KCN solution.
Table 1 shows the case where Cu was etched with the l 3 solution.

【０００９】[0009]

【表１】 [Table 1]

【００１０】表１よりＡu、Ｃuをエッチングした後にＡ
uをＫＣＮ溶液で再度エッチングすることによりサイド
エッチ量を極めて少なくすることができた。一方、比較
例１ないし３よりＡu,Ｃuの２段のエッチングではＣuの
エッチング時間が短いと、Ｃuがエッチング不十分とな
り、この場合でもサイドエッチ量が大きく、またＣuの
エッチング時間が長いほどサイドエッチ量はさらに大き
くなり、従来の２段のエッチングではサイドエッチを小
さくすることが困難であることがわかる。 （実施例２）窒化アルミニウム上にＮi,Ａuをそれぞれ
1.5μm、0.5μmにスパッタ法にて成膜した。マスキング
用レジストにてパターニングした後、5%Ｉ2＋10%ＮＨ4
Ｉ溶液にてＡu、40%ＦeＣl3溶液にてＮiをエッチングし
た。その後、5%Ｉ2＋10%ＮＨ4Ｉ溶液により再度エッチ
ングを行なった。結果を表２に示す。また、比較例とし
てエッチング時間を変えて、5%Ｉ2＋10%ＮＨ4Ｉ溶液に
てＡu、40%ＦeＣl3溶液にてＮiをエッチングした場合を
表２に示す。From Table 1, after etching Au and Cu, A
By etching u again with a KCN solution, the side etch amount could be extremely reduced. On the other hand, compared with Comparative Examples 1 to 3, in the two-stage etching of Au and Cu, when the etching time of Cu is short, the etching of Cu becomes insufficient. The amount of etching is further increased, and it can be seen that it is difficult to reduce the side etch by the conventional two-step etching. (Example 2) Ni and Au were respectively deposited on aluminum nitride.
Films were formed to a thickness of 1.5 μm and 0.5 μm by a sputtering method. After patterning with a masking resist, 5% I 2 + 10% NH 4
Au was etched with the I solution and Ni was etched with the 40% FeCl 3 solution. Then, etching was performed again with a 5% I 2 + 10% NH 4 I solution. The results are shown in Table 2. Further, as a comparative example, Table 2 shows a case where Au was etched with a 5% I 2 + 10% NH 4 I solution and Ni was etched with a 40% FeCl 3 solution while changing the etching time.

【００１１】[0011]

【表２】 [Table 2]

【００１２】これよりＡu、Ｎiのエッチング後にＡuを5
%Ｉ2＋10%ＮＨ4Ｉ溶液で再度エッチングすることにより
サイドエッチ量を非常に少なくすることができた。また
比較例で示す従来の２段エッチングではいずれの時間で
もサイドエッチが生じており、時間が長いほどサイドエ
ッチ量が大きくなり、また時間が短いとエッチング不十
分となり、サイドエッチをなくすことはできないことが
わかる。As a result, after etching Au and Ni, Au is added to 5
By etching again with the% I 2 + 10% NH 4 I solution, the side etch amount could be made extremely small. Further, in the conventional two-step etching shown in the comparative example, side etching occurs at any time. The longer the time, the larger the side etching amount, and the shorter the time, the insufficient etching, and the side etching cannot be eliminated. I understand.

【００１３】[0013]

【発明の効果】本発明の方法は、金属多層膜を有する基
材の金属多層膜をエッチングにより除去する際に、２種
の金属層間の電気化学的性質の差に起因するサイドエッ
チを少ないものとすることができるため、特にサイドエ
ッチが少ないことが必要である半導体用途に好適であ
る。本発明の方法によれば、接合部にメタライズが必要
であるアルミナ、窒化アルミニウム等のセラミックスの
メタライズ部分のエッチング端の品位が向上するため、
アルミナ、窒化アルミニウムを基板あるいはパッケージ
といった半導体用途に使用する場合、極めて有効な手段
となる。According to the method of the present invention, when the metal multilayer film of the substrate having the metal multilayer film is removed by etching, side etching caused by a difference in electrochemical property between two kinds of metal layers is reduced. Therefore, it is suitable for semiconductor applications in which it is particularly necessary to reduce side etching. According to the method of the present invention, since the quality of the etching end of the metallized portion of ceramics such as alumina and aluminum nitride that requires metallization at the joint is improved,
It is an extremely effective means when using alumina or aluminum nitride for semiconductor applications such as substrates or packages.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明のエッチング方法による各段階の多層膜
断面の模式図である。FIG. 1 is a schematic view of a cross section of a multilayer film at each stage according to the etching method of the present invention.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 ＡよりＢの方が電気化学的に貴である２
種の金属あるいは合金を基材上にＡ，Ｂの順で積層させ
た金属多層膜を有する基材のエッチング方法において、
まずＡよりもＢを優先的にエッチングする第１のエッチ
ング液を用いてＢ膜を除去し、次にＢよりもＡを優先的
にエッチングする第２のエッチング液を用いてＡ膜を除
去し、その後ＡよりもＢを優先的にエッチングする第３
のエッチング液を用いてＡ膜よりも突出した部分のＢ膜
を除去することを特徴とする金属多層膜を有するセラミ
ックス基材のエッチング方法。1. B is electrochemically more precious than A. 2
In a method for etching a base material having a metal multilayer film in which a metal or alloy of a certain kind is laminated on the base material in the order of A and B,
First, the B film is removed using a first etching solution that preferentially etches B over A, and then the A film is removed using a second etching solution that preferentially etches A over B. , Then preferentially etching B over A
A method for etching a ceramic substrate having a metal multi-layered film, characterized in that the B film in a portion projecting from the A film is removed by using the etching solution of. 【請求項２】 基材がアルミナまたは窒化アルミニウム
であることを特徴とする請求項１に記載の金属多層膜を
有するセラミックス基材のエッチング方法。2. The method for etching a ceramic substrate having a metal multilayer film according to claim 1, wherein the substrate is alumina or aluminum nitride.
JP4012685A 1992-01-28 1992-01-28 Method of etching ceramic basic material having metallic multilayer film Pending JPH05206098A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4012685A JPH05206098A (en) 1992-01-28 1992-01-28 Method of etching ceramic basic material having metallic multilayer film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4012685A JPH05206098A (en) 1992-01-28 1992-01-28 Method of etching ceramic basic material having metallic multilayer film

Publications (1)

Publication Number Publication Date
JPH05206098A true JPH05206098A (en) 1993-08-13

Family

ID=11812235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4012685A Pending JPH05206098A (en) 1992-01-28 1992-01-28 Method of etching ceramic basic material having metallic multilayer film

Country Status (1)

Country Link
JP (1) JPH05206098A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8216654B2 (en) 2003-02-19 2012-07-10 Ulvac, Inc. Components for a film-forming device and method for cleaning the same
JP2019083250A (en) * 2017-10-30 2019-05-30 ラピスセミコンダクタ株式会社 Semiconductor device and manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8216654B2 (en) 2003-02-19 2012-07-10 Ulvac, Inc. Components for a film-forming device and method for cleaning the same
JP2019083250A (en) * 2017-10-30 2019-05-30 ラピスセミコンダクタ株式会社 Semiconductor device and manufacturing method of semiconductor device

Similar Documents

Publication Publication Date Title
US5058799A (en) Metallized ceramic substrate and method therefor
US5100714A (en) Metallized ceramic substrate and method therefor
US5039552A (en) Method of making thick film gold conductor
JPH03216909A (en) Reinforced directly coupled copper structure
JP2009504547A (en) Metal ceramic substrate
TW200846497A (en) Selective etch of TiW for capture pad formation
JPH0463838B2 (en)
US5250394A (en) Metallization method for microwave circuit
JPH03225810A (en) Structure of terminal electrode film in stacked capacitor and formation of the film
JPH05206098A (en) Method of etching ceramic basic material having metallic multilayer film
KR900003849B1 (en) Circuit substrate and thermal printing head using the same caller identifying method
JP2022050582A (en) Mounting board and manufacturing method thereof
JPS5918184A (en) Ceramic metallization
EP0089604B1 (en) Method for selectively coating metallurgical patterns on dielectric substrates
JP4520665B2 (en) Printed wiring board, manufacturing method thereof, and component mounting structure
JP4264091B2 (en) Wiring board manufacturing method
EP0219122B1 (en) Metallized ceramic substrate and method of manufacturing the same
KR100942944B1 (en) Method for Manufacturing of Multi-layer Thin film Substrate and the multi-layer Thin film Substrate
JP2000154081A (en) Ceramic parts and their production
JP3792642B2 (en) Wiring board and manufacturing method thereof
RU2329622C1 (en) Method of multi-layer thin-film structure manufacturing
JPH1065294A (en) Ceramic wiring board and manufacture thereof
JP3554195B2 (en) Wiring board
JP3857219B2 (en) Wiring board and manufacturing method thereof
JP2005244005A (en) Method for manufacturing circuit board and circuit board

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term