JPH05198278A - Flat panel type display device - Google Patents
Flat panel type display deviceInfo
- Publication number
- JPH05198278A JPH05198278A JP4007503A JP750392A JPH05198278A JP H05198278 A JPH05198278 A JP H05198278A JP 4007503 A JP4007503 A JP 4007503A JP 750392 A JP750392 A JP 750392A JP H05198278 A JPH05198278 A JP H05198278A
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- Prior art keywords
- gate
- gates
- cathode
- electron emission
- voltage
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- Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は電子放出陰極を用いた
平面パネル型ディスプレイに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel type display using an electron emitting cathode.
【０００２】[0002]
【従来の技術】電子放出陰極を用いた平面パネル型ディ
スプレイは微小な電子放出陰極を縦横に配列し、縦・横
の２次元のアドレッシングを行う事で各画素を発光させ
ディスプレイを構成する。図６は例えば特表平２−５０
００６５号公報に示されたマトリクスアドレス平面パネ
ルディスプレイの一部分の模式断面図である。図におい
て、２は電子放出陰極、３は絶縁層、６は支柱、７ａ，
７ｂ，７ｃは蛍光体、８はアノード、９はフェースパネ
ル、１０は基板、１１ａ，１１ｂ，１１ｃは基体、１２
は基体間絶縁層、１３はゲートである。2. Description of the Related Art A flat panel type display using an electron emission cathode has a structure in which minute electron emission cathodes are arranged vertically and horizontally and two-dimensional vertical and horizontal addressing is performed to make each pixel emit light. FIG. 6 shows, for example, the special table 2-50.
It is a schematic cross-sectional view of a part of the matrix address flat panel display shown in Japanese Patent Publication No. 0065. In the figure, 2 is an electron emission cathode, 3 is an insulating layer, 6 is a pillar, 7a,
7b and 7c are phosphors, 8 is an anode, 9 is a face panel, 10 is a substrate, 11a, 11b and 11c are bases, 12
Is an inter-substrate insulating layer, and 13 is a gate.
【０００３】次に動作について説明する。電子放出陰極
２とゲート１３間に電圧を印加するとゲート穴近傍に位
置する円錐状の電子放出陰極２の先端から電子が放出さ
れ、高電圧が印加されたアノード８に向かって進行す
る。この際にアノード８下面の蛍光体に電子が当り、蛍
光体が発光する。ディスプレイとして２次元に配列され
た画素のマトリックスの選択は、例えば基体を縦方向
に、ゲート１３を横方向にそれぞれ分割し、分割された
ある基体と分割されたあるゲ−ト間に電圧を印加する事
で行う。Next, the operation will be described. When a voltage is applied between the electron emission cathode 2 and the gate 13, electrons are emitted from the tip of the conical electron emission cathode 2 located near the gate hole, and proceed toward the anode 8 to which a high voltage is applied. At this time, electrons hit the phosphor on the lower surface of the anode 8 and the phosphor emits light. To select a matrix of pixels arranged two-dimensionally as a display, for example, the substrate is divided vertically and the gate 13 is divided horizontally, and a voltage is applied between a divided substrate and a divided gate. Do by doing.
【０００４】この方法によれば、各縦・横のアドレッシ
ングを行う事で各画素を発光させディスプレイを構成す
る事ができる。According to this method, it is possible to form a display by causing each pixel to emit light by performing vertical and horizontal addressing.
【０００５】[0005]
【発明が解決しようとする課題】上記のような方法では
画素のアドレッシングを行うために電子放出陰極を形成
する基体の分割が必要であり、例えば電子放出陰極をＳ
ｉウェハを基体としＳｉのエッチングなどで形成する場
合、基体であるＳｉウェハを分割する事が困難である。In the method as described above, it is necessary to divide the substrate forming the electron emission cathode in order to perform the addressing of the pixel.
When an i-wafer is used as a base and is formed by etching Si, it is difficult to divide the Si-wafer as a base.
【０００６】この発明はかかる問題を解決するためにな
されたものであって、簡単な素子構成で２次元画素のア
ドレッシングを容易に行え、製作が容易な平面パネル型
ディスプレイを得る事を目的とする。The present invention has been made to solve the above problems, and an object thereof is to obtain a flat panel type display which can easily address two-dimensional pixels with a simple device structure and can be easily manufactured. ..
【０００７】[0007]
【課題を解決するための手段】この発明の平面パネル型
ディスプレイは電子放出陰極から放出される電子を制御
するゲートを一軸方向に並行なアレイ状の第１ゲート
と、上記一軸と直交する方向に並行なアレイ状の第２ゲ
ートとの２段構造とし、上記電子放出陰極先端部が上記
２段のゲート間に位置するように配置し、上記２段のゲ
ートのそれぞれ独立した電圧のオン・オフによって画素
に応じた電子放出を選択するようにしたものである。In the flat panel display of the present invention, the gates for controlling the electrons emitted from the electron-emitting cathodes are arrayed in parallel with the first gates in the uniaxial direction, and in the direction orthogonal to the uniaxial direction. It has a two-stage structure with a parallel second gate, and the tip of the electron-emitting cathode is arranged between the two-stage gates, and the two-stage gates are turned on and off independently of each other. The electron emission is selected according to the pixel.
【０００８】[0008]
【作用】このように構成された平面パネル型ディスプレ
イでは、第１，第２の２段のゲートによって容易に画素
のアドレッシングを行う事ができ、従来のように分割が
困難な基体の分割が不要となる。また、このゲートは形
成が容易である。In the flat panel type display having such a structure, the addressing of pixels can be easily performed by the first and second stages of gates, and there is no need to divide the substrate, which is difficult to divide as in the conventional case. Becomes Also, this gate is easy to form.
【０００９】[0009]
実施例１．図１はこの発明の一実施例の電子放出陰極を
用いた平面パネル型ディスプレイの一部分の模式断面図
であり、図２は図１におけるゲートの模式平面図であ
る。この図において、１は基体、２は電子放出陰極、３
は絶縁層、４は第１ゲートである下段ゲートで、４ａ，
４ｂ，４ｃはそれぞれ一軸方向に平行に分割された下段
ゲート、５は第２ゲートである上段ゲートで、５ａ，５
ｂ，５ｃはそれぞれ一軸と直交方向に平行に分割された
上段ゲート、６は支柱、７は蛍光体、８はアノード、９
はフェースパネルである。なお、電子放出陰極２先端部
は上，下段ゲート４，５間に位置するように配置されて
いる。図２における多数の丸はゲート穴を示す。また、
この図では、説明のためにＸ列・Ｙ列が交差する一つの
画素において電子放出陰極２が３×３個の構成について
示すが、任意のＭ×Ｎ個の構成でもかまわない。Example 1. FIG. 1 is a schematic sectional view of a part of a flat panel type display using an electron emitting cathode according to an embodiment of the present invention, and FIG. 2 is a schematic plan view of a gate in FIG. In this figure, 1 is a substrate, 2 is an electron emission cathode, 3
Is an insulating layer, 4 is a lower gate which is a first gate, 4a,
Reference numerals 4b and 4c denote lower gates which are divided in parallel with each other in the uniaxial direction, and 5 denotes an upper gate which is a second gate.
b and 5c are upper gates divided in parallel to the direction orthogonal to one axis, 6 is a pillar, 7 is a phosphor, 8 is an anode, 9
Is a face panel. The tip of the electron emission cathode 2 is arranged so as to be located between the upper and lower gates 4 and 5. A large number of circles in FIG. 2 indicate gate holes. Also,
In this figure, for the sake of explanation, a configuration is shown in which the number of electron emission cathodes 2 is 3 × 3 in one pixel in which the X and Y columns intersect, but any number of M × N configurations may be used.
【００１０】次に動作について説明する。図２に示した
ゲートのＸ列のどれか一列とＹ列のどれか一列に同時に
電圧が印加されると電子放出陰極２に適当な電界が加わ
り、電子が放出し蛍光体７を発光させる。しかし、Ｘ列
のどれか一列かＹ列のどれか一列の片方のみに電圧が印
加されても電子放出陰極２に加わる電界は小さく電子を
放出させる事はできない。このため、ある画素のＸ・Ｙ
両方のゲートに電圧が印加された場合に画素が発光す
る。このように、この平面パネル型ディスプレイではゲ
ートを上下２段構造とし、それぞれのゲートを画素に対
応するように交差して分離するという簡単な構成で、そ
れぞれのゲートに独立に電圧を印加することによって電
子放出を選択することができ、画素のアドレッシングが
容易に行える。また、このゲートは形成が容易であり、
従来のように分割が困難な基体を電気的に分割する必要
も無く、製作も容易である。Next, the operation will be described. When a voltage is applied to any one of the X and Y columns of the gate shown in FIG. 2 at the same time, an appropriate electric field is applied to the electron emission cathode 2 and electrons are emitted to cause the phosphor 7 to emit light. However, even if a voltage is applied to only one of the X rows and one of the Y rows, the electric field applied to the electron emission cathode 2 is small and electrons cannot be emitted. Therefore, the X and Y of a pixel
The pixel emits light when a voltage is applied to both gates. As described above, in this flat panel type display, the gate has a two-tiered structure, and each gate is crossed and separated so as to correspond to a pixel, and a voltage is independently applied to each gate. The electron emission can be selected by this, and the pixel addressing can be easily performed. Also, this gate is easy to form,
It is not necessary to electrically divide a substrate that is difficult to divide as in the conventional case, and the manufacturing is easy.
【００１１】ところで、ゲートのＸ列のどれか一列かＹ
列のどれか一列の片方のみに電圧が印加された場合で
も、電子放出陰極２と電圧が印加されたゲート４，５の
位置関係によっては、電界が高くなり電子放出が起こる
場合があり、アドレッシングが適切に行われない。By the way, one of the X columns of gates or Y
Even if the voltage is applied to only one of the columns, the electric field may be increased and electron emission may occur depending on the positional relationship between the electron emission cathode 2 and the gates 4 and 5 to which the voltage is applied. Is not done properly.
【００１２】図３のグラフに２段ゲート４，５間の絶縁
層３の膜厚方向の中心の高さから電子放出陰極２の高さ
の差であるゲート／陰極高さの差と、電子放出陰極２の
先端から０．０１μｍ離れた点での電界の関係を有限要
素法を用いて計算した結果を示す。ここで、ゲートに印
加した電圧はオンの場合１００Ｖ、オフの場合０Ｖであ
り、ゲート穴直径は１μｍである。図中で白丸の特性曲
線は２段のゲートのうち上段ゲート５に電圧を印加し下
段ゲート４に電圧を印加しない場合、黒丸の特性曲線は
２段のゲートのうち下段ゲート４に電圧を印加し上段ゲ
ート５に電圧を印加しない場合で、画素が発光しない事
を目的とした構成である。破線の特性曲線は２段のゲー
ト４，５の両方に電圧を印加した場合で、画素が発光す
る事を目的としている。一方のゲートのみに電圧を印加
した場合、電界はゲート／陰極高さの差に影響され、ゲ
ート／陰極高さの差が０．１５μｍ程度で電界は最も低
くなる。電界がどの程度低下すると電子が放出されず蛍
光体が発光しなくなるかは、図５のグラフに示す電子放
出陰極先端での電界とアノード８電流の一般的な関係よ
り、最大電界の６割程度であると考えられる。なお、図
５では２段のゲート４，５の両方に電圧を印加した場合
（図３における破線に相当）の電界、アノード電流を１
とした場合の規格化した値で示している。このため、図
３よりゲート／陰極高さの差が０．１μｍから０．２μ
ｍの範囲にあるとき 電界は最大時の６割以下であり、
電子は放出されず、適切な画素のアドレッシングが行え
る。２段のゲート４，５において、２つのゲート４，５
間の絶縁層３の膜厚方向の中心の高さを電子放出陰極２
先端の高さより０．１〜０．２μｍ高くすると良い。即
ち、電子放出陰極２先端が２つのゲート４，５間の中間
位置より０．１〜０．２μｍ低くなるように配置すると
よい。In the graph of FIG. 3, the difference between the height of the gate / cathode, which is the difference between the height of the center of the insulating layer 3 in the film thickness direction between the two-stage gates 4 and 5, and the height of the electron / cathode, and the electron The result of calculating the relationship of the electric field at a point 0.01 μm away from the tip of the emission cathode 2 by using the finite element method is shown. Here, the voltage applied to the gate is 100 V when it is on and 0 V when it is off, and the diameter of the gate hole is 1 μm. In the figure, the characteristic curve with white circles is a case where a voltage is applied to the upper gate 5 and the voltage is not applied to the lower gate 4 of the two-stage gates. However, this is a configuration in which the pixel does not emit light when no voltage is applied to the upper gate 5. The dashed characteristic curve is intended to cause the pixel to emit light when a voltage is applied to both gates 4 and 5 in two stages. When a voltage is applied only to one of the gates, the electric field is affected by the height difference between the gate and the cathode, and the electric field becomes the lowest when the height difference between the gate and the cathode is about 0.15 μm. From the general relationship between the electric field at the tip of the electron-emitting cathode and the current at the anode 8 shown in the graph of FIG. 5, how much the electric field is reduced does not cause the emission of electrons and the phosphor does not emit light. Is considered to be. In FIG. 5, the electric field and the anode current when the voltage is applied to both of the two-stage gates 4 and 5 (corresponding to the broken line in FIG. 3) are 1
The values are standardized. Therefore, the difference in gate / cathode height is 0.1 μm to 0.2 μm as shown in FIG.
When in the range of m, the electric field is 60% or less of the maximum,
Electrons are not emitted, and appropriate pixel addressing can be performed. In the two-stage gates 4,5, two gates 4,5
The height of the center of the insulating layer 3 in the film thickness direction is set to the electron emission cathode 2
It is preferable that the height is 0.1 to 0.2 μm higher than the height of the tip. That is, the tip of the electron emission cathode 2 may be arranged so as to be lower than the intermediate position between the two gates 4 and 5 by 0.1 to 0.2 μm.
【００１３】また、図４のグラフに一方のゲートに正、
他方のゲートに負の電圧をかけた場合における、２段ゲ
ート間の絶縁層の膜厚方向の中心の高さから電子放出陰
極の高さの差であるゲート／陰極高さの差と、電子放出
陰極の先端から０．０１μｍ離れた点での電界の関係を
有限要素法を用いて計算した結果を示す。図中で白丸の
特性曲線は２段のゲートのうち上段のゲート５に正の電
圧を印加し下段のゲート４に負の電圧を印加した場合、
黒丸の特性曲線は２段のゲートのうち下段４のゲートに
正の電圧を印加し上段のゲート５に負の電圧を印加した
場合で、画素が発光しない事を目的とした構成である。
破線は２段のゲートの両方に電圧を印加した場合で、画
素が発光する事を目的としている。一方のゲートに正の
電圧を印加した場合、電界はゲート／陰極高さの差に影
響され、ゲート／陰極高さの差が０．１５μｍ程度で電
界は最も低くなる。電界が負の場合、電子は放出されな
い。負の電圧を印加する事によって画素を発光させたく
ない場合の電界を著しく低くする事ができる。従って、
２段のゲート４，５に印加する電圧を電子放出オン時に
プラスの電圧、電子放出オフ時にマイナスの電圧とする
とよい。このように電子放出陰極２とゲート４，５の位
置関係の最適化、ゲート４，５に印加する電圧の極性の
選択により電子放出の制御を容易に行うことができる。Further, in the graph of FIG. 4, one gate is positive,
When a negative voltage is applied to the other gate, the difference between the height of the gate / cathode, which is the difference between the height of the center of the insulating layer between the two gates in the film thickness direction, and the height of the electron / cathode The result of having calculated the relationship of the electric field in the point 0.01 micrometer away from the front-end | tip of an emission cathode using the finite element method is shown. In the figure, the characteristic curve with white circles indicates that when a positive voltage is applied to the upper gate 5 and a negative voltage is applied to the lower gate 4 of the two-stage gates,
The characteristic curve indicated by the black circles is intended to prevent the pixel from emitting light when a positive voltage is applied to the lower gate 4 and a negative voltage is applied to the upper gate 5 of the two gates.
The broken line shows the case where a voltage is applied to both gates of two stages, and the pixel is intended to emit light. When a positive voltage is applied to one of the gates, the electric field is affected by the height difference between the gate and the cathode, and the electric field becomes the lowest when the height difference between the gate and the cathode is about 0.15 μm. When the electric field is negative, no electrons are emitted. By applying a negative voltage, the electric field when the pixel does not want to emit light can be significantly lowered. Therefore,
The voltage applied to the two-stage gates 4 and 5 may be a positive voltage when the electron emission is on and a negative voltage when the electron emission is off. Thus, the electron emission can be easily controlled by optimizing the positional relationship between the electron emission cathode 2 and the gates 4 and 5 and selecting the polarity of the voltage applied to the gates 4 and 5.
【００１４】[0014]
【発明の効果】この発明の平面パネル型ディスプレイ
は、以上説明したように、ゲートを一軸方向に並行なア
レイ状の第１ゲートと、上記一軸と直交する方向に並行
なアレイ状の第２ゲートとの２段構造とし、上記電子放
出陰極先端部が上記第１、第２ゲート間に位置するよう
に配置し、上記第１、第２ゲートそれぞれ独立に電圧を
印加することによって、２次元に配列された画素に応じ
た電子放出を容易に選択でき、全体の素子構成、作成が
容易となる効果がある。As described above, the flat panel display of the present invention has an array-shaped first gate whose gates are parallel to one axis and an array-shaped second gate which is parallel to the direction orthogonal to the one axis. And a two-stage structure in which the tip of the electron-emitting cathode is located between the first and second gates, and a voltage is applied to each of the first and second gates independently to form a two-dimensional structure. The electron emission can be easily selected according to the arrayed pixels, and there is an effect that the entire device configuration and fabrication can be facilitated.
【図１】この発明の一実施例の平面パネル型ディスプレ
イの一部を示す模式断面図である。FIG. 1 is a schematic cross-sectional view showing a part of a flat panel type display according to an embodiment of the present invention.
【図２】この発明の一実施例の平面パネル型ディスプレ
イのゲート部分の模式平面図である。FIG. 2 is a schematic plan view of a gate portion of the flat panel display according to the embodiment of the present invention.
【図３】この発明の一実施例に係わる電界解析結果を示
すグラフである。FIG. 3 is a graph showing an electric field analysis result according to an embodiment of the present invention.
【図４】この発明の一実施例に係わる電界解析結果を示
すグラフである。FIG. 4 is a graph showing an electric field analysis result according to an example of the present invention.
【図５】この発明に係わる電子放出陰極先端での電界と
アノード電流の一般的な関係を示すグラフである。FIG. 5 is a graph showing a general relationship between the electric field and the anode current at the tip of the electron emission cathode according to the present invention.
【図６】従来の平面パネル型ディスプレイの一部を示す
模式断面図である。FIG. 6 is a schematic cross-sectional view showing a part of a conventional flat panel display.
１ 基体 ２ 電子放出陰極 ３ 絶縁層 ４ 下段ゲート ５ 上段ゲート ７ 蛍光体 ８ アノード ９ フェースパネル 1 Base 2 Electron Emission Cathode 3 Insulating Layer 4 Lower Gate 5 Upper Gate 7 Phosphor 8 Anode 9 Face Panel
Claims (1)
これら電子放出陰極から電子を放出させ、放出される電
子を制御するゲート、及び上記電子放出陰極対向面にア
ノードと上記電子の衝突に応答して可視光を発する蛍光
体を有するフェースパネルを備える平面パネル型ディス
プレイにおいて、上記ゲートを一軸方向に並行なアレイ
状の第１ゲートと、上記一軸と直交する方向に並行なア
レイ状の第２ゲートとの２段構造とし、上記電子放出陰
極先端部が上記第１、第２ゲート間に位置するように配
置し、上記第１、第２ゲートそれぞれ独立に電圧を印加
することによって２次元に配列された画素に応じた電子
放出を選択するようにしたことを特徴とする平面パネル
型ディスプレイ。1. A plurality of electron-emitting cathodes formed on a substrate,
A plane including a gate for emitting electrons from these electron-emitting cathodes and controlling the emitted electrons, and a face panel having a phosphor for emitting visible light in response to a collision between the anode and the electrons on a surface facing the electron-emitting cathode. In the panel type display, the gate has a two-stage structure including an array-shaped first gate parallel to the uniaxial direction and an array-shaped second gate parallel to the direction orthogonal to the uniaxial direction, and the electron emission cathode tip portion is It is arranged so as to be located between the first and second gates, and by applying a voltage to each of the first and second gates independently, electron emission is selected according to the pixels arranged two-dimensionally. A flat panel type display characterized in that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP750392A JP2949988B2 (en) | 1992-01-20 | 1992-01-20 | Flat panel display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP750392A JP2949988B2 (en) | 1992-01-20 | 1992-01-20 | Flat panel display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05198278A true JPH05198278A (en) | 1993-08-06 |
| JP2949988B2 JP2949988B2 (en) | 1999-09-20 |
Family
ID=11667588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP750392A Expired - Fee Related JP2949988B2 (en) | 1992-01-20 | 1992-01-20 | Flat panel display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2949988B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100522692B1 (en) * | 2003-07-02 | 2005-10-19 | 삼성에스디아이 주식회사 | Field emission device and manufacturing method thereof |
| JP2007101880A (en) * | 2005-10-04 | 2007-04-19 | Nippon Hoso Kyokai <Nhk> | Cold cathode, field emission type display, and method for driving field emission type display |
-
1992
- 1992-01-20 JP JP750392A patent/JP2949988B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100522692B1 (en) * | 2003-07-02 | 2005-10-19 | 삼성에스디아이 주식회사 | Field emission device and manufacturing method thereof |
| JP2007101880A (en) * | 2005-10-04 | 2007-04-19 | Nippon Hoso Kyokai <Nhk> | Cold cathode, field emission type display, and method for driving field emission type display |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2949988B2 (en) | 1999-09-20 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |