JPH05198245A - Chip type fuse and manufacture thereof - Google Patents
Chip type fuse and manufacture thereofInfo
- Publication number
- JPH05198245A JPH05198245A JP840792A JP840792A JPH05198245A JP H05198245 A JPH05198245 A JP H05198245A JP 840792 A JP840792 A JP 840792A JP 840792 A JP840792 A JP 840792A JP H05198245 A JPH05198245 A JP H05198245A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- coating
- ceramic substrate
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Fuses (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、チップ型ヒューズ及び
その製造法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type fuse and its manufacturing method.
【０００２】[0002]
【従来の技術】一般に電子回路部品などにおいては、過
電流が流れないようにヒューズを設けて電子機器の発
熱、火災、破損等を防止するようにしている。該ヒュー
ズとしては、近年プリント基板等に直接実装するために
チップ型のものが開発されている。2. Description of the Related Art Generally, in electronic circuit parts and the like, a fuse is provided to prevent overcurrent from flowing, thereby preventing heat generation, fire, damage, etc. of electronic equipment. As the fuse, in recent years, a chip type fuse has been developed for direct mounting on a printed circuit board or the like.
【０００３】従来ヒューズの製造法としては、特開昭６
３−２５２１１０号公報に示されるような方法がある。
この方法で製造されるヒューズは、ホーロー基板上に、
半田被膜が形成されており、過電流により半田被膜が破
断するように構成されている。A conventional fuse manufacturing method is disclosed in Japanese Patent Laid-Open No.
There is a method as disclosed in Japanese Patent Publication No. 3-252110.
The fuse manufactured by this method is
A solder coating is formed, and the solder coating is configured to break due to overcurrent.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら上記の方
法によれば、プリント基板への半田付け時に生じる熱に
より、可溶体である半田被膜の導体抵抗が増加したり、
断線してしまうという欠点がある。However, according to the above method, the heat generated during the soldering to the printed circuit board increases the conductor resistance of the solder coating which is a fusible body,
It has the drawback of breaking the wire.
【０００５】本発明は、上記の欠点のないチップ型ヒュ
ーズ及びその製造法を提供するものである。The present invention provides a chip-type fuse and a method for manufacturing the same, which does not have the above-mentioned drawbacks.
【０００６】[0006]
【課題を解決するための手段】本発明者らは、上記の欠
点について種々検討した結果、フォトエッチング法を用
いてめっき法で形成したＣｕの被膜上に電気めっき法で
Ｐｂ−Ｓｎ−Ｃｕ三元合金めっき被膜を施して可溶体部
分及び電極を構成すれば、導体回路と電極とが同一の工
程で形成することができ、かつ電極とセラミック基板と
の密着力に優れ、プリント板に半田付けする際、導体抵
抗の増加、断線等が生じないチップ型ヒューズが得られ
ることを見出した。DISCLOSURE OF THE INVENTION As a result of various studies on the above-mentioned drawbacks, the inventors of the present invention have found that a Pb-Sn-Cu three layer is formed by electroplating on a Cu coating film formed by photoetching. If the fusible part and the electrode are formed by applying the original alloy plating film, the conductor circuit and the electrode can be formed in the same process, and the electrode and the ceramic substrate have excellent adhesion and can be soldered to the printed board. It has been found that a chip-type fuse can be obtained which does not cause an increase in conductor resistance or disconnection.
【０００７】本発明はセラミック基板の表面に形成され
た導体回路及び電極の上面にＰｂ−Ｓｎ−Ｃｕ三元合金
被膜が形成され、前記セラミック基板の上部露出面及び
Ｐｂ−Ｓｎ−Ｃｕ三元合金被膜の上面がシリコーン被膜
で被覆されたチップ型ヒューズ並びに複数個のチップ型
ヒューズを一括して形成するセラミック基板の表面を粗
化し、無電解めつき法でＣｕの被膜を形成し、ついでＣ
ｕの被膜の上面にレジスト膜を形成し、しかる後露光、
現像、エッチング、レジスト膜の剥離をし、Ｃｕの被膜
の必要な部分のみを残して導体回路及び電極を形成し、
さらに導体回路及び電極の上面に電気めっき法でＰｂ−
Ｓｎ−Ｃｕ三元合金被膜を形成し、前記セラミック基板
の上部露出面及び導体回路の上面に形成したＰｂ−Ｓｎ
−Ｃｕ三元合金被膜の上面をシリコーン被膜で被覆した
後、前記セラミック基板を個々に分割してチップ状に成
形するチップ型ヒューズの製造法に関する。According to the present invention, a Pb-Sn-Cu ternary alloy coating is formed on the upper surface of a conductor circuit and an electrode formed on the surface of a ceramic substrate, and the upper exposed surface of the ceramic substrate and the Pb-Sn-Cu ternary alloy are formed. The surface of a ceramic substrate on which a chip-type fuse whose upper surface is coated with a silicone film and a plurality of chip-type fuses are formed at one time is roughened, and a Cu film is formed by an electroless plating method.
A resist film is formed on the upper surface of the u film, and then exposed,
Developing, etching, peeling off the resist film, and forming the conductor circuit and electrodes, leaving only the necessary portions of the Cu coating,
Further, Pb- is formed on the upper surface of the conductor circuit and the electrode by electroplating.
Pb-Sn formed by forming a Sn-Cu ternary alloy coating on the upper exposed surface of the ceramic substrate and the upper surface of the conductor circuit.
A method of manufacturing a chip-type fuse in which the upper surface of a Cu ternary alloy coating is coated with a silicone coating and then the ceramic substrate is divided into individual chips to be molded into chips.
【０００８】本発明においてＰｂ−Ｓｎ−Ｃｕ三元合金
被膜は、電気めっき法で形成され、他の方法例えば蒸着
法、スパッタ法では特殊な装置を必要とするため高価と
なり不適である。Ｐｂ−Ｓｎ−Ｃｕ三元合金被膜の厚さ
については特に制限はないが、作業性の面から１〜１５
μｍの範囲であることが好ましい。In the present invention, the Pb-Sn-Cu ternary alloy coating is formed by the electroplating method, and other methods such as the vapor deposition method and the sputtering method require special equipment and are expensive and unsuitable. The thickness of the Pb-Sn-Cu ternary alloy coating film is not particularly limited, but it is 1 to 15 from the viewpoint of workability.
It is preferably in the range of μm.
【０００９】セラミック基板の材質としては、アルミ
ナ、ＰＺＴ（鉛、ジルコニア及びチタンを主成分とした
もの）、ムライト、チッ化アルミニウム等が用いられ
る。セラミック基板の表面を粗化する方法については特
に制限はないが、セラミック基板を融点以上の温度に加
熱したアルカリ融液中に３０秒以上浸漬して粗化すれば
作業性に優れ、またばらつきが少なく、均一に粗化する
ことができるので好ましい。As the material of the ceramic substrate, alumina, PZT (having lead, zirconia and titanium as the main components), mullite, aluminum nitride or the like is used. The method of roughening the surface of the ceramic substrate is not particularly limited, but if the ceramic substrate is immersed in an alkali melt heated to a temperature of the melting point or higher for 30 seconds or more to roughen it, workability is excellent, and there are variations. It is preferable because it is less and can be uniformly roughened.
【００１０】Ｃｕの被膜は、無電解めっき法で形成する
ものとし、電気めっき法ではリード端子を必要とするた
め工程が煩雑となり、まためっきの厚さにばらつきが生
じ、他の蒸着法、スパツタ法では特殊な装置を必要とす
るため高価になるという欠点が生じる。Ｃｕの被膜の厚
さについても特に制限はないが、作業性の面から５〜３
０μｍの範囲であることが好ましい。The Cu coating is formed by an electroless plating method, and the electroplating method requires lead terminals, which complicates the process and causes variations in the plating thickness. The method has the disadvantage of being expensive because it requires special equipment. The thickness of the Cu coating is not particularly limited, but it is 5 to 3 from the viewpoint of workability.
It is preferably in the range of 0 μm.
【００１１】シリコーン被膜の形成については特に制限
はないが、作業性の面からシリコーン樹脂溶液を塗布し
て硬化させることが好ましい。The formation of the silicone coating is not particularly limited, but it is preferable to apply and cure the silicone resin solution from the viewpoint of workability.
【００１２】本発明では必要に応じ、電極となる部分に
形成したＰｂ−Ｓｎ−Ｃｕ三元合金被膜を除去した後、
露出したＣｕの被膜上面にめつき法でＮｉ及びＡｕの被
膜が形成される。In the present invention, after removing the Pb-Sn-Cu ternary alloy coating formed on the portion to be the electrode, if necessary,
Ni and Au coatings are formed on the exposed upper surface of the Cu coating by the plating method.
【００１３】[0013]
【実施例】以下本発明の実施例を説明する。EXAMPLES Examples of the present invention will be described below.
【００１４】実施例１ 図３の（ａ）に示すように複数個のチップ型ヒューズを
一括して形成した直径が０．８ｍｍ（φ）のスルーホー
ル５を形成したアルミナセラミック基板（日立化成工業
製、商品名ハロックス５５２、寸法８０×８０×厚さ
０．６３５ｍｍ）２を脱脂液（日立化成工業製、商品名
ＨＣＲ−２０１）で洗浄し、乾燥後ＮＨ4Ｆ１０ｇ（４
０．５重量％）、（ＮＨ4）2ＳＯ4 １ｇ（４．１重量
％）、濃Ｈ2ＳＯ4 ２ｍｌ（１４．９重量％）及びＨ2
Ｏ １０ｍｌ（４０．５重量％）の混合溶液（液温７０
℃）中に１０分間浸漬して粗化を行った。なお図３の
（ａ）において１２は基板分割部である。Example 1 As shown in FIG. 3 (a), an alumina ceramic substrate having a through hole 5 having a diameter of 0.8 mm (φ) formed by collectively forming a plurality of chip-type fuses (Hitachi Chemical Industry Co., Ltd.) Made, product name Harox 552, size 80 × 80 × thickness 0.635 mm) 2 was washed with a degreasing liquid (Hitachi Chemical Co., Ltd. product name HCR-201), and after drying NH 4 F 10 g (4
0.5% by weight), (NH 4 ) 2 SO 4 1 g (4.1% by weight), concentrated H 2 SO 4 2 ml (14.9% by weight) and H 2
O 10 ml (40.5 wt%) mixed solution (liquid temperature 70
C.) was immersed for 10 minutes for roughening. In FIG. 3A, reference numeral 12 is a board dividing portion.
【００１５】次に流水中で十分に水洗し、乾燥後３５０
℃に加熱したＮａＯＨ融液中に５分間浸漬して再粗化を
行った。この後濃度１０重量％のＨ2ＳＯ4溶液中に５分
間浸漬し、超音波（出力３００Ｗ）による振動エネルギ
ーを付与し、アルミナセラミック基板２の表面を中和
し、ついで水洗を行い、無電解Ｃｕめっきを２時間行っ
て図３の（ｂ）に示すように厚さ４μｍのＣｕの被膜６
を形成した。なお無電解Ｃｕめっき液はｐＨが１２．４
で表１に示す組成のものを用いた。Next, after thoroughly washing with running water and drying, 350
Re-roughening was carried out by immersing in a NaOH melt heated to ℃ for 5 minutes. After that, it is immersed in a H 2 SO 4 solution having a concentration of 10% by weight for 5 minutes, vibrational energy by ultrasonic waves (output 300 W) is applied to neutralize the surface of the alumina ceramic substrate 2, and then washing with water is performed, and electroless electrolysis is performed. After Cu plating for 2 hours, a Cu coating 6 having a thickness of 4 μm is formed as shown in FIG.
Formed. The electroless Cu plating solution has a pH of 12.4.
The composition shown in Table 1 was used.
【００１６】[0016]
【表１】 [Table 1]
【００１７】Ｃｕめっき後感光性レジストフィルム（日
立化成工業製、商品名ＰＨＴ−８６２ＡＦ−２５）を前
記Ｃｕの被膜６上に全面貼付し、さらにその上面に、得
られる導体回路と同形状に透明な部分を形成したネガフ
ィルム（図示せず）を貼付した後、露光してネガフィル
ムの透明な部分の下面に配設した感光性レジストフィル
ムを硬化させた。ついでネガフィルムを取り除き、さら
に現像して硬化していない部分、詳しくは露光していな
い部分の感光性レジストフィルムを除去し、図３の
（ｃ）に示すようなレジスト膜１１を形成した。しかる
後濃度２５重量％の過硫酸アンモニウムの溶液でエッチ
ングを行い図３の（ｄ）に示すように導体回路として不
必要な部分の銅の被膜６を除去した。After Cu plating, a photosensitive resist film (trade name: PHT-862AF-25, manufactured by Hitachi Chemical Co., Ltd.) was attached on the entire surface of the Cu coating film 6, and the upper surface thereof was transparent in the same shape as the conductor circuit to be obtained. After a negative film (not shown) on which the negative portion was formed was attached, the negative resist film was exposed to light to cure the photosensitive resist film provided on the lower surface of the transparent portion of the negative film. Then, the negative film was removed, and the photosensitive resist film in the unhardened portion, specifically, the unexposed portion was further developed and removed to form a resist film 11 as shown in FIG. 3 (c). Thereafter, etching was performed with a solution of ammonium persulfate having a concentration of 25% by weight to remove the copper coating film 6 which is unnecessary for the conductor circuit as shown in FIG. 3 (d).
【００１８】この後濃度５重量％のＮａＯＨ溶液で硬化
している感光性レジストフィルムを剥離し、図３の
（ｅ）に示すように導体回路３及び電極４を同時に形成
したセラミック配線板を得た。Thereafter, the photosensitive resist film cured with a 5 wt% NaOH solution was peeled off to obtain a ceramic wiring board on which the conductor circuit 3 and the electrode 4 were simultaneously formed as shown in FIG. 3 (e). It was
【００１９】次に該セラミック配線板を脱脂液（日立化
成工業製、商品名ＨＣＲ−２０１）で洗浄し、水洗後、
濃度１０重量％のＨ2ＳＯ4溶液中に１分間浸漬し、水洗
後、電気Ｐｂ−Ｓｎ−Ｃｕ三元合金めつきを４５分間行
い、図３の（ｆ）に示すように導体回路３及び電極４の
上面に厚さ１０μｍのＰｂ−Ｓｎ−Ｃｕ三元合金被膜７
を形成した。なお電気Ｐｂ−Ｓｎ−Ｃｕめっき液は、表
２に示す組成のものを用い浴温２２℃、電流密度０．０
０５Ａ／ｍ2の条件でめっきを行った。Next, the ceramic wiring board is washed with a degreasing liquid (Hitachi Chemical Co., Ltd., trade name HCR-201), and after washing with water,
It is immersed in a H 2 SO 4 solution having a concentration of 10 wt% for 1 minute, washed with water, and then plated with an electric Pb-Sn-Cu ternary alloy for 45 minutes. As shown in FIG. Pb-Sn-Cu ternary alloy coating 7 having a thickness of 10 μm on the upper surface of the electrode 4
Formed. The electric Pb-Sn-Cu plating solution having the composition shown in Table 2 was used, and the bath temperature was 22 ° C and the current density was 0.0.
Plating was performed under the conditions of 05 A / m 2 .
【００２０】[0020]
【表２】 [Table 2]
【００２１】Ｐｂ−Ｓｎ−Ｃｕ三元合金めつき後、水
洗、水切り、乾燥し、印刷法でアルミナセラミック基板
２の上部露出面及び導体回路３の上面に形成したＰｂ−
Ｓｎ−Ｃｕ三元合金被膜７の上面にシリコーン樹脂溶液
（東レ・ダウ・コーニング製、商品名ＳＥ−１７００）
を７０μｍの厚さに塗布し、オーブン中で、１３０℃で
１５分間硬化させ、図３の（ｇ）に示すようにシリコー
ン被膜１０を形成した。さらに電極４の上面に形成した
Ｐｂ−Ｓｎ−Ｃｕ三元合金被膜７の露出部分を従来公知
の方法で選択的にエッチングして除去し電極４のＣｕの
被膜を露出させた。なおエッチング液は、奧野製薬製の
商品名ＯＰＣリップソルダーＴを用い、浴温２４℃で３
分間浸漬した。After the Pb-Sn-Cu ternary alloy was plated, it was washed with water, drained and dried, and Pb-formed on the upper exposed surface of the alumina ceramic substrate 2 and the upper surface of the conductor circuit 3 by a printing method.
Silicone resin solution (Toray Dow Corning, trade name SE-1700) on the upper surface of the Sn-Cu ternary alloy coating 7
Was applied to a thickness of 70 μm and cured in an oven at 130 ° C. for 15 minutes to form a silicone coating 10 as shown in FIG. Further, the exposed portion of the Pb-Sn-Cu ternary alloy coating 7 formed on the upper surface of the electrode 4 was selectively etched and removed by a conventionally known method to expose the Cu coating of the electrode 4. The etching solution used was OPC Lip Solder T, a trade name of Utano Pharmaceutical Co., Ltd.
Soaked for a minute.
【００２２】ついで脱脂液（日立化成工業製、商品名Ｈ
ＣＲ−２０１）で洗浄し、水洗後、濃度１０重量％のＨ
2ＳＯ4溶液中に１分間浸漬し、再度水洗後、従来公知の
方法で無電解Ｎｉ及びＡｕめっきを施し、図３の（ｉ）
に示すようにそれぞれ厚さ２．０μｍ及び０．１μｍの
Ｎｉの被膜８及びＡｕの被膜９を形成したチップ型ヒュ
ーズ基板を得た。なお無電解Ｎｉめっき液は日本カニゼ
ン製の商品名Ｓ−６８０を用い、浴温７０℃で１０分間
行い、無電解Ａｕめっき液はＥＥＪＡ製の商品名レクト
ロレスプレップを用い浴温９０℃で１０分間行った。Next, a degreasing liquid (Hitachi Chemical Co., Ltd., trade name H
After washing with CR-201) and washing with water, H with a concentration of 10% by weight
It is immersed in a 2 SO 4 solution for 1 minute, washed again with water, and then subjected to electroless Ni and Au plating by a conventionally known method.
A chip-type fuse substrate having a Ni coating 8 and an Au coating 9 having a thickness of 2.0 μm and 0.1 μm, respectively, was obtained as shown in FIG. The electroless Ni plating solution used was S-680 (trade name, manufactured by Kanigen Japan), and the bath temperature was 70 ° C. for 10 minutes. I went for a minute.
【００２３】このようにして得られたチップ型ヒューズ
基板をスライシングマシーン（ディスコ製、商品名ＤＡ
Ｄ−２Ｈ−６）を用いて基板分割部１２で個々に分割
し、図１及び図２に示すチップ型ヒューズ１を得た。The chip-type fuse substrate thus obtained is used as a slicing machine (manufactured by DISCO, trade name DA
D-2H-6) was used to individually divide the substrate by the substrate dividing section 12 to obtain the chip-type fuse 1 shown in FIGS.
【００２４】比較例１ Ｐｂ−Ｓｎ−Ｃｕ三元合金めっきに代えて厚さ１０μｍ
のＰｂ−Ｓｎめっきを施した以外は実施例１と同様の工
程を経てチップ型ヒューズを得た。なおＰｂ−Ｓｎめっ
き液は、上村工業製の商品名リードＳＢを用い、浴温２
０℃で４０分間めっきを行った。Comparative Example 1 10 μm thick instead of Pb-Sn-Cu ternary alloy plating
A chip-type fuse was obtained through the same steps as in Example 1 except that the Pb-Sn plating was performed. The Pb-Sn plating solution used was Lead SB manufactured by Uemura Kogyo, and the bath temperature was 2
Plating was performed at 0 ° C. for 40 minutes.
【００２５】次に実施例１及び比較例１で得られたチッ
プ型ヒューズを２４０℃及び３００℃に加熱溶融した
６：４半田（Ｐｂ：Ｓｎ＝６：４）中に５秒間浸漬した
後引上げ、再度５秒間浸漬するという工程を５回繰して
半田耐熱性試験を行った。この結果を表３に示す。Next, the chip-type fuses obtained in Example 1 and Comparative Example 1 were immersed in 6: 4 solder (Pb: Sn = 6: 4) which was heated and melted at 240 ° C. and 300 ° C. for 5 seconds and then pulled up. Then, the solder heat resistance test was performed by repeating the step of immersing again for 5 seconds five times. The results are shown in Table 3.
【００２６】[0026]
【表３】 [Table 3]
【００２７】表３から明らかなように本発明の実施例に
なるチップ型ヒューズは、比較例のチップ型ヒューズに
比較して抵抗値変化率が小さく、半田耐熱性に優れるこ
とがわかる。As is clear from Table 3, the chip-type fuse according to the embodiment of the present invention has a smaller rate of change in resistance value and excellent solder heat resistance than the chip-type fuse of the comparative example.
【００２８】[0028]
【発明の効果】本発明になるチップ型ヒューズは、セラ
ミック基板と電極との密着力に優れ、また半田耐熱性に
優れるため導体抵抗の増加、断線等が生ぜず、さらに電
極形成工程と導体回路形成工程とを同一工程で形成でき
るため量産化に優れ、工業的に極めて好適なチップ型ヒ
ューズである。The chip-type fuse according to the present invention is excellent in the adhesion between the ceramic substrate and the electrodes, and is also excellent in the heat resistance of the solder, so that the conductor resistance does not increase and the wire breakage does not occur. The chip type fuse is excellent in mass production because it can be formed in the same step as the forming step and is industrially extremely suitable.
【図１】本発明の実施例になるチップ型ヒューズの斜視
図である。FIG. 1 is a perspective view of a chip fuse according to an embodiment of the present invention.
【図２】図１のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.
【図３】本発明の実施例になるチップ型ヒューズの製造
作業状態を示す断面図である。FIG. 3 is a cross-sectional view showing a manufacturing operation state of the chip fuse according to the embodiment of the present invention.
１ チップ型ヒューズ ２ アルミナセラミック基板 ３ 導体回路 ４ 電極 ５ スルーホール ６ Ｃｕの被膜 ７ Ｐｂ−Ｓｎ−Ｃｕ三元合金被膜 ８ Ｎｉの被膜 ９ Ａｕの被膜 １０ シリコーン被膜 １１ レジスト膜１２ 基板分割部 DESCRIPTION OF SYMBOLS 1 Chip type fuse 2 Alumina ceramic substrate 3 Conductor circuit 4 Electrode 5 Through hole 6 Cu coating 7 Pb-Sn-Cu ternary alloy coating 8 Ni coating 9 Au coating 10 Silicone coating 11 Resist film 12 Substrate part
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中村 正則 茨城県勝田市大字足崎字西原1380番地１ 日立化成セラミックス株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masanori Nakamura 1380 Nishihara, Katsuta-shi, Ibaraki, Osaka, Japan 1 Hitachi Chemicals Co., Ltd.
Claims (2)
回路及び電極の上面にＰｂ−Ｓｎ−Ｃｕ三元合金被膜が
形成され、前記セラミック基板の上部露出面及びＰｂ−
Ｓｎ−Ｃｕ三元合金被膜の上面がシリコーン被膜で被覆
されたチップ型ヒューズ。1. A Pb-Sn-Cu ternary alloy coating is formed on the upper surface of a conductor circuit and an electrode formed on the surface of a ceramic substrate, and the upper exposed surface of the ceramic substrate and Pb-
A chip-type fuse in which the upper surface of a Sn-Cu ternary alloy coating is covered with a silicone coating.
成するセラミック基板の表面を粗化し、無電解めつき法
でＣｕの被膜を形成し、ついでＣｕの被膜の上面にレジ
スト膜を形成し、しかる後露光、現像、エッチング、レ
ジスト膜の剥離をし、Ｃｕの被膜の必要な部分のみを残
して導体回路及び電極を形成し、さらに導体回路及び電
極の上面に電気めっき法でＰｂ−Ｓｎ−Ｃｕ三元合金被
膜を形成し、前記セラミック基板の上部露出面及び導体
回路の上面に形成したＰｂ−Ｓｎ−Ｃｕ三元合金被膜の
上面をシリコーン被膜で被覆した後、前記セラミック基
板を個々に分割してチップ状に形成することを特徴とす
るチップ型ヒューズの製造法。2. A surface of a ceramic substrate on which a plurality of chip fuses are collectively formed is roughened, a Cu film is formed by an electroless plating method, and then a resist film is formed on the upper surface of the Cu film. After that, exposure, development, etching, and peeling of the resist film are performed, and a conductor circuit and an electrode are formed by leaving only a necessary portion of the Cu coating film. Further, Pb-Sn is formed on the upper surface of the conductor circuit and the electrode by electroplating. After forming a Cu ternary alloy coating and coating the upper exposed surface of the ceramic substrate and the upper surface of the Pb-Sn-Cu ternary alloy coating formed on the upper surface of the conductor circuit with a silicone coating, the ceramic substrates are individually A method of manufacturing a chip-type fuse, which is characterized in that the chip-shaped fuse is divided into chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP840792A JPH05198245A (en) | 1992-01-21 | 1992-01-21 | Chip type fuse and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP840792A JPH05198245A (en) | 1992-01-21 | 1992-01-21 | Chip type fuse and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05198245A true JPH05198245A (en) | 1993-08-06 |
Family
ID=11692309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP840792A Pending JPH05198245A (en) | 1992-01-21 | 1992-01-21 | Chip type fuse and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05198245A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9666547B2 (en) | 2002-10-08 | 2017-05-30 | Honeywell International Inc. | Method of refining solder materials |
-
1992
- 1992-01-21 JP JP840792A patent/JPH05198245A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9666547B2 (en) | 2002-10-08 | 2017-05-30 | Honeywell International Inc. | Method of refining solder materials |
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