JPH05182973A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05182973A
JPH05182973A JP4000539A JP53992A JPH05182973A JP H05182973 A JPH05182973 A JP H05182973A JP 4000539 A JP4000539 A JP 4000539A JP 53992 A JP53992 A JP 53992A JP H05182973 A JPH05182973 A JP H05182973A
Authority
JP
Japan
Prior art keywords
bump
solder
film
substrate
paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4000539A
Other languages
Japanese (ja)
Inventor
Hajime Kiyokawa
肇 清川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4000539A priority Critical patent/JPH05182973A/en
Publication of JPH05182973A publication Critical patent/JPH05182973A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder

Abstract

PURPOSE:To restrain an irregularity in the height of a solder bump forming a bump shape and to enhance the strength of the solder bump by a method wherein conductive fillers having a large particle size are mixed with a solder paste, the whole surface of a chip is coated with the solder paste and a heat treatment is executed. CONSTITUTION:An Al pad 2 is formed on a semiconductor substrate 1; a cover film 3 is grown on it by a vapor growth method. Then, a polyimide film 4 is applied to the whole surface of the substrate; a Ti film 5 and a Pd film 6 are applied as barrier metal films. Metal balls which can be eutectic with a solder, e.g. Au or Cu whose particle size is 70 to 100mum, as conductive fillers are mixed with a paste in which an organic acid, a Pd powder and an Sn powder have been diffused into an organic solvent in the ratio of 1:4 to 1:25 in terms of their volume percentage. The whole surface of the substrate is coated with the solder paste 7 with which the fillers have been mixed; a heat treatment is executed to the substrate at 200 to 320 deg.C for several minutes. Thereby, a solder alloy bump 7A is formed selectively only the barrier metal film. At this time, the conductive fillers act as a role to form the framework of the bump, and the height of the bump becomes uniform.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
係り，特に半導体チップの接続端子となるバンプの形成
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming bumps which are connection terminals of a semiconductor chip.

【０００２】近年，高密度実装が進み，基板またはフィ
ルムへのチップの接続（ボンディング）には半田バンプ
が要求されている。そのため半田バンプを，寸法のばら
つきを少なく且つ安定に形成させる必要がある。In recent years, high-density mounting has advanced, and solder bumps are required for connecting (bonding) chips to a substrate or a film. Therefore, it is necessary to form the solder bump stably with little variation in dimensions.

【０００３】[0003]

【従来の技術】高密度実装の進展に伴い, 印刷配線され
たフィルム状のテープにチップを自動機で接合するTAB
(Tape Automated Bonding)や, 基板上へチップを反転し
て接合するフリップチップボンディングが用いられてい
る。TAB ではバンプはチップ周辺部に形成されている
が, フリップチップボンディングではチップ内部の接合
点にもバンプを形成する所謂エリアバンプ(Area Bump)
形成工程が要求され，この場合は特にバンプの高さの制
御が重要である。2. Description of the Related Art With the progress of high-density packaging, TAB is used to bond chips to a film-shaped tape with printed wiring by an automatic machine.
(Tape Automated Bonding) and flip-chip bonding are used to invert and bond the chip onto the substrate. With TAB, bumps are formed around the chip, but with flip chip bonding, bumps are also formed at the junction points inside the chip, so-called area bumps.
A forming process is required, and in this case, control of the bump height is especially important.

【０００４】いずれにしても, 従来は半田メッキ法によ
って, チップ上に被着されたカバー絶縁膜の開口部に露
出された金属パッド上に半田メッキし, 熱処理により形
状に丸みをつけて半田バンプを形成していた。In any case, conventionally, the solder plating method is used to perform solder plating on the metal pad exposed in the opening of the cover insulating film deposited on the chip, and the solder bump is formed by heat treatment to round the shape. Had formed.

【０００５】[0005]

【発明が解決しようとする課題】ところが, 半田バンプ
は熱処理後その高さにばらつきを生じていた。例えば,
鉛(Pb)/ 錫(Sn)半田の場合の高さを 100μｍとすると,
そのばらつきは10％以上あり，そのため高精度高密度実
装が困難となり, 接合歩留りの低下を招いていた。However, the solder bumps have a variation in height after heat treatment. For example,
If the height of lead (Pb) / tin (Sn) solder is 100 μm,
The variation was 10% or more, which made it difficult to perform high-precision and high-density mounting, and resulted in a decrease in bonding yield.

【０００６】本発明はチップ上でバンプの高さを揃える
ことを目的とする。It is an object of the present invention to make bump heights uniform on a chip.

【０００７】[0007]

【課題を解決するための手段】上記課題の解決は， １）バンプ材料と, 該バンプ材料の粒径より大きく且つ
該バンプ材料と共晶化する金属粒からなる導電性フィラ
とを有機溶剤中に混入したペーストを半導体基板上に塗
布し，次いで該基板を熱処理して該基板上に形成された
金属膜上に選択的にバンプを形成する半導体装置の製造
方法，あるいは ２）前記導電性フィラがAu, またはCu, またはSn, また
はAg, またはNiからなる金属球である前記１）記載の半
導体装置の製造方法，あるいは ３）前記導電性フィラの粒径が少なくともバンプ材料の
粉末の２倍以上で且つバンプ高さの１／２以下である前
記１）または２）記載の半導体装置の製造方法により達
成される。Means for Solving the Problems To solve the above problems, 1) a bump material and a conductive filler made of metal particles larger than the particle diameter of the bump material and eutecticized with the bump material in an organic solvent. Or a method of manufacturing a semiconductor device, wherein the paste mixed in the above is applied on a semiconductor substrate, and then the substrate is heat-treated to selectively form bumps on a metal film formed on the substrate, or 2) the conductive filler. Wherein 1 is a metal sphere made of Au, Cu, Sn, Ag, or Ni, or 3) the conductive filler has a particle size at least twice that of the powder of the bump material. This is achieved by the method of manufacturing a semiconductor device as described above in 1) or 2), which is not more than 1/2 of the bump height.

【０００８】[0008]

【作用】本発明ではバンプ形成工程において, 半田ペー
スト中に粒径の大きい導電性フィラを入れてチップ上全
面に塗布し, 熱処理することによりバリアメタル上にの
み選択的に半田合金からなるバンプを形成している。In the present invention, in the bump forming process, a conductive filler having a large particle size is put in a solder paste and applied on the entire surface of the chip, and a heat treatment is performed to form a bump made of a solder alloy only on the barrier metal. Is forming.

【０００９】この場合, 本発明者の実験によれば上記フ
ィラの存在によりバンプ高さのばらつきが低減している
ことが確認された。これは, パンプ内には少なくとも２
個以上のフィラが入り，これがバンプ形状を形成する骨
格となって半田バンプの高さのばらつきを抑え，強度を
向上させているものと考えられる。In this case, according to the experiments by the present inventors, it was confirmed that the presence of the filler reduces the variation in bump height. This is at least 2 in the pump
It is thought that more than one filler is inserted, and this becomes the skeleton that forms the bump shape, suppressing variation in the height of the solder bump and improving the strength.

【００１０】[0010]

【実施例】図１(A) 〜(D) は本発明の実施例を説明する
断面図である。図１(A) において，半導体基板１上にア
ルミニウム(Al)からなるパッド２を形成し，その上に，
気相成長(CVD) 法により，カバー膜３として, 例えばり
ん珪酸ガラス(PSG) 膜とプラズマ窒化シリコン (SiX N
Y ) 膜を順に成長する。1 (A) to 1 (D) are sectional views for explaining an embodiment of the present invention. In FIG. 1A, a pad 2 made of aluminum (Al) is formed on a semiconductor substrate 1, and
As a cover film 3, for example, a phosphosilicate glass (PSG) film and a plasma silicon nitride (Si X N
Y ) The film is grown in sequence.

【００１１】次いで，パッド２上のカバー膜３を開口す
る。図１(B) において，基板上全面にポリイミド膜４を
被着し，ドライエッチングまたはリフトオフ法によりパ
ッド２上を開口する。Next, the cover film 3 on the pad 2 is opened. In FIG. 1 (B), a polyimide film 4 is deposited on the entire surface of the substrate and an opening is formed on the pad 2 by dry etching or lift-off method.

【００１２】次いで，バリアメタル膜としてチタン(Ti)
膜５とパラジウム(Pd)膜６を被着し，これらの膜をパタ
ーニングしてパッド２上の領域を残す。図１(C) におい
て，有機酸パラジウム（有機酸Pd) とSn粉末（粒径25〜
50μｍ) を有機溶媒中に拡散させたペースト中に, 導電
性フィラとして，半田と共晶可能な金属球，例えば粒径
70〜100 μｍのAu, Cu, Sn, Ag, Ni等からなる球を半田
に対し体積率で（１：４）〜（１：25）の割合で混入す
る。Next, titanium (Ti) is used as a barrier metal film.
A film 5 and a palladium (Pd) film 6 are deposited, and these films are patterned to leave a region on the pad 2. In Fig. 1 (C), organic acid palladium (organic acid Pd) and Sn powder (particle size 25 ~
(50 μm) in a paste that is dispersed in an organic solvent, and as a conductive filler, metal spheres that can be eutectic with solder, such as particle size
70 to 100 μm spheres made of Au, Cu, Sn, Ag, Ni, etc. are mixed in the solder in a volume ratio of (1: 4) to (1:25).

【００１３】このフィラ混入ペースト（有機酸Pd＋Sn粉
末＋有機溶媒＋導電性フィラ）７を基板上全面に塗布す
る。図１(D) において，基板に 200〜320 ℃で数分間の
熱処理を加えると，バリアメタル膜上にだけ選択的に半
田合金パンプ7Aが形成される。この場合導電性フィラが
バンプの骨格を形成する役目を果たしバンプの高さが揃
うようになる。また, ポリイミド膜４上に半田球7Bが形
成されるがこれはエチルアルコール, イソプロピルアル
コール等で洗い落とす。This filler-containing paste (organic acid Pd + Sn powder + organic solvent + conductive filler) 7 is applied to the entire surface of the substrate. In Fig. 1 (D), when the substrate is heat-treated at 200-320 ℃ for several minutes, the solder alloy pump 7A is selectively formed only on the barrier metal film. In this case, the conductive filler plays the role of forming the skeleton of the bump, and the height of the bump becomes uniform. Further, solder balls 7B are formed on the polyimide film 4, but these are washed off with ethyl alcohol, isopropyl alcohol or the like.

【００１４】実施例では有機酸PdとSn粉末を有機溶媒中
に拡散させたペーストを用いたが,単なるPd, Sn粉末を
有機溶媒中に拡散させたペーストを用いてもよく,またI
n系半田の場合は, In粉末とAuまたはAgまたはSnまたはN
i粉末を有機溶媒中に拡散させたペーストを用いてもよ
い。In the examples, a paste prepared by diffusing organic acid Pd and Sn powder in an organic solvent was used, but a paste prepared by diffusing simple Pd and Sn powder in an organic solvent may be used.
In the case of n-based solder, In powder and Au or Ag or Sn or N
A paste in which i powder is dispersed in an organic solvent may be used.

【００１５】これらの場合, 導電性フィラとして導入す
る金属球の粒径は, 少なくとも半田として使用される金
属粉末の２倍以上，およびバンプ高さの１／２以下とす
ればよいことが，種々実験の結果分かった。In these cases, the particle diameter of the metal spheres introduced as the conductive filler should be at least twice the metal powder used as solder and less than half the bump height. I understood the result of the experiment.

【００１６】[0016]

【発明の効果】本発明によれば, バンプの高さ±５％に
揃えることができた。この結果, 特にチップ中央部に存
在するエリアバンプの接合の信頼性が向上した。According to the present invention, the bump height can be adjusted to ± 5%. As a result, the reliability of the bonding of the area bumps existing especially in the central part of the chip was improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の実施例を説明する断面図FIG. 1 is a sectional view illustrating an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ 半導体基板 ２ パッド ３ カバー膜（下層PSG 膜と上層SiX N Y 膜からなる） ４ ポリイミド膜 ５ バリアメタル膜でTi膜 ６ バリアメタル膜でPd膜 ７ 本発明のペースト 7A 本発明のバンプ 7B 半田球 ８ 導電性フィラ1 semiconductor substrate 2 pad 3 cover film (consisting of lower PSG film and upper Si X N Y film) 4 polyimide film 5 Ti film with barrier metal film 6 Pd film with barrier metal film 7 Paste 7A of the present invention 7A Bump of the present invention 7B Solder ball 8 Conductive filler

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 バンプ材料と, 該バンプ材料の粒径より
大きく且つ該バンプ材料と共晶化する金属粒からなる導
電性フィラとを有機溶剤中に混入したペーストを半導体
基板上に塗布し，次いで該基板を熱処理して該基板上に
形成された金属膜上に選択的にバンプを形成することを
特徴とする半導体装置の製造方法。1. A paste in which an organic solvent is mixed with a bump material and a conductive filler having a grain size larger than that of the bump material and which is eutectic with the bump material is applied onto a semiconductor substrate, Then, the substrate is heat-treated to selectively form bumps on the metal film formed on the substrate. 【請求項２】 前記導電性フィラがAu, またはCu, また
はSn, またはAg, またはNiからなる金属球であることを
特徴とする請求項１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive filler is a metal sphere made of Au, Cu, Sn, Ag, or Ni. 【請求項３】 前記導電性フィラの粒径が少なくともバ
ンプ材料の粉末の２倍以上で且つバンプ高さの１／２以
下であることを特徴とする請求項１または２記載の半導
体装置の製造方法。3. The manufacturing of a semiconductor device according to claim 1, wherein the particle diameter of the conductive filler is at least twice as large as the powder of the bump material and 1/2 or less of the bump height. Method.
JP4000539A 1992-01-07 1992-01-07 Manufacture of semiconductor device Withdrawn JPH05182973A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4000539A JPH05182973A (en) 1992-01-07 1992-01-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4000539A JPH05182973A (en) 1992-01-07 1992-01-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05182973A true JPH05182973A (en) 1993-07-23

Family

ID=11476554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4000539A Withdrawn JPH05182973A (en) 1992-01-07 1992-01-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05182973A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2799337A1 (en) * 1999-10-05 2001-04-06 St Microelectronics Sa METHOD FOR MAKING ELECTRICAL CONNECTIONS ON THE SURFACE OF A SEMICONDUCTOR PACKAGE WITH ELECTRICAL CONNECTION DROPS
US6344690B1 (en) 1997-09-08 2002-02-05 Fujitsu Limited Semiconductor device with gold bumps, and method and apparatus of producing the same
KR100399338B1 (en) * 2001-01-12 2003-09-26 주식회사 암트론 Compositions and Preparation Methods of Solder Alloys for Surface Mount Technology Applications
US6959856B2 (en) 2003-01-10 2005-11-01 Samsung Electronics Co., Ltd. Solder bump structure and method for forming a solder bump
US7271084B2 (en) 2003-01-10 2007-09-18 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
US8022551B2 (en) * 2000-06-12 2011-09-20 Renesas Electronics Corporation Solder composition for electronic devices
US10591529B2 (en) 2015-12-25 2020-03-17 Mitsubishi Aircraft Corporation Wiring safety evaluation system and wiring safety evaluation method
US11901325B2 (en) 2015-01-13 2024-02-13 Dexerials Corporation Multilayer substrate

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6344690B1 (en) 1997-09-08 2002-02-05 Fujitsu Limited Semiconductor device with gold bumps, and method and apparatus of producing the same
FR2799337A1 (en) * 1999-10-05 2001-04-06 St Microelectronics Sa METHOD FOR MAKING ELECTRICAL CONNECTIONS ON THE SURFACE OF A SEMICONDUCTOR PACKAGE WITH ELECTRICAL CONNECTION DROPS
EP1091627A1 (en) * 1999-10-05 2001-04-11 STMicroelectronics SA Process for providing electrical connections on the surface of a semiconductor package using electrical connection bumps
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KR100399338B1 (en) * 2001-01-12 2003-09-26 주식회사 암트론 Compositions and Preparation Methods of Solder Alloys for Surface Mount Technology Applications
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US7271084B2 (en) 2003-01-10 2007-09-18 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
US11901325B2 (en) 2015-01-13 2024-02-13 Dexerials Corporation Multilayer substrate
US10591529B2 (en) 2015-12-25 2020-03-17 Mitsubishi Aircraft Corporation Wiring safety evaluation system and wiring safety evaluation method

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