JPH05175247A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05175247A JPH05175247A JP34538591A JP34538591A JPH05175247A JP H05175247 A JPH05175247 A JP H05175247A JP 34538591 A JP34538591 A JP 34538591A JP 34538591 A JP34538591 A JP 34538591A JP H05175247 A JPH05175247 A JP H05175247A
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- semiconductor substrate
- hole
- forming
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、例えばＧａＡｓを用い
た電力増幅用ＦＥＴ等の半導体装置の製造方法に関し、
特にビアホールと呼ばれる貫通孔に金属を充填した貫通
電極の形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a power amplification FET using GaAs,
In particular, the present invention relates to a method of forming a through electrode in which a through hole called a via hole is filled with metal.
【０００２】[0002]
【従来の技術】電力増幅用のＦＥＴ、特に熱伝導率が比
較的悪いＧａＡｓ等を用いたものでは、放熱効率の向上
及び高周波での寄生コンダクタンス等の低減のために、
ソースパッド等の接続用電極をビアホールに充填した金
属を介してヒートシンク等に接続することが行われてい
る。2. Description of the Related Art FETs for power amplification, particularly those using GaAs or the like having a relatively low thermal conductivity, are used to improve heat dissipation efficiency and reduce parasitic conductance at high frequencies.
Connection electrodes such as a source pad are connected to a heat sink or the like through a metal filling a via hole.
【０００３】図２は、このような従来のビアホール構造
の形成方法を示している。ＧａＡｓ基板２１の表面に、
ソース電極２２、ドレイン電極及びゲート電極が形成さ
れ、さらにソース電極２２に接続されるように接続用電
極としてソースパッド電極２３が形成される。このあ
と、ＧａＡｓ基板２１の裏面から選択エッチングが行わ
れてソースパッド電極２３に達するビアホール２４が形
成される（同図（ａ））。ビアホール２４内及びＧａＡ
ｓ基板２１の裏面にスパッタリングにより下地金属膜２
７が形成される。次いで、下地金属膜２７上に電気メッ
キが行われてビアホール２４内へ金属２８が充填される
（同図（ｂ））。チップに分割したのち、加熱してＡｕ
−Ｓｎ等の共晶ハンダでパッケージのヒートシンク部に
ダイボンディングされる。FIG. 2 shows a method of forming such a conventional via hole structure. On the surface of the GaAs substrate 21,
A source electrode 22, a drain electrode, and a gate electrode are formed, and a source pad electrode 23 is formed as a connection electrode so as to be connected to the source electrode 22. After that, selective etching is performed from the back surface of the GaAs substrate 21 to form a via hole 24 reaching the source pad electrode 23 (FIG. 9A). Inside the via hole 24 and GaA
The underlying metal film 2 is formed on the back surface of the substrate 21 by sputtering.
7 is formed. Next, electroplating is performed on the underlying metal film 27 to fill the via holes 24 with the metal 28 (FIG. 7B). After dividing into chips, heat and Au
Die-bonded to the heat sink of the package with eutectic solder such as Sn.
【０００４】[0004]
【発明が解決しようとする課題】従来は、基板裏面から
の選択エッチングによりソースパッド電極に達するビア
ホールを形成する際、ビアホール底部のソースパッド電
極との境界部に異常エッチングが進行して図２（ａ）中
に示すような逆テーパ部２５が生じ易い。このため、ス
パッタリングにより下地金属膜を形成したのち、電気メ
ッキによりビアホール内への金属充填を行ったとき、図
２（ｂ）中に示すような閉じた空洞２６が生じ、その後
のダイボンディングの加熱の際にその空洞２６が熱膨張
してソースパッド電極のビアホールに接する部分が脹れ
上ってしまう場合がある。そして、このような脹れ上り
部が生じると、外観不良、さらには電気的、熱的な不良
が生じ易いという問題があった。Conventionally, when a via hole reaching the source pad electrode is formed by selective etching from the back surface of the substrate, abnormal etching progresses at the boundary with the source pad electrode at the bottom of the via hole, as shown in FIG. The reverse taper portion 25 shown in (a) is likely to occur. Therefore, when a metal film is formed in the via hole by electroplating after forming a base metal film by sputtering, a closed cavity 26 as shown in FIG. At this time, the cavity 26 may be thermally expanded and the portion of the source pad electrode in contact with the via hole may be expanded. When such a swollen portion is generated, there is a problem that a defective appearance is likely to occur, and further an electrical or thermal defect is likely to occur.
【０００５】そこで、本発明は、ビアホール構造の形成
時に閉じた空洞の発生を防止し、その後の加熱時に金属
膜に膨れが生じることのない半導体装置の製造方法を提
供することを目的とする。Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor device which prevents the formation of closed cavities when forming a via hole structure and prevents the metal film from bulging during subsequent heating.
【０００６】[0006]
【課題を解決するための手段】本発明は上記課題を解決
するために、（ａ）半導体基板の一主面上に金属膜を形
成する工程、（ｂ）前記半導体基板を熱処理して前記金
属膜と合金化する工程、（ｃ）前記半導体基板を他の主
面から選択的にエッチングして前記金属膜が露出する貫
通孔を形成する工程、（ｄ）前記貫通孔内に金属を充填
する工程を有することを要旨とする。In order to solve the above problems, the present invention provides: (a) a step of forming a metal film on one main surface of a semiconductor substrate; (b) heat treating the semiconductor substrate to form the metal film. Alloying with a film, (c) selectively etching the semiconductor substrate from another main surface to form a through hole through which the metal film is exposed, (d) filling the through hole with a metal The point is to have a process.
【０００７】金属膜としては、Ｔｉ、Ａｕ、Ｐｔ等を用
いることが望ましい。It is desirable to use Ti, Au, Pt or the like for the metal film.
【０００８】選択的エッチングは、半導体基板のみをエ
ッチングし、金属膜はエッチングしない。The selective etching etches only the semiconductor substrate, not the metal film.
【０００９】半導体基板の一主面上には半導体装置を構
成する全ての電極が形成され、前記金属膜は、その中の
少なくとも１つの電極と接続される。All electrodes forming a semiconductor device are formed on one main surface of a semiconductor substrate, and the metal film is connected to at least one of the electrodes.
【００１０】[0010]
【作用】上記構成において、熱処理により金属膜と半導
体基板の界面における反応、或いは相互拡散により、そ
の界面部が合金化され、金属膜と半導体基板の付着力が
高められる。これにより、半導体基板の選択的エッチン
グで貫通孔を形成する際、金属膜と半導体基板との界面
部へのエッチング液の浸み込みや、この部分でのエッチ
ング速度が異常に速くなることがなくなり、逆テーパ部
の発生が抑えられる。したがって、貫通孔内には閉じた
空洞が生じることなく金属が充填され、その後のダイボ
ンディング工程等における加熱の際、金属膜に膨れの生
じることがなくなる。In the above structure, the heat treatment causes a reaction at the interface between the metal film and the semiconductor substrate, or mutual diffusion, so that the interface is alloyed and the adhesion between the metal film and the semiconductor substrate is enhanced. As a result, when the through hole is formed by the selective etching of the semiconductor substrate, the etching liquid does not soak into the interface between the metal film and the semiconductor substrate and the etching rate at this portion does not become abnormally high. The occurrence of reverse taper is suppressed. Therefore, the through hole is filled with metal without forming a closed cavity, and the metal film is prevented from bulging during heating in the subsequent die bonding process or the like.
【００１１】[0011]
【実施例】以下、本発明の実施例を図１を参照して説明
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.
【００１２】この実施例は、ＧａＡｓ基板を用いたＦＥ
Ｔの製造方法に適用されている。This embodiment is an FE using a GaAs substrate.
It is applied to the manufacturing method of T.
【００１３】なお、以下の説明において、（ａ）〜
（ｃ）の各項目記号は、図１の（ａ）〜（ｃ）のそれぞ
れに対応する。In the following description, (a)-
Each item symbol of (c) corresponds to each of (a) to (c) of FIG.
【００１４】（ａ）ＧａＡｓ基板１の表面上に、オーミ
ック接触するソース電極２、ドレイン電極３及びショッ
トキー接触するゲート電極４を形成する。ビアホール
（貫通孔）を形成する部分にＴｉからなる金属膜５を厚
さ４００nm程度に形成する。金属膜５とソース電極２を
接続するソースパッド電極６をそれらの電極の上に形成
する。次いで、３００〜４５０℃の温度で熱処理し、金
属膜５とＧａＡｓ基板１との界面部を合金化する。な
お、この合金化の熱処理の温度は、ソース電極２及びド
レイン電極３のオーミック電極（ＡｕＧｅ／Ｎｉ）形成
時の熱処理の温度とほぼ同じなので、両熱処理は同時に
行なってもよい。(A) On the surface of the GaAs substrate 1, a source electrode 2 and a drain electrode 3 which are in ohmic contact and a gate electrode 4 which is in Schottky contact are formed. A metal film 5 made of Ti is formed to a thickness of about 400 nm in a portion where a via hole (through hole) is formed. A source pad electrode 6 that connects the metal film 5 and the source electrode 2 is formed on these electrodes. Then, heat treatment is performed at a temperature of 300 to 450 ° C. to alloy the interface between the metal film 5 and the GaAs substrate 1. Since the temperature of the heat treatment for alloying is almost the same as the temperature of the heat treatment for forming the ohmic electrodes (AuGe / Ni) of the source electrode 2 and the drain electrode 3, both heat treatments may be performed simultaneously.
【００１５】（ｂ）周知の技術を用いて基板裏面を削
り、全体の厚さを所要厚さとした後、ＧａＡｓ基板１の
裏面に、ビアホール形成部のみに開口部を有するレジス
トマスクを形成し、Ｈ3 ＰＯ4 ＋Ｈ2 Ｏ2 系のエッチン
グ液を用いた選択エッチングによりＧａＡｓ基板１をエ
ッチングして金属膜５の下面が露出するビアホール７を
形成する。(B) The back surface of the substrate is ground by a well-known technique to make the entire thickness to a required thickness, and then a resist mask having an opening only in the via hole forming portion is formed on the back surface of the GaAs substrate 1. The GaAs substrate 1 is etched by selective etching using an H 3 PO 4 + H 2 O 2 system etching solution to form a via hole 7 in which the lower surface of the metal film 5 is exposed.
【００１６】（ｃ）ビアホール７内及びＧａＡｓ基板１
の裏面に、下地金属膜８としてＴｉ／Ａｕをスパッタリ
ングにより形成する。次いで、下地金属膜８上に電気メ
ッキを行なってビアホール７内に金属９を充填する。充
填用の金属９としてはＡｕが適している。このあと、個
々のチップに分割し、加熱してＡｕ−Ｓｎ等の共晶ハン
ダ１０でパッケージのヒートシンク部１１にダイボンデ
ィングする。(C) Inside via hole 7 and GaAs substrate 1
Ti / Au is formed as a base metal film 8 on the back surface of the substrate by sputtering. Then, the underlying metal film 8 is electroplated to fill the via holes 7 with the metal 9. Au is suitable as the metal 9 for filling. After that, it is divided into individual chips, heated, and die-bonded to the heat sink portion 11 of the package with the eutectic solder 10 such as Au—Sn.
【００１７】なお、金属膜５としては、Ｔｉの他にＰ
ｔ、Ａｕ等を用いることもできる。但し、ＡｕＧｅ合金
は用いることができない。これは、上述のエッチング液
は、ＧａＡｓとＡｕＧｅとの間に選択性がなく、ＧａＡ
ｓをエッチングすると、これと同時にＧｅ分もエッチン
グされてしまうからである。As the metal film 5, in addition to Ti, P
It is also possible to use t, Au, or the like. However, AuGe alloy cannot be used. This is because the above etching solution has no selectivity between GaAs and AuGe,
This is because when s is etched, Ge is also etched at the same time.
【００１８】上述したように、この実施例の半導体装置
の製造方法によれば、ＧａＡｓ基板１の表面上における
ビアホール形成部にＴｉからなる金属膜５を形成し、熱
処理によりその金属膜５と半導体基板１の界面部を合金
化して金属膜５とＧａＡｓ基板１の付着力を高めるよう
にしたため、ウェットエッチングでＧａＡｓ基板１を選
択的にエッチングしてビアホール７を形成する際、金属
膜５とＧａＡｓ基板１との界面部へのエッチング液の浸
み込みや、この部分でのエッチング速度が異常に速くな
ることがなくなり、逆テーパ部の発生を抑えることがで
きる。したがって、ビアホール７内には、閉じた空洞を
生じさせることなく金属９を充填することができ、その
後のダイボンディング工程における加熱の際、ソースパ
ッド電極６におけるビアホール７に接する部分に膨れの
生じることがなくなる。As described above, according to the semiconductor device manufacturing method of this embodiment, the metal film 5 made of Ti is formed in the via hole forming portion on the surface of the GaAs substrate 1, and the metal film 5 and the semiconductor are heat-treated. Since the interface portion of the substrate 1 is alloyed to increase the adhesion between the metal film 5 and the GaAs substrate 1, the metal film 5 and the GaAs substrate 1 are selectively etched by wet etching to form the via hole 7. It is possible to prevent the etching solution from penetrating into the interface with the substrate 1 and to prevent the etching rate at this portion from becoming abnormally high, and to suppress the occurrence of the inverse taper portion. Therefore, the via hole 7 can be filled with the metal 9 without forming a closed cavity, and swelling occurs in the portion of the source pad electrode 6 in contact with the via hole 7 during heating in the subsequent die bonding process. Disappears.
【００１９】[0019]
【発明の効果】以上説明したように、本発明によれば、
半導体基板の一主面上における貫通孔の形成部に金属膜
を形成し、熱処理により金属膜と半導体基板とを合金化
するようにしたため、金属膜と半導体基板の付着力が高
められ、半導体基板の選択的エッチングで貫通孔を形成
する際、金属膜と半導体基板との界面部へのエッチング
液の浸み込みや、この部分でのエッチング速度が異常に
速くなることがなくなって、逆テーパ部の発生を抑える
ことができる。したがって、貫通孔内には閉じた空洞が
生じることなく金属を充填することができ、その後のダ
イボンディング工程等における加熱の際、金属膜に膨れ
の生じることがなくなるという利点がある。As described above, according to the present invention,
Since the metal film is formed in the portion where the through hole is formed on the one main surface of the semiconductor substrate and the metal film and the semiconductor substrate are alloyed by heat treatment, the adhesive force between the metal film and the semiconductor substrate is increased, and the semiconductor substrate When the through holes are formed by selective etching of the reverse taper portion, the etching solution does not soak into the interface between the metal film and the semiconductor substrate, and the etching rate at this portion does not become abnormally high. Can be suppressed. Therefore, there is an advantage that the metal can be filled without forming a closed cavity in the through hole, and the metal film is prevented from bulging during heating in the subsequent die bonding process or the like.
【図１】本発明に係る半導体装置の製造方法の実施例を
説明するための工程図である。FIG. 1 is a process chart for explaining an embodiment of a method for manufacturing a semiconductor device according to the present invention.
【図２】従来のビアホール構造の形成方法を示す工程図
である。FIG. 2 is a process drawing showing a conventional method for forming a via hole structure.
１ ＧａＡｓ基板（半導体基板） ２ ソース電極 ５ 金属膜 ６ ソースパッド電極 ７ ビアホール（貫通孔） ８ 下地金属膜 ９ 金属 1 GaAs substrate (semiconductor substrate) 2 source electrode 5 metal film 6 source pad electrode 7 via hole (through hole) 8 underlying metal film 9 metal
Claims (1)
形成する工程、 （ｂ）前記半導体基板を熱処理して前記金属膜と合金化
する工程、 （ｃ）前記半導体基板を他の主面から選択的にエッチン
グして前記金属膜が露出する貫通孔を形成する工程、 （ｄ）前記貫通孔内に金属を充填する工程 を有することを特徴とする半導体装置の製造方法。1. (a) a step of forming a metal film on one main surface of a semiconductor substrate, (b) a step of heat-treating the semiconductor substrate to alloy it with the metal film, (c) another semiconductor substrate A method for manufacturing a semiconductor device, comprising: a step of selectively etching from the main surface of the above step to form a through hole through which the metal film is exposed; and (d) a step of filling the through hole with a metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34538591A JPH05175247A (en) | 1991-12-26 | 1991-12-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34538591A JPH05175247A (en) | 1991-12-26 | 1991-12-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05175247A true JPH05175247A (en) | 1993-07-13 |
Family
ID=18376244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34538591A Pending JPH05175247A (en) | 1991-12-26 | 1991-12-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05175247A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6900482B2 (en) | 2001-03-30 | 2005-05-31 | Fujitsu Quantum Devices Limited | Semiconductor device having divided active regions with comb-teeth electrodes thereon |
| WO2007061059A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Sensor device and method for manufacturing same |
| WO2007061054A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Wafer level package structure and sensor device obtained from such package structure |
| US7288486B2 (en) | 2005-12-01 | 2007-10-30 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device having via holes |
| US8026594B2 (en) | 2005-11-25 | 2011-09-27 | Panasonic Electric Works Co., Ltd. | Sensor device and production method therefor |
| US8080869B2 (en) | 2005-11-25 | 2011-12-20 | Panasonic Electric Works Co., Ltd. | Wafer level package structure and production method therefor |
| JP2013004572A (en) * | 2011-06-13 | 2013-01-07 | Mitsubishi Electric Corp | Semiconductor device manufacturing method |
| WO2020110299A1 (en) * | 2018-11-30 | 2020-06-04 | 三菱電機株式会社 | Semiconductor device |
-
1991
- 1991-12-26 JP JP34538591A patent/JPH05175247A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6900482B2 (en) | 2001-03-30 | 2005-05-31 | Fujitsu Quantum Devices Limited | Semiconductor device having divided active regions with comb-teeth electrodes thereon |
| WO2007061059A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Sensor device and method for manufacturing same |
| WO2007061054A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Wafer level package structure and sensor device obtained from such package structure |
| WO2007061062A1 (en) * | 2005-11-25 | 2007-05-31 | Matsushita Electric Works, Ltd. | Method for manufacturing wafer level package structure |
| US7674638B2 (en) | 2005-11-25 | 2010-03-09 | Panasonic Electric Works Co., Ltd. | Sensor device and production method therefor |
| US8026594B2 (en) | 2005-11-25 | 2011-09-27 | Panasonic Electric Works Co., Ltd. | Sensor device and production method therefor |
| US8067769B2 (en) | 2005-11-25 | 2011-11-29 | Panasonic Electric Works Co., Ltd. | Wafer level package structure, and sensor device obtained from the same package structure |
| US8080869B2 (en) | 2005-11-25 | 2011-12-20 | Panasonic Electric Works Co., Ltd. | Wafer level package structure and production method therefor |
| US7288486B2 (en) | 2005-12-01 | 2007-10-30 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device having via holes |
| JP2013004572A (en) * | 2011-06-13 | 2013-01-07 | Mitsubishi Electric Corp | Semiconductor device manufacturing method |
| WO2020110299A1 (en) * | 2018-11-30 | 2020-06-04 | 三菱電機株式会社 | Semiconductor device |
| JPWO2020110299A1 (en) * | 2018-11-30 | 2021-02-15 | 三菱電機株式会社 | Semiconductor device |
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