JPH05175199A - Formation of bump electrode - Google Patents
Formation of bump electrodeInfo
- Publication number
- JPH05175199A JPH05175199A JP3344334A JP34433491A JPH05175199A JP H05175199 A JPH05175199 A JP H05175199A JP 3344334 A JP3344334 A JP 3344334A JP 34433491 A JP34433491 A JP 34433491A JP H05175199 A JPH05175199 A JP H05175199A
- Authority
- JP
- Japan
- Prior art keywords
- protruding electrode
- electrode
- bump electrode
- wiring board
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置及びその製造
方法関し、特にマイクロコンピュータや、ゲートアレー
等の多電極、狭ピッチのＬＳＩチップの実装に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to mounting a microcomputer, a multi-electrode such as a gate array, and a narrow pitch LSI chip.
【０００２】[0002]
【従来の技術】半導体装置の典型的な従来の技術を図３
とともに説明する。図３においてまず、図３ａに示すよ
うに、セラミック、ガラス等よりなる絶縁性の配線基板
１４の導体配線１５を有する面の半導体素子接続部位
に、絶縁性樹脂１６を塗布する。導体配線１５は、Ｃｒ
−Ａｕ，Ａｌ、ＩＴＯ等であり、絶縁樹脂１６は熱硬化
あるいは紫外線硬化のエポキシ、アクリル等である。つ
ぎに、図３ｂに示すように、Ａｕ等よりなり全てが金属
で構成された突起電極１８を有したＬＳＩチップ等の半
導体素子１７を、突起電極１８と導体配線１５が整合す
るように配線基板１４の絶縁樹脂１６が塗布された領域
に設置し、加圧ツール１９にて半導体素子１７を配線基
板１４に対して加圧する。このとき、半導体素子１７の
突起電極１８は金属であるため塑性変形し、絶縁樹脂１
６は周囲に押し出され、半導体素子１７の突起電極１８
は導体配線１５に接触する。つぎに、加圧ツール１９で
半導体素子１７を配線基板１４に対して加圧した状態
で、絶縁樹脂１６を硬化させ、その後図３ｃに示すよう
に、加圧ツール１９を除去する。このとき、半導体素子
１７は配線基板１４に絶縁樹脂１６により固着されると
ともに、半導体素子１７の塑性変形された突起電極１８
と導体配線１５は接触により電気的に接続される。2. Description of the Related Art A typical conventional technique of a semiconductor device is shown in FIG.
Will be explained together. In FIG. 3, first, as shown in FIG. 3A, an insulating resin 16 is applied to the semiconductor element connecting portion on the surface having the conductor wiring 15 of the insulating wiring board 14 made of ceramic, glass or the like. The conductor wiring 15 is Cr
-Au, Al, ITO, etc., and the insulating resin 16 is thermosetting or ultraviolet curing epoxy, acrylic, etc. Next, as shown in FIG. 3b, a semiconductor element 17 such as an LSI chip having a protruding electrode 18 made of Au or the like and entirely made of metal is attached to a wiring board so that the protruding electrode 18 and the conductor wiring 15 are aligned with each other. 14 is installed in the area where the insulating resin 16 is applied, and the semiconductor element 17 is pressed against the wiring board 14 by the pressing tool 19. At this time, since the protruding electrodes 18 of the semiconductor element 17 are made of metal, they are plastically deformed and the insulating resin 1
6 is extruded to the periphery, and the protruding electrode 18 of the semiconductor element 17 is
Contacts the conductor wiring 15. Next, the insulating resin 16 is cured while the semiconductor element 17 is pressed against the wiring board 14 by the pressing tool 19, and then the pressing tool 19 is removed as shown in FIG. 3C. At this time, the semiconductor element 17 is fixed to the wiring board 14 by the insulating resin 16, and the plastically deformed protruding electrode 18 of the semiconductor element 17 is provided.
And the conductor wiring 15 are electrically connected by contact.
【０００３】半導体素子への突起電極への形成方法は、
半導体ウェハーの段階で表面にバリアメタルを蒸着しフ
ォトレジストによりめっきマスクを形成し電解めっきに
より半導体ウェハーの電極上に選択的に金属層を形成し
行なうものであり、通常のＴＡＢ（ＴＡＰＥ ＡＵＴＯ
ＭＡＴＥＤ ＤＢＯＮＤＩＮＧ）方式の突起電極形成方
法と同様である。The method of forming the protruding electrodes on the semiconductor element is as follows.
A barrier metal is vapor-deposited on the surface of a semiconductor wafer, a plating mask is formed with a photoresist, and a metal layer is selectively formed on the electrodes of the semiconductor wafer by electrolytic plating, which is a normal TAB (TAPE AUTO).
This is the same as the method for forming the protruding electrodes of the MATED DBONDING method.
【０００４】[0004]
【発明が解決しようとする課題】前述した従来の技術で
は、半導体素子１７の突起電極１８を塑性変形させてい
るため、半導体素子１１を固着している絶縁樹脂１６が
熱膨張して突起電極１８と導体配線１５との間に隙間が
生じて電気的な接続不良が生じ、耐熱性の低いものであ
る。また、金属性の突起電極１８の変形を極力小さくし
て弾性変形にとどめておき、絶縁成樹脂１６の熱膨張に
突起電極１８の変形を追従させる方法もあるが、変形量
が非常に小さいため、突起電極１８の高さのばらつき
や、配線基板１４の平面度の影響により接続歩留りが非
常に低いものである。In the prior art described above, since the protruding electrode 18 of the semiconductor element 17 is plastically deformed, the insulating resin 16 fixing the semiconductor element 11 is thermally expanded and the protruding electrode 18 is fixed. The gap between the conductor wiring 15 and the conductor wiring 15 causes a poor electrical connection, resulting in low heat resistance. There is also a method in which the deformation of the metallic protruding electrode 18 is made as small as possible and is limited to elastic deformation, and the deformation of the protruding electrode 18 is made to follow the thermal expansion of the insulating resin 16, but the amount of deformation is very small. The connection yield is very low due to the variation in the height of the bump electrodes 18 and the flatness of the wiring board 14.
【０００５】本発明は上記問題点に鑑み、絶縁性樹脂に
熱膨張が生じても突起電極が常に導体配線に接触し信頼
性の高い半導体装置を得るための突起電極を提供するも
のである。In view of the above problems, the present invention provides a protruding electrode for obtaining a highly reliable semiconductor device in which the protruding electrode is always in contact with the conductor wiring even if the insulating resin is thermally expanded.
【０００６】[0006]
【課題を解決するための手段】上記問題点を解決するた
めに本発明の突起電極形成方法は、配線が形成された半
導体ウェハーの表面に金属膜を形成する工程、前記配線
の一部にリング状の開口部を有した絶縁性皮膜を前記金
属膜上に形成する工程、前記金属膜を電極とし電解めっ
きにより前記開口部に前記リング状の開口部内にある島
状の絶縁性皮膜の表面を覆うように金属突起を形成する
工程、前記金属突起の周囲にある前記絶縁性皮膜を除去
する工程、前記金属膜の不要部を除去する工程を備えた
ものである。In order to solve the above-mentioned problems, a method of forming a protruding electrode according to the present invention comprises a step of forming a metal film on the surface of a semiconductor wafer on which wiring is formed, and a ring on a part of the wiring. Forming an insulating coating having a ring-shaped opening on the metal film, the surface of the island-shaped insulating coating in the ring-shaped opening in the opening by electrolytic plating using the metal film as an electrode The method is provided with a step of forming a metal protrusion so as to cover, a step of removing the insulating film around the metal protrusion, and a step of removing an unnecessary portion of the metal film.
【０００７】[0007]
【作用】本発明は上記した構成によって、半導体素子の
突起電極が内部の中央部に弾性体の絶縁性皮膜よりなる
核を含んでいるため突起電極の弾性回復量を十分に大き
くすることができる。したがって、配線基板に絶縁性樹
脂を用いて半導体素子を固定して、半導体素子の突起電
極と配線基板の導体配線の電気的接続を得る場合におい
て、半導体素子を配線基板に対して加圧した状態で絶縁
性樹脂を硬化させることで、突起電極の中央部にある弾
性体の絶縁性皮膜よりなる核が弾性変形して突起電極が
配線基板の導体配線に弾性接触した状態になる。このた
め、仮に半導体素子固定用の絶縁性樹脂の寸法変化が生
じても突起電極の弾性復元により導体配線と突起電極は
常に接触した状態を保持するものである。According to the present invention, since the protruding electrode of the semiconductor element includes the core made of the insulating film of the elastic body in the center of the inside, the elastic recovery amount of the protruding electrode can be sufficiently increased. .. Therefore, when the semiconductor element is fixed to the wiring board by using an insulating resin and the protruding electrode of the semiconductor element and the conductor wiring of the wiring board are electrically connected, the semiconductor element is pressed against the wiring board. By curing the insulating resin with, the nucleus of the elastic insulating film in the central portion of the protruding electrode is elastically deformed and the protruding electrode is in elastic contact with the conductor wiring of the wiring board. For this reason, even if the dimensional change of the insulating resin for fixing the semiconductor element occurs, the conductor wiring and the protruding electrode are always kept in contact with each other due to the elastic restoration of the protruding electrode.
【０００８】[0008]
【実施例】以下本発明の一実施例の突起電極の製造方法
及びその突起電極を有したＬＳＩチップの実装方法につ
いて、図面を参照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a protruding electrode and a method of mounting an LSI chip having the protruding electrode according to an embodiment of the present invention will be described below with reference to the drawings.
【０００９】図１は本発明の実施例における突起電極の
製造方法の工程別断面図、図２は本発明の突起電極を有
したＬＳＩチップの実装方法の工程別断面図を示すもの
である。図１、図２においてにおいて、１は半導体ウェ
ハー、２は電極、３は保護膜、４はバリアメタル、５は
感光性樹脂、６は突起電極の核、７はリング状の開口
部、８は突起電極、９は回路基板、１０は導体配線、１
１は絶縁性樹脂、１２は加圧ツール、１３は紫外線を示
すものである。FIG. 1 is a sectional view of each step of a method of manufacturing a protruding electrode according to an embodiment of the present invention, and FIG. 2 is a sectional view of each step of a method of mounting an LSI chip having a protruding electrode of the present invention. In FIGS. 1 and 2, 1 is a semiconductor wafer, 2 is an electrode, 3 is a protective film, 4 is a barrier metal, 5 is a photosensitive resin, 6 is a core of a protruding electrode, 7 is a ring-shaped opening, and 8 is Projection electrodes, 9 is a circuit board, 10 is conductor wiring, 1
Reference numeral 1 is an insulating resin, 12 is a pressure tool, and 13 is ultraviolet light.
【００１０】まず図１を用いて突起電極の製造方法につ
いて説明する。まず始めに図１ａに示すように、電極２
及び保護膜３を有した半導体ウェハー１の表面に、バリ
アメタル４を形成する。バリアメタル４は電極２と後に
形成する突起電極の密着性を上げるために形成するもの
でその材料は、ＣｒーＣｕ，Ｔｉ−Ｐｄ−Ａｕ等の２層
から３層の金属膜で、厚みは０・３から１・０μｍ程度
であるある。バリアメタル４の形成は、真空蒸着やスパ
ッタリングなどを用いることにより容易に行なうことが
できる。次に図１ｂに示すように、バリアメタル４上に
感光性樹脂５をスピンナー等を用いて塗布する。感光性
樹脂５はいわゆるポジ型、ネガ型のフォトレジストや、
シリコーン、エポキシ、ポリイミド等の感光性樹脂を用
いる。感光性樹脂５の厚みは２から３０μｍ程度であ
る。次にフォトマスクを介して感光性樹脂５に選択的に
光を照射し、現像することにより、電極２上にリング状
の開口部７及び突起電極の核６を形成する。リング状の
開口部７の寸法は１０μｍΦから５０μｍΦ、突起電極
の核６の寸法は３μｍΦから４０μｍΦ程度である。リ
ング状の開口部７と突起電極の核６の寸法関係は例えば
リング状の開口部７の寸法が３０μｍのとき突起電極の
核６の寸法は５から１０μｍ程度である。次に図１ｃに
示すようにバリアメタル４を電極にし、感光性樹脂５を
マスクとし電解めっきを施しリング状の開口部７に突起
電極の核６を覆うように金属層を成長させ突起電極８を
形成する。突起電極８の材質はＡｕ、Ｃｕ、Ｎｉ等であ
る。突起電極の核６を覆うように金属層が形成できるの
は感光性樹脂５の表面まで金属層を成長させ引き続きめ
っきを施すことにより金属層は横方向にも成長する事に
よる。次に図１ｄに示すように感光性樹脂５をレジスト
ストリッパーや発煙硝酸等を用いて除去する。その後図
１ｄにし示す様にフォトリソ技術及び、エッチング技術
を用いて不要部のバリアメタル４を除去し突起電極８を
電気的に分離する。以上の様に、本発明によれば従来の
突起電極の形成方法を、そのまま用いめっきマスクとな
る感光性樹脂５のパターンニング時の形状をフォトマス
クにより変更するだけで、容易に弾性体よりなる突起電
極の核６を有した突起電極８を形成することができる。First, a method of manufacturing the bump electrode will be described with reference to FIG. First of all, as shown in FIG.
A barrier metal 4 is formed on the surface of the semiconductor wafer 1 having the protective film 3. The barrier metal 4 is formed in order to improve the adhesion between the electrode 2 and the projection electrode to be formed later, and the material thereof is a two- to three-layer metal film of Cr-Cu, Ti-Pd-Au, etc. It is about 0.3 to 1.0 μm. The barrier metal 4 can be easily formed by using vacuum deposition or sputtering. Next, as shown in FIG. 1b, a photosensitive resin 5 is applied onto the barrier metal 4 using a spinner or the like. The photosensitive resin 5 is a so-called positive type or negative type photoresist,
A photosensitive resin such as silicone, epoxy, or polyimide is used. The thickness of the photosensitive resin 5 is about 2 to 30 μm. Next, the photosensitive resin 5 is selectively irradiated with light through a photomask and developed to form a ring-shaped opening 7 and a protruding electrode nucleus 6 on the electrode 2. The size of the ring-shaped opening 7 is 10 μmΦ to 50 μmΦ, and the size of the core 6 of the protruding electrode is about 3 μmΦ to 40 μmΦ. The dimensional relationship between the ring-shaped opening 7 and the core 6 of the protruding electrode is, for example, about 5 to 10 μm when the size of the ring-shaped opening 7 is 30 μm. Next, as shown in FIG. 1c, the barrier metal 4 is used as an electrode, the photosensitive resin 5 is used as a mask, and electrolytic plating is performed to grow a metal layer in the ring-shaped opening 7 so as to cover the nucleus 6 of the bump electrode. To form. The material of the bump electrode 8 is Au, Cu, Ni or the like. The reason why the metal layer can be formed so as to cover the core 6 of the bump electrode is that the metal layer grows in the lateral direction by growing the metal layer up to the surface of the photosensitive resin 5 and then performing plating. Next, as shown in FIG. 1d, the photosensitive resin 5 is removed using a resist stripper, fuming nitric acid or the like. Thereafter, as shown in FIG. 1d, the barrier metal 4 in the unnecessary portion is removed by using the photolithography technique and the etching technique, and the protruding electrode 8 is electrically separated. As described above, according to the present invention, the conventional method for forming the protruding electrode is used as it is, and the shape of the photosensitive resin 5 serving as the plating mask during patterning is changed by the photomask to easily form the elastic body. The protruding electrode 8 having the core 6 of the protruding electrode can be formed.
【００１１】なお以上のようにして突起電極８が形成さ
れた半導体ウェハー１を各区画毎に切断して分離する
と、それぞれＬＳＩチップなどのの半導体素子となりこ
れが後に配線基板に搭載される。When the semiconductor wafer 1 on which the protruding electrodes 8 are formed is cut and separated into each section as described above, each becomes a semiconductor element such as an LSI chip, which is later mounted on a wiring board.
【００１２】次に図２を用い、前述した突起電極８を有
したＬＳＩチップの配線基板への接続方法について説明
する。Next, a method of connecting the above-mentioned LSI chip having the protruding electrode 8 to the wiring board will be described with reference to FIG.
【００１３】まず図２ａに示すように、ガラス、セラミ
ック等よりなり、導体配線１０を有した絶縁性の配線基
板９の後にＬＳＩチップを搭載する領域に絶縁性樹脂１
１を塗布する。配線基板９の厚みは、０・１から２・０
ｍｍ程度である。導体配線１０は、Ｃｒ−Ａｕ，Ａｌ、
ＩＴＯ等であり、その厚みは０・１から１０μｍ程度で
ある。絶縁性樹脂１１は例えばアクリル、エポキシ等の
光硬化型であり、塗布はディスペンサ、印刷等を用い
る。First, as shown in FIG. 2A, an insulating resin 1 is formed in a region where an LSI chip is mounted after an insulating wiring board 9 made of glass, ceramics or the like and having a conductor wiring 10.
Apply 1. The thickness of the wiring board 9 is from 0.1 to 2.0
It is about mm. The conductor wiring 10 is made of Cr-Au, Al,
It is ITO or the like and its thickness is about 0.1 to 10 μm. The insulating resin 11 is, for example, a photocurable type such as acrylic or epoxy, and is applied by using a dispenser, printing, or the like.
【００１４】次に、図２ｂに示すように、前述した弾性
体よりなる突起電極の核６を有した突起電極８を有した
ＬＳＩチップ１２を突起電極８と導体配線１０が整合す
るように配線基板９の絶縁性樹脂１１が塗布された領域
に設置する。突起電極８の厚みは５μｍから４０μｍ程
度であり、その寸法は１５μｍΦから５０μｍΦ程度で
ある。ついで、突起電極８が弾性変形状態になるよう
に、加圧ツール１３にてＬＳＩチップ１２を配線基板９
に対して加圧する。加圧力は、０．５ｇ／突起電極〜５
ｇ／突起電極程度である。このとき、絶縁性樹脂１１は
周囲に押し出され、ＬＳＩチップ１２の突起電極８と導
体配線１０は電気的に弾性接触する。Next, as shown in FIG. 2b, the LSI chip 12 having the protruding electrode 8 having the core 6 of the protruding electrode made of the elastic body is wired so that the protruding electrode 8 and the conductor wiring 10 are aligned with each other. It is installed in a region of the substrate 9 coated with the insulating resin 11. The thickness of the protruding electrode 8 is about 5 μm to 40 μm, and the dimension thereof is about 15 μmΦ to 50 μmΦ. Then, the LSI chip 12 is mounted on the wiring board 9 by the pressing tool 13 so that the protruding electrode 8 is elastically deformed.
Pressurize against. Applied pressure is 0.5g / projection electrode ~ 5
g / protruded electrode. At this time, the insulating resin 11 is pushed out to the periphery, and the protruding electrode 8 of the LSI chip 12 and the conductor wiring 10 electrically elastically contact each other.
【００１５】このとき、突起電極８は、ゴム状の弾性体
である突起電極の核６を有しているため、小さい加圧力
で安易に変形し、その弾性変形量が大きく、突起電極８
の厚みのばらつきや、配線基板９の平面度を吸収し、Ｌ
ＳＩチップ１２の全ての突起電極８を導体配線１０に容
易にかつ確実に接触させることができるつぎに、ＬＳＩ
チップ１２を加圧した状態で、絶縁性樹脂１１を硬化さ
せる。硬化の方法は、例えば配線基板９がガラス等の透
明基板の場合は、配線基板９の裏面より紫外線１４を照
射する。また、セラミック等の不透明基板の場合は、Ｌ
ＳＩチップ１２の側面より紫外線を照射する。At this time, since the projecting electrode 8 has the core 6 of the projecting electrode which is a rubber-like elastic body, the projecting electrode 8 is easily deformed by a small pressing force, and the elastic deformation amount is large.
Of the thickness of the wiring board and the flatness of the wiring board 9
All the protruding electrodes 8 of the SI chip 12 can be brought into contact with the conductor wiring 10 easily and reliably.
The insulating resin 11 is cured while the chip 12 is pressed. The curing method is, for example, when the wiring substrate 9 is a transparent substrate such as glass, the back surface of the wiring substrate 9 is irradiated with the ultraviolet rays 14. In the case of an opaque substrate such as ceramic, L
Ultraviolet rays are irradiated from the side surface of the SI chip 12.
【００１６】つぎに、図２ｃに示すように、加圧ツール
１３による加圧を解除する。このとき、ＬＳＩチップ１
２は配線基板９に固着されると同時に、突起電極８と導
体配線１０とは接触により電気的に接続され、その状態
が保持される。Next, as shown in FIG. 2c, the pressure applied by the pressure tool 13 is released. At this time, the LSI chip 1
2 is fixed to the wiring board 9, and at the same time, the protruding electrode 8 and the conductor wiring 10 are electrically connected by contact, and the state is maintained.
【００１７】[0017]
【発明の効果】本発明では中央部部に弾性対よりなる核
を有した突起電極の製造方法として電解めっきに用いる
めっきマスクの材料をそのまま用い、また形成方法もめ
っきマスクのパターンニング時に同時に行なうことがで
きるため非常に簡単に核を有した突起電極を形成するこ
とができ低コストなものである。According to the present invention, the material of the plating mask used for electrolytic plating is used as it is as a method of manufacturing a protruding electrode having a nucleus composed of an elastic pair in the central portion, and the forming method is performed simultaneously with the patterning of the plating mask. Therefore, it is possible to form a protruding electrode having a nucleus very easily and at low cost.
【００１８】また本発明による突起電極を有したＬＳＩ
チップの配線基板への接続においては、ＬＳＩチップの
突起電極が弾性を有する絶縁体からなる突起電極核を有
しており、突起電極が弾性変形状態で配線基板の導体配
線に接触しているため、つぎに示す効果がある。An LSI having a protruding electrode according to the present invention
When connecting the chip to the wiring board, the protruding electrode of the LSI chip has a protruding electrode core made of an elastic insulator, and the protruding electrode contacts the conductor wiring of the wiring board in an elastically deformed state. , And has the following effects.
【００１９】１ ＬＳＩチップを配線基板に接続した後
に、ＬＳＩチップの固着に用いた絶縁性樹脂が熱膨張し
ても、突起電極は容易に弾性復元し、突起電極と配線基
板の導体配線は常に接触した状態を保ち、耐熱性が高
く、信頼性が高い。1 After connecting the LSI chip to the wiring board, even if the insulating resin used for fixing the LSI chip is thermally expanded, the protruding electrode easily elastically restores, and the protruding electrode and the conductor wiring of the wiring board are always Maintains contact, high heat resistance, and high reliability.
【００２０】２ 突起電極の変形量を大きくしても、弾
性変形状態を保つことができるため、突起電極の厚みの
ばらつきが大きい場合や、配線基板の平面度が無い場合
でも、歩留まりよく接続することができる。2 Since the elastic deformation state can be maintained even when the deformation amount of the protruding electrode is increased, the connection can be made with a good yield even when the thickness of the protruding electrode varies greatly or the wiring board has no flatness. be able to.
【００２１】３ 非常に小さい加圧力で、接続を行なう
ことができるため、ＬＳＩチップの加圧時におけるＬＳ
Ｉチップのそりや歪の発生がなく、ＬＳＩの特性変動が
なく高品質の半導体装置を得ることができる。3 Since the connection can be made with a very small pressing force, the LS when the LSI chip is pressed
It is possible to obtain a high-quality semiconductor device without warpage or distortion of the I-chip and without fluctuation of the LSI characteristics.
【図１】本発明の第１の実施例における突起電極の形成
方法の工程順断面図FIG. 1 is a sectional view in order of steps of a method for forming a protruding electrode according to a first embodiment of the present invention.
【図２】図１の突起電極を有したＬＳＩチップの配線基
板への接続方法の１例を示す工程別断面図2A to 2C are cross-sectional views for each step showing an example of a method of connecting an LSI chip having a protruding electrode of FIG. 1 to a wiring board.
【図３】従来の突起電極を有したＬＳＩチップの基板へ
の接続方法を示す工程別断面図FIG. 3 is a cross-sectional view for each step showing a conventional method for connecting an LSI chip having protruding electrodes to a substrate.
１ 半導体ウェハー ２ 電極 ３ 保護膜 ４ バリアメタル ５ 感光性樹脂 ６ 突起電極の核 ７ リング状の開口部 ８ 突起電極 ９ 配線基板 １０ 導体配線 １１ 絶縁性樹脂 １２ ＬＳＩチップ １３ 加圧ツール 1 Semiconductor Wafer 2 Electrode 3 Protective Film 4 Barrier Metal 5 Photosensitive Resin 6 Core of Projection Electrode 7 Ring-shaped Opening 8 Projection Electrode 9 Wiring Board 10 Conductor Wiring 11 Insulating Resin 12 LSI Chip 13 Pressing Tool
Claims (2)
金属膜を形成する工程、前記配線の一部にリング状の開
口部を有した絶縁性皮膜を前記金属膜上に形成する工
程、前記金属膜を電極とし電解めっきにより前記開口部
に前記リング状の開口部内にある島状の絶縁性皮膜の表
面を覆うように金属突起を形成する工程、前記金属突起
の周囲にある前記絶縁性皮膜を除去する工程、前記金属
膜の不要部を除去する工程よりなることを特徴とする突
起電極の形成方法。1. A step of forming a metal film on a surface of a semiconductor wafer on which wiring is formed, a step of forming an insulating film having a ring-shaped opening on a part of the wiring on the metal film, A step of forming a metal projection in the opening so as to cover the surface of the island-shaped insulating film in the ring-shaped opening by electrolytic plating using the metal film as an electrode, the insulating film around the metal projection And a step of removing an unnecessary portion of the metal film.
る請求項１記載の突起電極の形成方法。2. The method of forming a protruding electrode according to claim 1, wherein the insulating film is an elastic body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3344334A JP3003344B2 (en) | 1991-12-26 | 1991-12-26 | Method of forming bump electrodes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3344334A JP3003344B2 (en) | 1991-12-26 | 1991-12-26 | Method of forming bump electrodes |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05175199A true JPH05175199A (en) | 1993-07-13 |
| JP3003344B2 JP3003344B2 (en) | 2000-01-24 |
Family
ID=18368441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3344334A Expired - Fee Related JP3003344B2 (en) | 1991-12-26 | 1991-12-26 | Method of forming bump electrodes |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3003344B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10017746A1 (en) * | 2000-04-10 | 2001-10-18 | Infineon Technologies Ag | Electronic component with microscopic contact surfaces and process for its manufacture |
| US6555849B1 (en) | 1998-05-12 | 2003-04-29 | Infineon Technologies Ag | Deactivatable thyristor |
-
1991
- 1991-12-26 JP JP3344334A patent/JP3003344B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6555849B1 (en) | 1998-05-12 | 2003-04-29 | Infineon Technologies Ag | Deactivatable thyristor |
| DE10017746A1 (en) * | 2000-04-10 | 2001-10-18 | Infineon Technologies Ag | Electronic component with microscopic contact surfaces and process for its manufacture |
| US6946725B2 (en) | 2000-04-10 | 2005-09-20 | Infineon Technologies Ag | Electronic device having microscopically small contact areas and methods for producing the electronic device |
| DE10017746B4 (en) * | 2000-04-10 | 2005-10-13 | Infineon Technologies Ag | Method for producing an electronic component with microscopically small contact surfaces |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3003344B2 (en) | 2000-01-24 |
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