JPH05173179A - Active matrix substrate - Google Patents
Active matrix substrateInfo
- Publication number
- JPH05173179A JPH05173179A JP34301391A JP34301391A JPH05173179A JP H05173179 A JPH05173179 A JP H05173179A JP 34301391 A JP34301391 A JP 34301391A JP 34301391 A JP34301391 A JP 34301391A JP H05173179 A JPH05173179 A JP H05173179A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- active matrix
- gate electrode
- peripheral circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はアクティブマトリクス基
板に関し、例えばアクティブマトリクス型液晶表示装置
に用いられる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate and is used, for example, in an active matrix type liquid crystal display device.
【０００２】[0002]
【従来の技術】アクティブマトリクス型液晶表示装置と
して、基板上に周辺回路部を内蔵したものが知られてい
る。ここで、周辺回路部にはアクティブマトリクス基板
の走査線（ゲート線）に駆動信号を供給する駆動（ドラ
イバ）回路と、データ線（ソース線）に表示信号を供給
する表示データ出力回路とが含まれる。2. Description of the Related Art As an active matrix type liquid crystal display device, a device in which a peripheral circuit portion is built in on a substrate is known. Here, the peripheral circuit portion includes a drive (driver) circuit that supplies a drive signal to a scanning line (gate line) of the active matrix substrate and a display data output circuit that supplies a display signal to a data line (source line). Be done.
【０００３】ところで画素部にスイッチとして用いられ
る薄膜トランジスタには、オフ電流の小さいことが要求
されるため、オフセット構造（ゲート電極とリース、ド
レイン領域が非整合である構造）あるいはＬＤＤ構造の
薄膜トランジスタをアクティブマトリクス型液晶表示装
置に用いることが検討されている。Since a thin film transistor used as a switch in a pixel portion is required to have a small off current, a thin film transistor having an offset structure (a structure in which a gate electrode and a lease are not aligned with a drain region) or an LDD structure is active. It is being studied for use in a matrix type liquid crystal display device.
【０００４】[0004]
【発明が解決しようとする課題】しかし、オフセット構
造あるいはＬＤＤ構造の薄膜トランジスタを画素部だけ
でなく周辺回路部にも用いると、オフ電流は低下するも
ののオン電流も低下してしまうため、内蔵のドライバ回
路の性能を十分にすることができない。そこで本発明
は、画素部と周辺回路部のそれぞれにおいて、薄膜トラ
ンジスタに要求される仕様を十分に満足させることので
きるアクティブマトリクス基板を提供することを目的と
する。However, when the thin film transistor having the offset structure or the LDD structure is used not only in the pixel portion but also in the peripheral circuit portion, the off current decreases but the on current also decreases. Therefore, the built-in driver is used. The circuit performance cannot be sufficient. Therefore, an object of the present invention is to provide an active matrix substrate capable of sufficiently satisfying the specifications required for a thin film transistor in each of the pixel portion and the peripheral circuit portion.
【０００５】[0005]
【課題を解決するための手段】本発明に係るアクティブ
マトリクス基板は、基板上に、スイッチとしての薄膜ト
ランジスタを含む画素部と、薄膜トランジスタを含んで
構成された周辺回路部とが形成された基板において、画
素部の薄膜トランジスタはオフセット構造またはＬＤＤ
構造とされ、周辺回路部の薄膜トランジスタはソースお
よびドレイン領域の端部とゲート電極の端部とが整合ま
たは重なり合う構造とされていることを特徴とする。An active matrix substrate according to the present invention is a substrate in which a pixel portion including a thin film transistor as a switch and a peripheral circuit portion including the thin film transistor are formed on the substrate. The thin film transistor of the pixel portion has an offset structure or LDD
The thin film transistor in the peripheral circuit portion has a structure in which the end portions of the source and drain regions and the end portions of the gate electrode are aligned or overlap with each other.
【０００６】ここで、周辺回路部と画素部の薄膜トラン
ジスタの有するゲート電極が同一材料で構成され、画素
部の薄膜トランジスタのゲート電極のみが陽極酸化され
ていてもよい。Here, the peripheral circuit section and the gate electrode of the thin film transistor in the pixel section may be made of the same material, and only the gate electrode of the thin film transistor in the pixel section may be anodized.
【０００７】[0007]
【作用】本発明の構成によれば、画素部の薄膜トランジ
スタはオフセット構造あるいはＬＤＤ構造とされるの
で、オフ電流の低減が可能であり、これに対して、周辺
回路部の薄膜トランジスタは通常の構造（ゲート電極と
ソース、ドレイン領域が整合または重なり合う構造）と
されるので、オン電流の低下を防止できる。According to the structure of the present invention, since the thin film transistor of the pixel portion has the offset structure or the LDD structure, it is possible to reduce the off current, while the thin film transistor of the peripheral circuit portion has the normal structure ( Since the gate electrode and the source / drain regions are aligned or overlapped with each other, it is possible to prevent a decrease in on-current.
【０００８】[0008]
【実施例】以下、添付図面により本発明の実施例を説明
する。Embodiments of the present invention will be described below with reference to the accompanying drawings.
【０００９】図１は実施例に係るアクティブマトリクス
基板の平面図である。図示の通り、ガラスあるいはセラ
ミックスなどの基板１上には、画素部２と周辺回路部３
１，３２が形成されている。画素部２には複数本の走査
線４が平行に配設され、スイッチ用の薄膜トランジスタ
のゲート電極（図示せず）に接続されると共に、ドライ
バとしての周辺回路部３１の出力に接続されている。ま
た、走査線４の他端は共通接続され、陽極酸化電圧Ｖが
印加される構造になっている。なお、表示データ出力回
路としての周辺回路部３２の入力には、走査線４と直交
するデータ線（図示せず）が接続されている。FIG. 1 is a plan view of an active matrix substrate according to an embodiment. As shown in the drawing, the pixel portion 2 and the peripheral circuit portion 3 are provided on the substrate 1 made of glass or ceramics.
1, 32 are formed. A plurality of scanning lines 4 are arranged in parallel in the pixel portion 2, connected to a gate electrode (not shown) of a thin film transistor for switching, and connected to an output of a peripheral circuit portion 31 as a driver. .. Further, the other ends of the scanning lines 4 are commonly connected, and have a structure to which an anodic oxidation voltage V is applied. A data line (not shown) orthogonal to the scanning line 4 is connected to the input of the peripheral circuit section 32 as the display data output circuit.
【００１０】上記の実施例において、周辺回路部３１，
３２の薄膜トランジスタは図２（ａ）のように構成され
る。すなわち、基板１上にポリシリコンなどの半導体薄
膜６が形成され、その上面にＳｉＯ2 などのゲート絶縁
膜７が形成され、チャネル領域６Ｃのゲート絶縁膜７上
にはタンタル、アルミニウム、ニオブ、ポリシリコンな
どのゲート電極８が形成されている。In the above embodiment, the peripheral circuit section 31,
The thin film transistor 32 is configured as shown in FIG. That is, a semiconductor thin film 6 of polysilicon or the like is formed on a substrate 1, a gate insulating film 7 of SiO 2 or the like is formed on the upper surface thereof, and tantalum, aluminum, niobium, or poly is formed on the gate insulating film 7 of the channel region 6C. A gate electrode 8 made of silicon or the like is formed.
【００１１】ここで、特徴的なことは、半導体薄膜６に
おけるｎ+ 型のソース領域６Ｓとドレイン領域６Ｄの端
部が、絶縁膜７をはさんでゲート電極８と位置的に整合
していることである。なお、端部で重なり合う構造とな
っていてもよい。このため、周辺回路部３１，３２にお
ける薄膜トランジスタは、オフ電流はそれほど小さくな
いものの、オン電流が大きくされている。Here, it is characteristic that the ends of the n + type source region 6S and the drain region 6D in the semiconductor thin film 6 are aligned with the gate electrode 8 with the insulating film 7 in between. That is. It should be noted that the structure may be such that the ends overlap. Therefore, the thin film transistors in the peripheral circuit portions 31 and 32 have a large on current, although the off current is not so small.
【００１２】一方、上記実施例において、画素部２の薄
膜トランジスタは図２（ｂ），（ｃ）のようになってい
る。すなわち、ｎ+ 型のソース領域６Ｓおよびドレイン
領域６Ｄの端部がゲート電極８から離れたオフセット構
造となり、あるいはソース領域６Ｓおよびドレイン領域
６Ｄとｉ型のチャネル領域６Ｃとの間に低ドープのｎ-
型ライトリドープド領域６Ｌが介在されてＬＤＤ構造と
なっている。このため、オン電流はそれほど大きくない
ものの、オフ電流は低く抑えられている。On the other hand, in the above embodiment, the thin film transistor of the pixel section 2 is as shown in FIGS. 2 (b) and 2 (c). That is, the ends of the n + -type source region 6S and the drain region 6D have an offset structure separated from the gate electrode 8, or the low-doped n-type region is provided between the source region 6S and the drain region 6D and the i-type channel region 6C. -
The LDD structure is formed by interposing the type light redoped region 6L. Therefore, the on-current is not so large, but the off-current is kept low.
【００１３】上記のようなオフセット構造あるいはＬＤ
Ｄ構造の薄膜トランジスタは、例えば図３〜図５のよう
にして形成される。図３（ａ）のように、タンタルなど
のゲート電極８をマスクとしてイオン注入し、ｉ型の半
導体薄膜６にｎ+ 型のソース領域６Ｓおよびドレイン領
域６Ｄを自己整合的に形成する。次に、ゲート電極８を
陽極酸化すると、酸化タンタル（Ｔａ2 Ｏ5 ）の絶縁膜
８１が形成され、ゲート電極８が細らされてオフセット
構造が実現される（図３（ｂ）図示）。Offset structure or LD as described above
The thin film transistor having the D structure is formed, for example, as shown in FIGS. As shown in FIG. 3A, ion implantation is performed using the gate electrode 8 of tantalum or the like as a mask to form the n + type source region 6S and the drain region 6D in the i type semiconductor thin film 6 in a self-aligned manner. Next, when the gate electrode 8 is anodized, an insulating film 81 of tantalum oxide (Ta 2 O 5 ) is formed, and the gate electrode 8 is thinned to realize an offset structure (FIG. 3B).
【００１４】図４（ａ）のように、絶縁膜７上にゲート
電極８を形成した後、同図（ｂ）のように陽極酸化で酸
化タンタル（Ｔａ2 Ｏ5 ）の絶縁膜８１を形成し、イオ
ン注入しても、同様にオフセット構造が得られる。After forming the gate electrode 8 on the insulating film 7 as shown in FIG. 4A, an insulating film 81 of tantalum oxide (Ta 2 O 5 ) is formed by anodic oxidation as shown in FIG. 4B. However, even if the ion implantation is performed, an offset structure can be similarly obtained.
【００１５】図５（ａ）のように、絶縁膜７上のゲート
電極８をマスクとして低濃度のイオン注入を行ない、ソ
ース領域６Ｓとドレイン領域６Ｄをｎ- 型とする。次
に、同図（ｂ）のように、ゲート電極８を陽極酸化し、
酸化タンタル（Ｔａ2 Ｏ5 ）の絶縁膜８１をマスクとし
て高濃度のイオン注入をすると、ｎ+ 型のソース領域６
Ｓおよびドレイン領域６Ｄとｉ型のソース領域６Ｓの間
に、ｎ- 型のライトリドープド領域６Ｌが介在されたＬ
ＤＤ構造が実現される。As shown in FIG. 5A, low concentration ion implantation is performed using the gate electrode 8 on the insulating film 7 as a mask to make the source region 6S and the drain region 6D n - type. Then, the gate electrode 8 is anodized as shown in FIG.
When high-concentration ion implantation is performed using the insulating film 81 of tantalum oxide (Ta 2 O 5 ) as a mask, the n + -type source region 6 is formed.
An L − type light re-doped region 6L is interposed between the S and drain regions 6D and the i type source region 6S.
The DD structure is realized.
【００１６】なお、実施例では陽極酸化によるオフセッ
ト構造およびＬＤＤ構造の形成を示したが、他の手法を
用いてもよい。例えば、画素部２の薄膜トランジスタに
ついてのみ、ゲート電極８の側壁にＳｉＯ2 を残してイ
オン注入し、あるいはゲートマスクを有するゲート電極
をサイドエッチングでアンダーカットしてからイオン注
入し、オフセット構造やＬＤＤ構造としてもよい。但
し、陽極酸化の膜厚は印加電圧で自由にコントロールで
きるので、制御性に優れている。Although the offset structure and the LDD structure are formed by anodic oxidation in the embodiments, other methods may be used. For example, only with respect to the thin film transistor of the pixel portion 2, ion implantation is performed while leaving SiO 2 on the side wall of the gate electrode 8, or the gate electrode having the gate mask is undercut by side etching and then ion implantation is performed, and an offset structure or an LDD structure is formed. May be However, since the thickness of the anodized film can be freely controlled by the applied voltage, the controllability is excellent.
【００１７】[0017]
【発明の効果】以上の通り、本発明のアクティブマトリ
クス基板では、画素部の薄膜トランジスタはオフセット
構造あるいはＬＤＤ構造とされるので、オフ電流の低減
が可能であり、これに対して、周辺回路部の薄膜トラン
ジスタは通常の構造（ゲート電極とソース、ドレイン領
域が整合または重なり合う構造）とされるので、オン電
流の低下を防止できる。このため、画素部の薄膜トラン
ジスタに要求される仕様と、周辺回路部の薄膜トランジ
スタに要求される仕様を同時に満足させることができ
る。As described above, in the active matrix substrate of the present invention, since the thin film transistor in the pixel portion has the offset structure or the LDD structure, it is possible to reduce the off current. Since the thin film transistor has a normal structure (a structure in which the gate electrode and the source / drain regions are aligned or overlapped with each other), a decrease in on-current can be prevented. Therefore, the specifications required for the thin film transistor of the pixel portion and the specifications required for the thin film transistor of the peripheral circuit portion can be satisfied at the same time.
【図１】実施例に係るアクティブマトリクス基板の平面
図である。FIG. 1 is a plan view of an active matrix substrate according to an example.
【図２】実施例に用いる薄膜トランジスタの断面図であ
る。FIG. 2 is a cross-sectional view of a thin film transistor used in an example.
【図３】オフセット構造の薄膜トランジスタの製法の一
例を示す図である。FIG. 3 is a diagram showing an example of a method of manufacturing a thin film transistor having an offset structure.
【図４】オフセット構造の薄膜トランジスタの製法の他
の例を示す図である。FIG. 4 is a diagram showing another example of a method of manufacturing a thin film transistor having an offset structure.
【図５】ＬＤＤ構造の薄膜トランジスタの製法の一例を
示す図である。FIG. 5 is a diagram showing an example of a method of manufacturing a thin film transistor having an LDD structure.
１…基板、２…画素部、３１，３２…周辺回路部、６…
半導体薄膜、６Ｃ…チャネル領域、６Ｓ…ソース領域、
６Ｄ…ドレイン領域、７…絶縁膜、８…ゲート電極、８
１…酸化タンタル（Ｔａ2 Ｏ5 ）の絶縁膜1 ... Substrate, 2 ... Pixel part, 31, 32 ... Peripheral circuit part, 6 ...
Semiconductor thin film, 6C ... Channel region, 6S ... Source region,
6D ... Drain region, 7 ... Insulating film, 8 ... Gate electrode, 8
1. Tantalum oxide (Ta 2 O 5 ) insulating film
Claims (2)
ジスタを含む画素部と、薄膜トランジスタを含んで構成
された周辺回路部とが形成されたアクティブマトリクス
基板において、 前記画素部の薄膜トランジスタはオフセット構造または
ＬＤＤ構造とされ、前記周辺回路部の薄膜トランジスタ
はソースおよびドレイン領域の端部とゲート電極の端部
とが整合または重なり合う構造とされていることを特徴
とするアクティブマトリクス基板。1. An active matrix substrate in which a pixel portion including a thin film transistor as a switch and a peripheral circuit portion including the thin film transistor are formed on a substrate, wherein the thin film transistor in the pixel portion has an offset structure or an LDD structure. The active matrix substrate is characterized in that the thin film transistor of the peripheral circuit portion has a structure in which the ends of the source and drain regions and the ends of the gate electrode are aligned or overlapped with each other.
ンジスタの有するゲート電極が同一材料で構成され、前
記画素部の薄膜トランジスタのゲート電極のみが陽極酸
化されている請求項１記載のアクティブマトリクス基
板。2. The active matrix substrate according to claim 1, wherein the peripheral circuit section and the gate electrode of the thin film transistor of the pixel section are made of the same material, and only the gate electrode of the thin film transistor of the pixel section is anodized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34301391A JP3072637B2 (en) | 1991-12-25 | 1991-12-25 | Active matrix substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34301391A JP3072637B2 (en) | 1991-12-25 | 1991-12-25 | Active matrix substrate |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35306399A Division JP3312617B2 (en) | 1991-12-25 | 1999-12-13 | Active matrix substrate manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05173179A true JPH05173179A (en) | 1993-07-13 |
| JP3072637B2 JP3072637B2 (en) | 2000-07-31 |
Family
ID=18358266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34301391A Expired - Lifetime JP3072637B2 (en) | 1991-12-25 | 1991-12-25 | Active matrix substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3072637B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0635890A1 (en) * | 1993-02-10 | 1995-01-25 | Seiko Epson Corporation | Active matrix substrate and thin film transistor, and method of its manufacture |
| JPH07111334A (en) * | 1993-08-20 | 1995-04-25 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
| EP0652595A2 (en) * | 1993-11-05 | 1995-05-10 | Sony Corporation | Thin film semiconductor device for display and method of producing same |
| US5962897A (en) * | 1992-06-18 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6180957B1 (en) | 1993-07-26 | 2001-01-30 | Seiko Epson Corporation | Thin-film semiconductor device, and display system using the same |
| US6417057B1 (en) | 1994-06-14 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming a semiconductor device having a TFT utilizing optical annealing before a gate electrode is formed |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6777763B1 (en) | 1993-10-01 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6862011B2 (en) | 1996-09-26 | 2005-03-01 | Seiko Epson Corporation | Display apparatus |
-
1991
- 1991-12-25 JP JP34301391A patent/JP3072637B2/en not_active Expired - Lifetime
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5962897A (en) * | 1992-06-18 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6455875B2 (en) | 1992-10-09 | 2002-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having enhanced field mobility |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| EP0635890A4 (en) * | 1993-02-10 | 1995-12-13 | Seiko Epson Corp | Active matrix substrate and thin film transistor, and method of its manufacture. |
| US5563427A (en) * | 1993-02-10 | 1996-10-08 | Seiko Epson Corporation | Active matrix panel and manufacturing method including TFTs having variable impurity concentration levels |
| EP0635890A1 (en) * | 1993-02-10 | 1995-01-25 | Seiko Epson Corporation | Active matrix substrate and thin film transistor, and method of its manufacture |
| US6808965B1 (en) | 1993-07-26 | 2004-10-26 | Seiko Epson Corporation | Methodology for fabricating a thin film transistor, including an LDD region, from amorphous semiconductor film deposited at 530° C. or less using low pressure chemical vapor deposition |
| US6180957B1 (en) | 1993-07-26 | 2001-01-30 | Seiko Epson Corporation | Thin-film semiconductor device, and display system using the same |
| JPH07111334A (en) * | 1993-08-20 | 1995-04-25 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
| US6777763B1 (en) | 1993-10-01 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| EP0652595A3 (en) * | 1993-11-05 | 1997-10-01 | Sony Corp | Thin film semiconductor device for display and method of producing same. |
| EP0652595A2 (en) * | 1993-11-05 | 1995-05-10 | Sony Corporation | Thin film semiconductor device for display and method of producing same |
| US6417057B1 (en) | 1994-06-14 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming a semiconductor device having a TFT utilizing optical annealing before a gate electrode is formed |
| US6690063B2 (en) | 1994-06-14 | 2004-02-10 | Semiconductor Energy Laboratory Co., Ltd. | Thin film semiconductor integrated circuit and method for forming the same |
| US6862011B2 (en) | 1996-09-26 | 2005-03-01 | Seiko Epson Corporation | Display apparatus |
| US7012278B2 (en) | 1996-09-26 | 2006-03-14 | Seiko Epson Corporation | Light-emitting apparatus driven with thin-film transistor and method of manufacturing light-emitting apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3072637B2 (en) | 2000-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW406210B (en) | Active matrix display device | |
| JP3647523B2 (en) | Matrix type liquid crystal display device | |
| JP2666103B2 (en) | Thin film semiconductor device | |
| CN100399179C (en) | Pixel structure of a liquid crystal panel, method of fabricating the same and driving method thereof | |
| JPH09186341A (en) | Thin film transistor and manufacture thereof | |
| JP2003332581A (en) | Method of manufacturing thin film transistor substrate and thin film transistor substrate | |
| JPH07202217A (en) | Polycrystalline silicon thin film transistor of ldd type and its manufacture | |
| KR20020013762A (en) | Thin-film semiconductor device | |
| JP3548237B2 (en) | Thin film transistor | |
| JPH05173179A (en) | Active matrix substrate | |
| JP4984369B2 (en) | Image display device and manufacturing method thereof | |
| JPH06317812A (en) | Active matrix element and its production | |
| JP3375681B2 (en) | Method for manufacturing semiconductor device | |
| JP3005918B2 (en) | Active matrix panel | |
| JPH0595117A (en) | Thin film transistor and its manufacture | |
| JP3405352B2 (en) | Active matrix substrate and manufacturing method thereof | |
| JP3312617B2 (en) | Active matrix substrate manufacturing method | |
| JPH0613397A (en) | Thin film bipolar transistor and thin film semiconductor device using it | |
| JPH05114732A (en) | Thin film transistor | |
| JP4353762B2 (en) | Thin film transistor and manufacturing method thereof | |
| JP4197270B2 (en) | Method for manufacturing semiconductor integrated circuit | |
| JP3369664B2 (en) | Liquid crystal display | |
| JP2000315797A (en) | Thin film semiconductor device and liquid crystal display | |
| JP3375914B2 (en) | Method for manufacturing semiconductor device | |
| JPH08186263A (en) | Thin-film transistor and liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090602 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100602 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110602 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110602 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120602 Year of fee payment: 12 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120602 Year of fee payment: 12 |