JPH05166976A - Mounting method of semiconductor element - Google Patents
Mounting method of semiconductor elementInfo
- Publication number
- JPH05166976A JPH05166976A JP32852491A JP32852491A JPH05166976A JP H05166976 A JPH05166976 A JP H05166976A JP 32852491 A JP32852491 A JP 32852491A JP 32852491 A JP32852491 A JP 32852491A JP H05166976 A JPH05166976 A JP H05166976A
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- semiconductor element
- mounting
- electrodes
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は二種類の樹脂を用いて半
導体素子を実装する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a semiconductor device using two kinds of resins.
【０００２】[0002]
【従来の技術】従来、二種類の樹脂を用いて半導体素子
を実装する方法、たとえば、半導体素子表面にまずポリ
イミド樹脂の層を形成し、続いてシリコーン樹脂のコー
ティングまたはポッティングを行う実装方法が用いられ
ていた。2. Description of the Related Art Conventionally, a method of mounting a semiconductor element using two kinds of resins, for example, a mounting method of forming a layer of a polyimide resin on the surface of the semiconductor element and then coating or potting with a silicone resin has been used. It was being done.
【０００３】[0003]
【発明が解決しようとする課題】上記従来の実装方法で
は、二種類の樹脂の親和性が乏しく、界面剥離を生じや
すかった。これを改善するために第一の樹脂層の表面を
キレート処理をするなどして親和性を高める試みもなさ
れているが、一般に処理薬品が高価であったり、新規な
処理装置が必要であるなどの問題があった。In the above-described conventional mounting method, the affinity between the two kinds of resins is poor and the interface peeling is likely to occur. In order to improve this, attempts have been made to increase the affinity by chelating the surface of the first resin layer, but generally the treatment chemicals are expensive, and a new treatment device is required. There was a problem.
【０００４】[0004]
【課題を解決するための手段】上記問題を解決するため
に本発明の半導体素子の実装方法は、半導体素子の表面
に第一樹脂層を形成する工程と、前記第一樹脂層を覆う
第二樹脂層を形成する工程とを含む半導体素子の実装方
法において、前記第二樹脂層の形成前に前記第一樹脂層
の表面を粗面化する工程を有している。In order to solve the above problems, a semiconductor element mounting method of the present invention comprises a step of forming a first resin layer on the surface of the semiconductor element, and a second step of covering the first resin layer. A method of mounting a semiconductor element, which includes a step of forming a resin layer, has a step of roughening a surface of the first resin layer before forming the second resin layer.
【０００５】また、本発明の半導体素子の実装方法は、
半導体素子の表面に突起電極を形成する工程と、半導体
素子の表面に第一樹脂層を形成する工程と、前記第一樹
脂層の表面を粗面化する工程と、前記第一樹脂層を覆う
第二樹脂層を形成する工程と、前記突起電極と実装基板
の電極との接続をする工程と、前記半導体素子と前記実
装基板との間に第二樹脂層を充填する工程とを有してい
る。The semiconductor element mounting method of the present invention is
Forming a protruding electrode on the surface of the semiconductor element, forming a first resin layer on the surface of the semiconductor element, roughening the surface of the first resin layer, and covering the first resin layer The method has a step of forming a second resin layer, a step of connecting the protruding electrode and an electrode of a mounting board, and a step of filling a second resin layer between the semiconductor element and the mounting board. There is.
【０００６】[0006]
【作用】上記本発明の実装方法によれば、第一の樹脂層
と第二の樹脂層との接触面積が増加するので密着力が向
上し、界面剥離を生じることがなくなる。According to the mounting method of the present invention, since the contact area between the first resin layer and the second resin layer is increased, the adhesion is improved and the interface peeling is prevented.
【０００７】[0007]
【実施例】図１及び図２は本発明の実施例を説明する工
程断面図である。アルミニウム電極より内側の表面には
ポリイミド樹脂による第一の樹脂層４が形成されてい
る。厚みは約２．０〜３．０μｍである。このポリイミ
ド樹脂の層を３００〜３５０℃でキュアーした後、酸素
プラズマによるアッシング処理を行う。この処理によっ
てポリイミド樹脂層３の表面は約０．０１〜０．０５μ
ｍ程度の微小な凹凸が形成され、粗面化する。このアッ
シング処理の条件は、たとえば出力４００Ｗ、酸素ガス
流量が６００ｍｌ／分、処理時間は６分間である。つぎ
に半導体素子１の表面のアルミニウム電極２の上にスタ
ッドバンプ法で突起電極４を設ける（図１）。この突起
電極４を液晶パネル等の実装基板８の電極７に導電性接
着剤５で接続する。そして半導体素子１と実装基板８と
の空間に第二の樹脂としてシリコーン樹脂６を充填し、
空間を埋める。続いてシリコーン樹脂６を熱硬化し、半
導体素子１を固定する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 and 2 are process sectional views for explaining an embodiment of the present invention. A first resin layer 4 made of a polyimide resin is formed on the inner surface of the aluminum electrode. The thickness is about 2.0 to 3.0 μm. After this polyimide resin layer is cured at 300 to 350 ° C., an ashing process using oxygen plasma is performed. By this treatment, the surface of the polyimide resin layer 3 is about 0.01-0.05μ.
Minute irregularities of about m are formed and roughened. The conditions of this ashing treatment are, for example, an output of 400 W, an oxygen gas flow rate of 600 ml / min, and a treatment time of 6 minutes. Next, the protruding electrode 4 is provided on the aluminum electrode 2 on the surface of the semiconductor element 1 by the stud bump method (FIG. 1). The protruding electrode 4 is connected to an electrode 7 of a mounting substrate 8 such as a liquid crystal panel with a conductive adhesive 5. Then, the space between the semiconductor element 1 and the mounting substrate 8 is filled with a silicone resin 6 as a second resin,
Fill the space. Then, the silicone resin 6 is thermally cured to fix the semiconductor element 1.
【０００８】図３及び図４はそれぞれ、突起電極を実装
基板の電極に導電性接着剤で接続し、半導体素子と実装
基板との空間にシリコーン樹脂を充填した構造体につい
て、熱衝撃試験及び高温高湿試験をした場合の接続抵抗
の変化を示している。●印でプロットされたのが、ポリ
イミド樹脂層を酸素プラズマによってアッシング処理し
た場合の結果であり、○印でプロットされたのが、ポリ
イミド樹脂層を酸素プラズマによってアッシング処理し
ない従来の実装方法による場合の結果である。3 and 4 show a thermal shock test and a high temperature test for a structure in which a protruding electrode is connected to an electrode of a mounting board with a conductive adhesive and a space between a semiconductor element and the mounting board is filled with a silicone resin. The change in connection resistance when a high humidity test is performed is shown. The plots with ● are the results when the polyimide resin layer is ashed by oxygen plasma, and the plots with ○ are the results of the conventional mounting method in which the polyimide resin layer is not ashed with oxygen plasma. Is the result of.
【０００９】いずれの試験結果においても、ポリイミド
樹脂層を酸素プラズマによってアッシング処理した本発
明の実装方法による場合の方が接続抵抗の変化が少な
く、従来の方法による場合の２分の１以下の変化量に抑
えられている。In any of the test results, the change in connection resistance is smaller in the case of the mounting method of the present invention in which the polyimide resin layer is ashed by oxygen plasma, and is less than half the change in the case of the conventional method. Limited in quantity.
【００１０】[0010]
【発明の効果】以上詳述したように、本発明の半導体素
子の実装方法によれば、半導体素子の表面に第一樹脂層
を形成する工程と、前記第一樹脂層を覆う第二樹脂層を
形成する工程とを含む半導体素子の実装方法において、
両樹脂層の密着性の劣化を生じない、信頼性に優れた実
装構造を実現することができる。As described above in detail, according to the semiconductor element mounting method of the present invention, the step of forming the first resin layer on the surface of the semiconductor element and the second resin layer covering the first resin layer. In the method of mounting a semiconductor element, including the step of forming
It is possible to realize a highly reliable mounting structure in which the adhesiveness between both resin layers does not deteriorate.
【図１】本発明の実装方法の工程断面図FIG. 1 is a process sectional view of a mounting method of the present invention.
【図２】本発明の実装方法の工程断面図FIG. 2 is a process sectional view of a mounting method of the present invention.
【図３】熱衝撃試験をした場合の接続抵抗の変化を示す
図FIG. 3 is a diagram showing a change in connection resistance when a thermal shock test is performed.
【図４】高温高湿試験をした場合の接続抵抗の変化を示
す図FIG. 4 is a diagram showing a change in connection resistance when a high temperature and high humidity test is performed.
１ 半導体素子 ２ アルミ電極 ３ ポリイミド樹脂層 ４ 突起電極 ５ 導電性接着剤 ６ シリコーン樹脂 ７ 電極 ８ 実装基板 1 Semiconductor Element 2 Aluminum Electrode 3 Polyimide Resin Layer 4 Projection Electrode 5 Conductive Adhesive 6 Silicone Resin 7 Electrode 8 Mounting Substrate
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/28 Ｊ 8617−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/28 J 8617-4M
Claims (2)
工程と、前記第一樹脂層を覆う第二樹脂層を形成する工
程とを含む半導体素子の実装方法において、前記第二樹
脂層の形成前に前記第一樹脂層の表面を粗面化する工程
を有する半導体素子の実装方法。1. A method for mounting a semiconductor element, comprising: a step of forming a first resin layer on a surface of a semiconductor element; and a step of forming a second resin layer covering the first resin layer. A method for mounting a semiconductor element, comprising the step of roughening the surface of the first resin layer before forming the.
程と、半導体素子の表面に第一樹脂層を形成する工程
と、前記第一樹脂層の表面を粗面化する工程と、前記第
一樹脂層を覆う第二樹脂層を形成する工程と、前記突起
電極と実装基板の電極との接続をする工程と、前記半導
体素子と前記実装基板との間に第二樹脂層を充填する工
程とを有する半導体素子の実装方法。2. A step of forming a protruding electrode on the surface of a semiconductor element, a step of forming a first resin layer on the surface of a semiconductor element, a step of roughening the surface of the first resin layer, A step of forming a second resin layer covering one resin layer, a step of connecting the protruding electrode and an electrode of a mounting board, and a step of filling a second resin layer between the semiconductor element and the mounting board A method for mounting a semiconductor device having:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32852491A JPH05166976A (en) | 1991-12-12 | 1991-12-12 | Mounting method of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32852491A JPH05166976A (en) | 1991-12-12 | 1991-12-12 | Mounting method of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05166976A true JPH05166976A (en) | 1993-07-02 |
Family
ID=18211251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32852491A Pending JPH05166976A (en) | 1991-12-12 | 1991-12-12 | Mounting method of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05166976A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07159602A (en) * | 1993-12-02 | 1995-06-23 | Dainippon Printing Co Ltd | Antireflection film and its production |
| JPH11274374A (en) * | 1998-03-20 | 1999-10-08 | Citizen Watch Co Ltd | Semiconductor package and its manufacture |
| KR100427925B1 (en) * | 2000-07-04 | 2004-04-28 | 닛본 덴끼 가부시끼가이샤 | Semiconductor device and method for fabricating same |
| JP2007242761A (en) * | 2006-03-07 | 2007-09-20 | Seiko Epson Corp | Method for manufacturing semiconductor device |
| US8236615B2 (en) | 2009-11-25 | 2012-08-07 | International Business Machines Corporation | Passivation layer surface topography modifications for improved integrity in packaged assemblies |
-
1991
- 1991-12-12 JP JP32852491A patent/JPH05166976A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07159602A (en) * | 1993-12-02 | 1995-06-23 | Dainippon Printing Co Ltd | Antireflection film and its production |
| JPH11274374A (en) * | 1998-03-20 | 1999-10-08 | Citizen Watch Co Ltd | Semiconductor package and its manufacture |
| KR100427925B1 (en) * | 2000-07-04 | 2004-04-28 | 닛본 덴끼 가부시끼가이샤 | Semiconductor device and method for fabricating same |
| US6806560B2 (en) | 2000-07-04 | 2004-10-19 | Nec Corporation | Semiconductor device and method for fabricating same |
| US7109067B2 (en) | 2000-07-04 | 2006-09-19 | Nec Corporation | Semiconductor device and method for fabricating same |
| JP2007242761A (en) * | 2006-03-07 | 2007-09-20 | Seiko Epson Corp | Method for manufacturing semiconductor device |
| US8236615B2 (en) | 2009-11-25 | 2012-08-07 | International Business Machines Corporation | Passivation layer surface topography modifications for improved integrity in packaged assemblies |
| US8786059B2 (en) | 2009-11-25 | 2014-07-22 | International Business Machines Corporation | Passivation layer surface topography modifications for improved integrity in packaged assemblies |
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