JPH0514760A - Clock regenerator - Google Patents
Clock regeneratorInfo
- Publication number
- JPH0514760A JPH0514760A JP3158174A JP15817491A JPH0514760A JP H0514760 A JPH0514760 A JP H0514760A JP 3158174 A JP3158174 A JP 3158174A JP 15817491 A JP15817491 A JP 15817491A JP H0514760 A JPH0514760 A JP H0514760A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- output
- pulse width
- polarity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
- Controls And Circuits For Display Device (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＰＬＬ（Ｐｈａｓｅ
Ｌｏｃｋｅｄ Ｌｏｏｐ）回路を用いたクロック再生装
置に関するものである。BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase).
The present invention relates to a clock reproduction device using a Locked Loop circuit.
【０００２】[0002]
【従来の技術】近年、コンピュータ（以下信号源と称す
る。）からの画像データを様々な形で処理する画像処理
が盛んになっている。画像処理を行うには、まず信号源
からの元の画像データをその信号源のクロックでメモリ
に記憶しなければならない。ところが、信号源の機種ご
とに信号形式が異なっている。そのため、信号源の機種
別に適したクロックを作り出す（以下クロック再生と称
する。）必要がある。従来のクロック再生装置の構成は
（図２）に示すような構成で、ａは水平同期信号の入力
端子、５は接続した信号源に応じて分周比の切換えを行
う分周比切替部、４は分周比切替部５からの分周比制御
信号ｉに応じて分周を行う分周器、１は水平同期信号の
入力端子ａからの入力信号ｃと分周器６からの入力信号
ｄの周波数を比較してその周波数差に応じた信号ｅ，ｆ
を出力する位相比較器、２は位相比較器１からの出力信
号ｅ，ｆで制御された電圧ｇを発生するループフィル
タ、３はループフィルタ２からの制御電圧ｇに応じた周
波数ｈを発振する電圧制御形発振器である。分周器４は
入力される電圧制御形発振器３からのある周波数ｈの信
号を、分周比切替部５で指定した分周比Ｂで分周し、ｈ
／Ｂの周波数の信号ｄを出力する。出力した信号ｄと、
接続されている信号源の水平同期信号ｃとの位相を位相
比較器１で比較する。このような構成により接続されて
いる信号源に適した安定なクロック信号ｈを出力端子ｂ
から得ている。2. Description of the Related Art In recent years, image processing for processing image data from a computer (hereinafter referred to as a signal source) in various forms has become popular. To perform image processing, the original image data from the signal source must first be stored in the memory at the clock of the signal source. However, the signal format differs depending on the model of the signal source. Therefore, it is necessary to create a clock suitable for each model of the signal source (hereinafter referred to as clock reproduction). The configuration of the conventional clock regenerator is as shown in FIG. 2, where a is a horizontal sync signal input terminal, 5 is a frequency division ratio switching unit for switching the frequency division ratio according to the connected signal source, Reference numeral 4 is a frequency divider that performs frequency division according to the frequency division ratio control signal i from the frequency division ratio switching unit 1, and 1 is an input signal c from the input terminal a of the horizontal synchronizing signal and an input signal from the frequency divider 6. The frequencies of d are compared, and signals e and f corresponding to the frequency difference are compared.
, A loop filter 2 for generating a voltage g controlled by the output signals e, f from the phase comparator 1, and a oscillator 3 for oscillating a frequency h corresponding to the control voltage g from the loop filter 2. It is a voltage controlled oscillator. The frequency divider 4 divides the input signal of a certain frequency h from the voltage controlled oscillator 3 by the frequency division ratio B designated by the frequency division ratio switching unit 5,
A signal d having a frequency of / B is output. The output signal d,
The phase comparator 1 compares the phase of the connected signal source with the horizontal synchronizing signal c. With this configuration, a stable clock signal h suitable for the connected signal source is output terminal b.
Is obtained from
【０００３】[0003]
【発明が解決しようとする課題】このように従来のクロ
ック再生装置では、分周器４の分周比の切替えの指示を
分周比切替部５で行っているが、接続されている信号源
がかわるごとに分周比の設定変更を行わなければならず
繁雑であった。As described above, in the conventional clock regenerator, the division ratio switching section 5 gives an instruction to switch the division ratio of the frequency divider 4, but the connected signal source is connected. Every time it changed, the division ratio setting had to be changed, which was complicated.
【０００４】本発明は接続される信号源がかわっても、
自動的にその信号源に対応したクロック信号の再生を実
現するクロック再生装置を提供しようとするものであ
る。In the present invention, even if the connected signal source is changed,
It is an object of the present invention to provide a clock reproduction device that automatically realizes reproduction of a clock signal corresponding to the signal source.
【０００５】[0005]
【課題を解決するための手段】本発明のクロック再生装
置は、水平同期信号の周波数と水平同期信号の極性と水
平同期信号のパルス幅と垂直同期信号の周波数と垂直同
期信号の極性と垂直同期信号のパルス幅より接続されて
いる信号源の機種を判定し、その信号源に応じた分周比
の指示を自動的に行い、目的とするクロックを再生する
ことを特徴とする。According to the clock reproducing apparatus of the present invention, the frequency of the horizontal synchronizing signal, the polarity of the horizontal synchronizing signal, the pulse width of the horizontal synchronizing signal, the frequency of the vertical synchronizing signal, the polarity of the vertical synchronizing signal, and the vertical synchronizing. It is characterized by determining the model of the connected signal source from the pulse width of the signal, automatically instructing the division ratio according to the signal source, and reproducing the target clock.
【０００６】[0006]
【作用】本発明のクロック再生装置によれば、接続され
ている信号源がかわっても自動的にその信号源に対応し
たクロック信号の再生を実現しうるものである。According to the clock reproducing apparatus of the present invention, even if the connected signal source is changed, the clock signal corresponding to the signal source can be automatically reproduced.
【０００７】[0007]
【実施例】以下に、本発明の一実施例について（図１）
を用いて説明する。ａは水平同期信号の入力端子で接続
されている信号源の水平同期信号ｃのみを入力する。ｊ
は垂直同期信号の入力端子で接続されている信号源の垂
直同期信号ｈのみを入力する。６は水平同期信号の周波
数を測定する周波数測定部、７は水平同期信号の極性を
判定する極性判定部、８は水平同期信号のパルス幅を測
定するパルス幅測定部、９は垂直同期信号の周波数を測
定する周波数測定部、１０は垂直同期信号の極性を判定
する極性判定部、１１は垂直同期信号のパルス幅を測定
するパルス幅測定部で、それらの内の周波数測定部６、
９及びパルス幅測定部８、１１はカウンタなどで各々構
成すればよい。極性判定部７、１０については、各々同
期信号の同期パルスを除く箇所でＬＯＷレベルであれば
正極性、ＨＩレベルであれば負極性と判定すればよい。
１２は接続されている信号源を判定し分周器４への分周
比の指示を与える判定部で、接続する信号源の機種別に
水平同期信号の周波数と極性とパルス幅、及び垂直同期
信号の周波数と極性とパルス幅のデ−タを全てマイクロ
コンピュータのＲＯＭテーブルに保管しておき、それと
測定したデータを比較し、上記６項目がすべて等しいも
のが現在接続されている信号源の機種と判定すればよ
い。その後、その信号源に対応した分周比で分周を行う
よう分周器４に指示を与えるが、これらの各信号源に対
応した分周比のデータも別のテーブルに保管しておき必
要に応じてマイクロコンピュータから指示を与え自動的
に設定できる。分周器４と以下の位相比較器１、ループ
フィルタ２、電圧制御形発振器３でＰＬＬ（Ｐｈａｓｅ
Ｌｏｃｋｅｄ Ｌｏｏｐ）回路を形成して、接続され
ている信号源に対応した安定なクロック信号を再生して
いる。ループフィルタ２は一般にアクテイブＲＣフィル
タと呼ばれるもので、入力信号ｅ，ｆが共に１の時は、
出力である制御電圧ｇは変化しない。入力信号ｅが０
で、ｆが１の時は電圧制御形発振器３の出力信号ｈの周
波数を上げる方向に制御電圧ｇが変化する。入力信号ｅ
が１で、ｆが０の時は電圧制御形発振器３の出力信号ｈ
の周波数を下げる方向に制御電圧ｇが変化するとする。
もし、信号ｃとｄの位相が一致している場合、位相比較
器１の出力ｅ，ｆは共に１となり、ループフィルタ２は
これを受けて、電圧制御形発振器３に対して出力される
制御電圧ｇを変化させない。一方信号ｃの位相が信号ｄ
より進んでいる時は信号ｅが０、ｆが１となり、ループ
フィルタ２はこれを受けて電圧制御形発振器３に対し
て、その発振周波数を上げるための制御電圧ｇを出力す
る。従って電圧制御形発振器３の発振周波数は上昇し信
号ｃとｄの位相が一致するよう制御される。また信号ｃ
の位相が信号ｄより遅れた場合は信号ｅは１、ｆが０と
なり、ループフィルタ２はこれを受けて電圧制御形発振
器３に対して、その発振周波数を下げるための制御電圧
ｇを出力する。従って、電圧制御形発振器３の発振周波
数は低下し、同様に信号ｃとｄの位相が一致するように
制御される。EXAMPLE An example of the present invention will be described below (FIG. 1).
Will be explained. The input a of the horizontal synchronizing signal is a horizontal synchronizing signal c which is a signal source connected to the horizontal synchronizing signal. j
Inputs only the vertical synchronizing signal h of the signal source connected at the input terminal of the vertical synchronizing signal. 6 is a frequency measuring unit that measures the frequency of the horizontal synchronizing signal, 7 is a polarity determining unit that determines the polarity of the horizontal synchronizing signal, 8 is a pulse width measuring unit that measures the pulse width of the horizontal synchronizing signal, and 9 is the vertical synchronizing signal. A frequency measuring unit for measuring the frequency, 10 is a polarity determining unit for determining the polarity of the vertical synchronizing signal, 11 is a pulse width measuring unit for measuring the pulse width of the vertical synchronizing signal, of which the frequency measuring unit 6,
9 and the pulse width measuring units 8 and 11 may each be configured by a counter or the like. With respect to the polarity determination sections 7 and 10, it is only necessary to determine positive polarity if the level is LOW and negative polarity if the level is HI at a position excluding the sync pulse of the sync signal.
Reference numeral 12 is a determination unit that determines the connected signal source and gives a frequency division ratio instruction to the frequency divider 4. The frequency and polarity, the pulse width, and the vertical synchronization signal of the horizontal synchronization signal for each model of the connected signal source. All frequency, polarity, and pulse width data are stored in the ROM table of the microcomputer, and the measured data are compared. All the above six items are the same as the currently connected signal source model. Just make a decision. After that, the frequency divider 4 is instructed to perform the frequency division at the frequency division ratio corresponding to the signal source, but the data of the frequency division ratio corresponding to each of these signal sources is also stored in another table. It can be automatically set by giving an instruction from a microcomputer according to. The frequency divider 4 and the following phase comparator 1, loop filter 2, and voltage-controlled oscillator 3 are used for PLL (Phase).
A locked loop circuit is formed to reproduce a stable clock signal corresponding to the connected signal source. Loop filter 2 is generally called a Akti Lee blanking RC filter, the input signal e, when f are both 1,
The output control voltage g does not change. Input signal e is 0
When f is 1, the control voltage g changes in the direction of increasing the frequency of the output signal h of the voltage controlled oscillator 3. Input signal e
Is 1 and f is 0, the output signal h of the voltage controlled oscillator 3
It is assumed that the control voltage g changes in the direction of decreasing the frequency of.
If the phases of the signals c and d match, the outputs e and f of the phase comparator 1 both become 1, and the loop filter 2 receives this and outputs the control to the voltage controlled oscillator 3. Do not change the voltage g. On the other hand, the phase of the signal c is the signal d
When the signal is further advanced, the signals e become 0 and f becomes 1, and the loop filter 2 receives this and outputs the control voltage g for increasing the oscillation frequency to the voltage controlled oscillator 3. Therefore, the oscillation frequency of the voltage controlled oscillator 3 rises and the signals c and d are controlled so that the phases thereof match. Also signal c
, The signal e becomes 1 and the signal f becomes 0, and the loop filter 2 receives this and outputs the control voltage g for lowering the oscillation frequency to the voltage controlled oscillator 3. .. Therefore, the oscillation frequency of the voltage controlled oscillator 3 is lowered, and similarly, the signals c and d are controlled so that their phases match each other.
【０００８】かかる構成によれば、接続されている信号
源の機種を自動的に検出し、分周比の設定を自動的に行
い、必要なクロック信号を再生することができ、手動に
よる繁雑な分周比の設定を行わずに済む。With such a configuration, the model of the connected signal source can be automatically detected, the division ratio can be set automatically, and the necessary clock signal can be reproduced, which is complicated and complicated by manual operation. It is not necessary to set the division ratio.
【０００９】[0009]
【発明の効果】以上のように、本発明のクロック再生装
置によれば、接続する信号源が変わっても、それに追従
して自動的に分周比を切替え、必要なクロック信号を再
生することができ繁雑な分周比の切替えを行う必要がな
く、容易に素早くクロック再生が行える。As described above, according to the clock reproducing apparatus of the present invention, even if the connected signal source changes, the frequency division ratio is automatically switched to follow the change and the necessary clock signal is reproduced. The clock can be easily and quickly reproduced without the need for complicated switching of the division ratio.
【図１】本発明の一実施例におけるクロック再生装置の
ブロック図FIG. 1 is a block diagram of a clock recovery device according to an embodiment of the present invention.
【図２】従来例のクロック再生装置のブロック図FIG. 2 is a block diagram of a conventional clock recovery device.
１ 位相比較器 ２ ル−プフィルタ ３ 電圧制御形発振器 ４ 分周器 ６ 水平同期信号の周波数測定部 ７ 水平同期信号の極性判定部 ８ 水平同期信号のパルス幅測定部 ９ 垂直同期信号の周波数測定部 １０ 垂直同期信号の極性判定部 １１ 垂直同期信号のパルス幅測定部 １２ 接続信号源の機種判定部 ａ 水平同期信号の入力端子 ｌ 水平同期信号の周波数を表す信号 1 Phase Comparator 2 Loop Filter 3 Voltage Controlled Oscillator 4 Frequency Divider 6 Horizontal Sync Signal Frequency Measuring Section 7 Horizontal Sync Signal Polarity Judging Section 8 Horizontal Sync Signal Pulse Width Measuring Section 9 Vertical Sync Signal Frequency Measuring Section 10 Vertical sync signal polarity determination unit 11 Vertical sync signal pulse width measurement unit 12 Connection signal source model determination unit a Horizontal sync signal input terminal l Signal representing the frequency of the horizontal sync signal
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０３Ｌ 7/08 Ｈ０４Ｎ 5/04 Ｚ 9070−5Ｃ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI Technical display location H03L 7/08 H04N 5/04 Z 9070-5C
Claims (1)
波数を測定する水平同期信号の周波数測定部と、上記信
号源から出力される水平同期信号の極性を判定する水平
同期信号の極性判定部と、上記信号源から出力される水
平同期信号のパルス幅を測定する水平同期信号のパルス
幅測定部と、上記信号源から出力される垂直同期信号の
周波数を測定する垂直同期信号の周波数測定部と、上記
信号源から出力される垂直同期信号の極性を判定する垂
直同期信号の極性判定部と、上記信号源から出力される
垂直同期信号のパルス幅を測定する垂直同期信号のパル
ス幅測定部と、上記水平同期信号の周波数測定部から出
力される周波数を表す信号と上記水平同期信号の極性判
定部から出力される極性を表す信号と上記水平同期信号
のパルス幅測定部から出力されるパルス幅を表す信号と
上記垂直同期信号の周波数測定部から出力される周波数
を表す信号と上記垂直同期信号の極性判定部から出力さ
れる極性を表す信号と上記垂直同期信号のパルス幅測定
部から出力されるパルス幅を表す信号より接続されてい
る信号源の機種を判定し機種に対応する分周比を示す信
号を出力する判定部と、第１の入力端子に上記信号源か
ら出力される水平同期信号を入力する位相比較器と、上
記位相比較器の比較結果に応じて出力される第１および
第２の出力を入力するループフィルタと、上記ループフ
ィルタの出力に応じた発振周波数の出力信号を出力する
電圧制御形発振器と、上記電圧制御形発振器の出力を上
記判定部からの出力である分周比を示す信号に基づき分
周する分周器とを有し、上記分周器の出力を上記位相比
較器の第２の入力端子に入力して上記位相比較器の第１
の入力端子に入力される水平同期信号と第２の入力端子
に入力される信号の位相比較を行うクロック再生装置。Claim: What is claimed is: 1. A horizontal synchronization signal frequency measuring unit for measuring the frequency of a horizontal synchronization signal output from a signal source, and a horizontal determination unit for determining the polarity of the horizontal synchronization signal output from the signal source. A sync signal polarity determination unit, a horizontal sync signal pulse width measurement unit that measures the pulse width of the horizontal sync signal output from the signal source, and a vertical measurement unit that measures the frequency of the vertical sync signal output from the signal source. Sync signal frequency measuring unit, vertical sync signal polarity determining unit that determines the polarity of the vertical sync signal output from the signal source, and vertical sync that measures the pulse width of the vertical sync signal output from the signal source. A signal representing the frequency output from the pulse width measuring section of the signal, the frequency measuring section of the horizontal synchronizing signal, a signal representing the polarity output from the polarity determining section of the horizontal synchronizing signal, and the horizontal synchronizing signal. A signal representing the pulse width output from the pulse width measuring unit, a signal representing the frequency output from the frequency measuring unit of the vertical synchronizing signal, a signal representing the polarity output from the polarity determining unit of the vertical synchronizing signal, and A determination unit that determines the model of the connected signal source from the signal indicating the pulse width output from the pulse width measurement unit of the vertical synchronization signal and outputs a signal indicating the division ratio corresponding to the model, and a first input A phase comparator for inputting a horizontal synchronizing signal output from the signal source to a terminal, a loop filter for inputting first and second outputs output according to a comparison result of the phase comparator, and the loop filter A voltage-controlled oscillator that outputs an output signal having an oscillation frequency corresponding to the output of the frequency-controlled oscillator, and a frequency divider that divides the output of the voltage-controlled oscillator based on the signal indicating the frequency division ratio that is the output from the determination unit, To The output of the frequency divider is input to the second input terminal of the phase comparator to output the first of the phase comparator.
Of the horizontal synchronizing signal input to the input terminal of the input terminal and the signal input to the second input terminal of the clock recovery apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3158174A JPH0514760A (en) | 1991-06-28 | 1991-06-28 | Clock regenerator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3158174A JPH0514760A (en) | 1991-06-28 | 1991-06-28 | Clock regenerator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0514760A true JPH0514760A (en) | 1993-01-22 |
Family
ID=15665895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3158174A Pending JPH0514760A (en) | 1991-06-28 | 1991-06-28 | Clock regenerator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0514760A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486857B1 (en) | 1999-02-12 | 2002-11-26 | Nec Corporation | Deflection correction circuit for narrowing a pull-in range of a VCO to reduce frequency variations in a horizontal synchronizing signal |
| JP2009055396A (en) * | 2007-08-28 | 2009-03-12 | Nec Electronics Corp | Horizontal synchronization detecting device |
| USRE41522E1 (en) | 1995-10-20 | 2010-08-17 | Seiko Epson Corporation | Method and apparatus for scaling up and down a video image |
| US8184665B2 (en) | 2009-01-07 | 2012-05-22 | Fujitsu Limited | Network device |
-
1991
- 1991-06-28 JP JP3158174A patent/JPH0514760A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE41522E1 (en) | 1995-10-20 | 2010-08-17 | Seiko Epson Corporation | Method and apparatus for scaling up and down a video image |
| USRE42656E1 (en) | 1995-10-20 | 2011-08-30 | Seiko Epson Corporation | Method and apparatus for scaling up and down a video image |
| USRE43641E1 (en) | 1995-10-20 | 2012-09-11 | Seiko Epson Corporation | Method and apparatus for scaling up and down a video image |
| US6486857B1 (en) | 1999-02-12 | 2002-11-26 | Nec Corporation | Deflection correction circuit for narrowing a pull-in range of a VCO to reduce frequency variations in a horizontal synchronizing signal |
| JP2009055396A (en) * | 2007-08-28 | 2009-03-12 | Nec Electronics Corp | Horizontal synchronization detecting device |
| US8184665B2 (en) | 2009-01-07 | 2012-05-22 | Fujitsu Limited | Network device |
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