JPH05136298A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05136298A JPH05136298A JP29885591A JP29885591A JPH05136298A JP H05136298 A JPH05136298 A JP H05136298A JP 29885591 A JP29885591 A JP 29885591A JP 29885591 A JP29885591 A JP 29885591A JP H05136298 A JPH05136298 A JP H05136298A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- resist
- polyimide
- protective film
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方
法、特に、半導体素子の表面保護膜のパターニング方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of patterning a surface protective film of a semiconductor element.
【０００２】[0002]
【従来の技術】半導体素子が形成された半導体基板表面
には、アルミなどの配線を保護するために、プラズマ窒
化膜やＰＳＧ（Ｐｈｏｓｐｈｏ−Ｓｉｌｉｃａｔｅ Ｇ
ｌａｓｓ）の様な無機材料から成る保護膜が形成され
る。このようにして形成された半導体チップは、リード
フレームにボンディングされた後、エポキシ樹脂等のモ
ールド樹脂体によって封止される。近年では、モールド
樹脂の半導体チップに対する応力緩和のために無機材料
から成る上記保護膜上にポリイミド等の有機高分子膜を
バッファーコーティング膜として形成する方法がとられ
ている。2. Description of the Related Art On the surface of a semiconductor substrate having a semiconductor element formed thereon, a plasma nitride film or PSG (Phospho-Silicate G
A protective film made of an inorganic material such as (lass) is formed. The semiconductor chip thus formed is bonded to a lead frame and then sealed with a mold resin body such as an epoxy resin. In recent years, a method has been adopted in which an organic polymer film such as polyimide is formed as a buffer coating film on the protective film made of an inorganic material in order to relax the stress of the mold resin on the semiconductor chip.
【０００３】しかしながら、有機系高分子材料から成る
保護膜は、モールド樹脂との密着性が悪いということか
ら、熱衝撃等の衝撃が加わった場合に、半導体チップと
モールド樹脂体との間に空隙を生じることがある。この
空隙が形成されると、外部から浸入した水分がこの空隙
に大量に蓄積される。この水分にモールド樹脂体から溶
け出した不純物イオンが溶け込むと、アルミニウム等か
らなる電極を腐食させる要因となる。また、多量に蓄積
された水分が熱変化で膨張・収縮を繰り返すため、この
ストレスによりモールド樹脂体のクラック（き裂）を発
生する原因にもなる。However, since the protective film made of an organic polymer material has poor adhesion to the mold resin, when a shock such as a thermal shock is applied, a gap is formed between the semiconductor chip and the mold resin body. May occur. When this void is formed, a large amount of moisture that has entered from the outside is accumulated in this void. If the impurity ions dissolved from the mold resin body dissolve in this water, it becomes a factor that corrodes the electrode made of aluminum or the like. Further, since a large amount of accumulated water repeatedly expands and contracts due to heat change, this stress also causes a crack (crack) in the mold resin body.
【０００４】この欠点を解消するために、例えば有機系
高分子材料から成る保護膜とモールド樹脂体との境界の
一部または全部を多数の凹凸を有する面で形成し、熱衝
撃後も十分耐性を確保できるようにした製造方法、たと
えば特開昭６２−１５０８５９号が開示されている。In order to solve this drawback, for example, a part or the whole of the boundary between the protective film made of an organic polymer material and the mold resin body is formed by a surface having a large number of irregularities so that it is sufficiently resistant to thermal shock. A manufacturing method capable of ensuring the above is disclosed, for example, JP-A-62-150859.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、前記の
製造方法では有機系高分子保護膜の表面に凹凸を設ける
ための、ホトリソおよびエッチング工程を増やさねばな
らず、工程数増加によるコストアップ、歩留りの低下、
生産効率低下の原因となる欠点があった。However, in the above manufacturing method, it is necessary to increase the number of photolithography and etching steps for forming the unevenness on the surface of the organic polymer protective film, which results in an increase in cost and yield. Decline,
There was a drawback that caused a drop in production efficiency.
【０００６】本発明は、前記有機系高分子保護膜表面の
凹凸を前記製造方法よりも、少ない工程数で形成するこ
とにより、前記欠点を解消することを目的とする。An object of the present invention is to eliminate the above-mentioned drawbacks by forming irregularities on the surface of the organic polymer protective film in a smaller number of steps than in the manufacturing method.
【０００７】[0007]
【課題を解決するための手段】本発明は、以上述べた工
程数増加によるコストアップ、歩留りの低下、生産効率
低下などの問題点を除去するため、有機系高分子材料保
護膜をパターニングする際に、前記保護膜表面に、解像
不良を利用した多数の凹部を、電極引き出し部となるパ
ッド部を開口するとともに形成することにより、半導体
装置の製造工程数を少なくしたものである。In order to eliminate the above-mentioned problems such as an increase in cost due to an increase in the number of steps, a decrease in yield, a decrease in production efficiency and the like, the present invention provides a method of patterning an organic polymer material protective film In addition, the number of manufacturing steps of the semiconductor device is reduced by forming a large number of concave portions utilizing the poor resolution together with the opening of the pad portion serving as the electrode lead portion on the surface of the protective film.
【０００８】[0008]
【作用】本発明においては、モールド樹脂体と有機系高
分子保護膜との密着性を良くするための両者境界面の凹
凸部を、電極引き出し部となるパッド部を開口する際
に、解像不良を利用することにより、前記保護膜表面
に、前記パッド部を形成するとともに形成する。この結
果、製造工程数を減少させることができる。According to the present invention, the uneven portion of the boundary surface between the mold resin body and the organic polymer protective film for improving the adhesion is improved when the pad portion serving as the electrode lead-out portion is opened. By utilizing a defect, the pad portion is formed and formed on the surface of the protective film. As a result, the number of manufacturing steps can be reduced.
【０００９】ここで、解像不良とは、レジストを塗布し
た半導体基板を設計パターンを描いたマスクを用いて露
光する際、前記パターンの線巾が解像限界以下の場合
は、露光光がレジスト底部まで到達せず、その結果、現
象しても、レジストが完全に除去できず凹部となる現象
を言う。The term "defective resolution" means that when a semiconductor substrate coated with a resist is exposed using a mask having a design pattern drawn, and the line width of the pattern is below the resolution limit, the exposure light is used as a resist. The phenomenon that the resist does not reach the bottom and, as a result, the resist cannot be completely removed and becomes a recess even if the phenomenon occurs.
【００１０】[0010]
【実施例】本発明の半導体装置の製造方法について図面
を用いて詳細に説明する。図１は本発明に係る半導体装
置の製造方法の工程断面図である。図２は本発明に係る
半導体装置のマスクパターンを示す図、図３は本発明に
係る半導体装置の他のマスクパターンを示す図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device manufacturing method of the present invention will be described in detail with reference to the drawings. 1A to 1D are process cross-sectional views of a method for manufacturing a semiconductor device according to the present invention. FIG. 2 is a diagram showing a mask pattern of the semiconductor device according to the present invention, and FIG. 3 is a diagram showing another mask pattern of the semiconductor device according to the present invention.
【００１１】図１（ａ）に示すように、図示してない半
導体素子およびアルミ電極２が形成された半導体基板１
上に、無機材料から成るパッシベーション膜、この例で
はＰＳＧ膜３を全面に形成する。次いで、図１（ｂ）に
示すようにホトリソおよびエッチングによりアルミ電極
２を露出する。更に、図１（ｃ）に示すように有機系高
分子膜、この例ではポリイミド４を形成する。次に図１
（ｄ）に示すようにレジスト５を塗布する。この後、図
２に示すような前記アルミ電極２を露出させるためのパ
ターン２１の他に、２μｍ角のパターン２２を有するマ
スクを用いて、密着露光法により露光し、現像する。As shown in FIG. 1A, a semiconductor substrate 1 having a semiconductor element (not shown) and an aluminum electrode 2 formed thereon.
A passivation film made of an inorganic material, which is a PSG film 3 in this example, is formed on the entire surface. Next, as shown in FIG. 1B, the aluminum electrode 2 is exposed by photolithography and etching. Further, as shown in FIG. 1C, an organic polymer film, polyimide 4 in this example, is formed. Next in FIG.
A resist 5 is applied as shown in (d). After that, a mask having a 2 μm square pattern 22 in addition to the pattern 21 for exposing the aluminum electrode 2 as shown in FIG. 2 is used to expose and develop by a contact exposure method.
【００１２】ここで、密着露光法では２μｍ以下のパタ
ーンは解像不良となり、パターン２５に対応する部分の
前記レジスト５は完全に露光されず、この後現像を行う
と、図１（ｅ）に示すようにパターン２５に対応する部
分のレジスト表面に凹部６が形成される。このレジスト
５をマスクに下地であるポリイミド４をエッチングする
と、凹部６に対応する部分のポリイミド４はわずかにエ
ッチングされ、図１（ｆ）に示すように凹部７が、アル
ミ電極２を露出するとともに形成される。この後、ワイ
ヤーボンディングし、モールド封止すれば、図１（ｇ）
に示すようにポリイミド４とモールド樹脂体１０との境
界面は凹凸面になり、両者の機械的密着性が大となる。
この結果、熱衝撃を受けた場合に両者間に空隙が生ずる
ことがなくなり、装置の耐湿性を確保することができ
る。Here, in the contact exposure method, a pattern of 2 μm or less has a poor resolution, and the resist 5 in the portion corresponding to the pattern 25 is not completely exposed. As shown, the concave portion 6 is formed on the resist surface corresponding to the pattern 25. When the underlying polyimide 4 is etched using the resist 5 as a mask, the polyimide 4 in the portion corresponding to the recess 6 is slightly etched, and the recess 7 exposes the aluminum electrode 2 as shown in FIG. 1 (f). It is formed. After this, wire bonding and mold sealing are performed, as shown in FIG.
As shown in (4), the boundary surface between the polyimide 4 and the mold resin body 10 becomes an uneven surface, and the mechanical adhesion between them becomes large.
As a result, when a thermal shock is applied, no void is generated between the two, and the moisture resistance of the device can be secured.
【００１３】ここでは、密着露光法を用いたが、反射投
影露光法など解像限界を持つ露光法であれば解像限界巾
以下のパターンを用いて同様の効果を得ることができ
る。Although the contact exposure method is used here, the same effect can be obtained by using a pattern having a resolution limit width or less if the exposure method has a resolution limit such as a reflection projection exposure method.
【００１４】また、ここでは解像不良となるパターンと
して、２μｍ角のパターンをマスク上に形成し用いた
が、図３に示すような（ａ）階段形状あるいは（ｂ）十
文字形等、解像限界巾以下で描かれたパターンならどの
ような形状でも構わない。Although a 2 μm square pattern is formed on a mask as a pattern which causes poor resolution, it is possible to use a pattern such as (a) staircase shape or (b) cross shape as shown in FIG. Any shape may be used as long as it is a pattern drawn within the limit width.
【００１５】また、解像限界巾は、露光装置のみでな
く、レジストの感度によっても変化するので、適宜線巾
を検討する必要がある。また、凹部の深さは、レジスト
と保護膜の膜厚比、エッチング選択比にも関係するの
で、適当な深さになるように、パターン巾を調整する必
要がある。この場合、有機系高分子保護膜の代わりに感
光性有機系高分子保護膜を用いれば、このような調整は
不要となる。Further, since the resolution limit width varies depending not only on the exposure apparatus but also on the sensitivity of the resist, it is necessary to consider the line width appropriately. Further, since the depth of the recess is related to the film thickness ratio between the resist and the protective film and the etching selection ratio, it is necessary to adjust the pattern width so as to have an appropriate depth. In this case, if a photosensitive organic polymer protective film is used instead of the organic polymer protective film, such adjustment becomes unnecessary.
【００１６】また、ここでは有機系高分子保護膜上に凹
部を設けているが、モールド樹脂体との境界面となる面
であればどこに設けてもよい。Although the concave portion is provided on the organic polymer protective film here, it may be provided on any surface as long as it becomes a boundary surface with the mold resin body.
【００１７】[0017]
【発明の効果】以上、詳細に説明したように、本発明に
よればモールド樹脂体と保護膜との密着性を良くするた
めの凹部を、解像不良を利用して、電極引き出し部とな
るパッド部を開口すると同時に形成するため、熱衝撃後
の耐湿性を前記の特開昭６２−１５０８５９号公報に開
示された製造方法より少ない工程数で得ることができ、
工程数減少によるコストダウン、歩留りの向上、生産効
率向上をはかることができる。As described above in detail, according to the present invention, the concave portion for improving the adhesion between the mold resin body and the protective film becomes the electrode lead portion by utilizing the poor resolution. Since the pad portion is formed at the same time when the pad portion is opened, moisture resistance after thermal shock can be obtained with a smaller number of steps than the manufacturing method disclosed in the above-mentioned JP-A-62-150859.
It is possible to reduce costs by reducing the number of steps, improve yield, and improve production efficiency.
【図１】本発明に係る半導体装置の各工程における半導
体基板の断面図FIG. 1 is a sectional view of a semiconductor substrate in each step of a semiconductor device according to the present invention.
【図２】本発明に係る半導体装置のマスクパターンを示
す図FIG. 2 is a diagram showing a mask pattern of a semiconductor device according to the present invention.
【図３】本発明に係る半導体装置の他のマスクパターン
を示す図FIG. 3 is a view showing another mask pattern of the semiconductor device according to the present invention.
１ シリコン基板 ２ アルミ電極 ３ ＰＳＧ膜 ４ ポリイミド膜 ５ レジスト膜 ６ レジスト膜上の凹部 ７ 有機系高分子膜上の凹部 ８ モールド樹脂体 ２２ 電極部露出用パターン ２５ ２μｍ角のパターン 1 Silicon substrate 2 Aluminum electrode 3 PSG film 4 Polyimide film 5 Resist film 6 Recess on resist film 7 Recess on organic polymer film 8 Mold resin body 22 Electrode part exposure pattern 25 2 μm square pattern
Claims (1)
なるパッド部が形成された半導体基板を準備する工程
と、前記半導体基板の主表面上を覆う保護膜を形成する
工程と、 前記パッド部を露出させるための第１パターンと、解像
不良を起こす線巾で描かれた第２パターンとを有するマ
スクパターンを準備する工程と、 前記保護膜を、前記マスクパターンを用いたホトリソグ
ラフィーおよびエッチングにより、前記保護膜表面の前
記第１パターンに対応した位置に開口部を形成し、パッ
ド部を露出させるとともに、前記第２パターンに対応し
た位置に凹部を形成する工程とを有する半導体装置の製
造方法。1. A step of preparing a semiconductor substrate in which a semiconductor element and a pad section to be an electrode lead section are formed on a main surface, a step of forming a protective film covering the main surface of the semiconductor substrate, and the pad section. A mask pattern having a first pattern for exposing the mask and a second pattern drawn with a line width that causes poor resolution, and the protective film is formed by photolithography and etching using the mask pattern. Thereby forming an opening at a position corresponding to the first pattern on the surface of the protective film, exposing the pad portion, and forming a recess at a position corresponding to the second pattern. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29885591A JPH05136298A (en) | 1991-11-14 | 1991-11-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29885591A JPH05136298A (en) | 1991-11-14 | 1991-11-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05136298A true JPH05136298A (en) | 1993-06-01 |
Family
ID=17865073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29885591A Pending JPH05136298A (en) | 1991-11-14 | 1991-11-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05136298A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2378578A (en) * | 2001-03-13 | 2003-02-12 | Nec Corp | Semiconductor device encapsulation |
| US7906859B2 (en) | 2007-08-22 | 2011-03-15 | Denso Corporation | Semiconductor device |
| JP2011164628A (en) * | 2011-03-02 | 2011-08-25 | Semiconductor Energy Lab Co Ltd | Method of manufacturing electro-optical device |
| JP2013519235A (en) * | 2010-02-05 | 2013-05-23 | クアルコム，インコーポレイテッド | Die surface treatment to improve bond strength |
| JP2014220463A (en) * | 2013-05-10 | 2014-11-20 | 住友電工デバイス・イノベーション株式会社 | Semiconductor device |
| US9947752B2 (en) | 2016-07-21 | 2018-04-17 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device having protection film with recess |
| JP2020181873A (en) * | 2019-04-24 | 2020-11-05 | トヨタ自動車株式会社 | Semiconductor device and manufacturing method thereof |
-
1991
- 1991-11-14 JP JP29885591A patent/JPH05136298A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2378578A (en) * | 2001-03-13 | 2003-02-12 | Nec Corp | Semiconductor device encapsulation |
| US7906859B2 (en) | 2007-08-22 | 2011-03-15 | Denso Corporation | Semiconductor device |
| JP2013519235A (en) * | 2010-02-05 | 2013-05-23 | クアルコム，インコーポレイテッド | Die surface treatment to improve bond strength |
| JP2011164628A (en) * | 2011-03-02 | 2011-08-25 | Semiconductor Energy Lab Co Ltd | Method of manufacturing electro-optical device |
| JP2014220463A (en) * | 2013-05-10 | 2014-11-20 | 住友電工デバイス・イノベーション株式会社 | Semiconductor device |
| US9583412B2 (en) | 2013-05-10 | 2017-02-28 | Sumitomo Electric Device Innovations, Inc. | Semiconductor device |
| US9947752B2 (en) | 2016-07-21 | 2018-04-17 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device having protection film with recess |
| JP2020181873A (en) * | 2019-04-24 | 2020-11-05 | トヨタ自動車株式会社 | Semiconductor device and manufacturing method thereof |
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