JPH05129609A - Semiconductor element and manufacture thereof - Google Patents
Semiconductor element and manufacture thereofInfo
- Publication number
- JPH05129609A JPH05129609A JP8368892A JP8368892A JPH05129609A JP H05129609 A JPH05129609 A JP H05129609A JP 8368892 A JP8368892 A JP 8368892A JP 8368892 A JP8368892 A JP 8368892A JP H05129609 A JPH05129609 A JP H05129609A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon compound
- sin
- substrate
- glass substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ディスプレイデバイス
やイメージセンサ等に使用できる薄膜トランジスタ及び
その製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor which can be used in a display device, an image sensor and the like, and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】液晶ディスプレイデバイスやイメージセ
ンサ等の駆動に用いる薄膜トランジスタは、従来のＩＣ
プロセスと同じプロセスで作製されていた。従来のＩＣ
プロセスは結晶化、絶縁膜の形成及び不純物の活性化を
１０００℃近い高温で行う必要があり、透光性基板を必
要とする時には基板材料が石英基板に限定されてしまい
大面積化が困難であった。2. Description of the Related Art A thin film transistor used for driving a liquid crystal display device or an image sensor is a conventional IC.
It was made by the same process as the process. Conventional IC
The process requires crystallization, formation of an insulating film, and activation of impurities at a high temperature close to 1000 ° C., and when a translucent substrate is required, the substrate material is limited to a quartz substrate, and it is difficult to increase the area. there were.
【０００３】近年、プロセスの低温化の方法が提案さ
れ、ガラス基板上に形成された非晶質膜あるいは多結晶
膜を出発材料とし、低温固相成長、レーザアニール等で
結晶化させる方法が検討されている。In recent years, a method for lowering the temperature of the process has been proposed, and a method for crystallizing an amorphous film or a polycrystalline film formed on a glass substrate as a starting material by low temperature solid phase growth, laser annealing or the like is examined. Has been done.
【０００４】ガラス基板上に薄膜トランジスタ等の各種
半導体素子を形成する場合、作製プロセス上の洗浄、エ
ッチング、熱処理、イオン注入、プラズマ処理等によ
り、ガラス基板中の不純物イオンが半導体素子中に拡散
されて悪影響を与えてしまう問題があった。例えば薄膜
トランジスタの場合、不純物イオンがチャンネル層に拡
散され、オフ電流が増大してトランジスタ特性を悪化さ
せてしまう問題がある。そこで従来、例えば、特開昭５
８−５２８７４号公報、特開昭５９−１０８３６０号公
報、特開昭５９−８９４３６号公報等に示されるよう
に、ガラス基板上に窒化シリコン（ＳｉＮz）膜を形成
することによって、上述のようなガラス基板中の不純物
イオンの影響を抑制し、トランジスタ特性の悪化を防止
していた。When various semiconductor elements such as thin film transistors are formed on a glass substrate, impurity ions in the glass substrate are diffused into the semiconductor element by cleaning, etching, heat treatment, ion implantation, plasma treatment, etc. in the manufacturing process. There was a problem that had an adverse effect. For example, in the case of a thin film transistor, there is a problem in that impurity ions are diffused into the channel layer and off current increases, which deteriorates transistor characteristics. Therefore, conventionally, for example, Japanese Patent Laid-Open No.
As described in JP-A-8-52874, JP-A-59-108360, JP-A-59-89436, etc., by forming a silicon nitride (SiN z ) film on a glass substrate, as described above. The influence of impurity ions in the transparent glass substrate is suppressed to prevent deterioration of transistor characteristics.
【０００５】[0005]
【発明が解決しようとする課題】しかし、上述のように
ガラス基板上にＳｉＮzの被膜を形成した場合にはガラ
ス基板中の不純物イオンの拡散が防止されるため、図５
に示したように、オフ電流は石英と同等の良好な特性を
得ることができるが、ガラス基板との十分な密着性を得
ることができずに素子作製に支障をきたしていた。However, when the SiN z coating film is formed on the glass substrate as described above, diffusion of impurity ions in the glass substrate is prevented, so that FIG.
As shown in, the off-current can obtain good characteristics equivalent to those of quartz, but sufficient adhesion with the glass substrate cannot be obtained, which hinders device fabrication.
【０００６】さらに、ＳｉＮzの上に直接非晶質シリコ
ン（以下ａ−Ｓｉ）を成膜し、これを熱処理することに
より多結晶シリコン（以下ｐ−Ｓｉ）を形成した場合、
ＳｉＮZ上でのシリコンの核生成速度が大きいため良質
のｐ−Ｓｉが得られないという問題が発生していた。Further, when amorphous silicon (hereinafter a-Si) is directly formed on SiN z and heat-treated to form polycrystalline silicon (hereinafter p-Si),
Since the nucleation rate of silicon on SiN Z is high, there has been a problem that good quality p-Si cannot be obtained.
【０００７】また、酸化シリコン（ＳｉＯ2）の被膜の
みを形成した場合には図５に示したようにガラスとの密
着性は十分であるが、オフ電流が大きく被膜処理を行わ
ないガラス基板に比してほとんど改善がみられなかっ
た。Further, when only a silicon oxide (SiO 2 ) film is formed, the adhesion to glass is sufficient as shown in FIG. 5, but the off current is large and the glass substrate is not processed. Little improvement was seen in comparison.
【０００８】本発明は上記のような問題点に鑑みてなさ
れたものであり、ガラス基板からの不純物の影響を抑
え、ガラス基板上に形成した被膜が剥がれ落ちることが
なく、移動度の高いトランジスタ特性を得ることを目的
とする。The present invention has been made in view of the above problems, and suppresses the influence of impurities from the glass substrate, prevents the coating film formed on the glass substrate from peeling off, and has a high mobility. The purpose is to obtain characteristics.
【０００９】[0009]
【課題を解決するための手段】上記課題を解決するため
に本発明は、絶縁性基板と該基板上に設けた被膜と、該
被膜上に順次形成された半導体層、ゲート絶縁膜、ゲー
ト電極とで構成された薄膜トランジスタとからなる半導
体素子において、前記被膜が少なくとも、窒素を含む珪
素化合物の膜と酸素を含む珪素化合物の膜とからなり、
前記酸素を含む珪素化合物の膜が基板側に形成されてい
ることを特徴とする。In order to solve the above problems, the present invention provides an insulating substrate, a film provided on the substrate, a semiconductor layer, a gate insulating film, and a gate electrode which are sequentially formed on the film. In a semiconductor element composed of a thin film transistor configured by, the coating film is composed of at least a silicon compound film containing nitrogen and a silicon compound film containing oxygen,
The film of the silicon compound containing oxygen is formed on the substrate side.
【００１０】また本発明は、前記被膜が少なくとも、窒
素を含む珪素化合物の膜と酸素を含む珪素化合物の膜と
からなり、前記酸素を含む珪素化合物からなる膜が前記
半導体層側に形成されていることを特徴とする。According to the present invention, the film comprises at least a film of a silicon compound containing nitrogen and a film of a silicon compound containing oxygen, and a film made of the silicon compound containing oxygen is formed on the semiconductor layer side. It is characterized by being
【００１１】さらに本発明は、前記被膜が少なくとも、
窒素を含む珪素化合物の膜と酸素を含む珪素化合物の膜
とからなり、前記酸素を含む珪素化合物からなる膜が前
記基板側と前記半導体層側に形成されていることを特徴
とする。Further, in the present invention, the coating film is at least
It is characterized in that a film of a silicon compound containing nitrogen and a film of a silicon compound containing oxygen are formed, and a film made of the silicon compound containing oxygen is formed on the substrate side and the semiconductor layer side.
【００１２】さらに本発明の半導体装置の製造方法で
は、絶縁性基板の少なくとも一面を、少なくとも、窒素
を含む珪素化合物からなる膜と酸素を含む珪素化合物か
らなる膜で被膜した後、該被膜上に薄膜トランジスタを
形成する際に、前記絶縁性基板上の被膜を同一成膜装置
内で連続して成膜することを特徴とする。Further, in the method for manufacturing a semiconductor device of the present invention, at least one surface of the insulating substrate is coated with at least a film made of a silicon compound containing nitrogen and a film made of a silicon compound containing oxygen, and then the film is formed on the film. When the thin film transistor is formed, the coating film on the insulating substrate is continuously formed in the same film forming apparatus.
【００１３】[0013]
【作用】本発明の半導体装置では、酸素を含む珪素化合
物の被膜が基板側に形成されているため、ガラス基板等
の絶縁性基板との密着性が良く、基板上に設けられた被
膜が、半導体装置の作製プロセスの洗浄、エッチング、
熱処理、イオン注入、プラズマ処理等によっても剥がれ
落ちる等の問題が生じることがない。また、窒素を含む
珪素化合物の被膜が酸素を含む珪素化合物とともに形成
されているため、半導体作製プロセス中に、ガラス基板
中の不純物イオンが半導体素子中へ拡散するのが防止さ
れ、ｐ−Ｓｉ薄膜トランジスタの場合には、オフ電流の
増大が抑制され、良好な特性を得ることができる。In the semiconductor device of the present invention, since the coating of the silicon compound containing oxygen is formed on the substrate side, the adhesiveness to an insulating substrate such as a glass substrate is good, and the coating provided on the substrate is Cleaning of semiconductor device manufacturing process, etching,
There is no problem such as peeling off even by heat treatment, ion implantation, plasma treatment or the like. Further, since the film of the silicon compound containing nitrogen is formed together with the silicon compound containing oxygen, impurity ions in the glass substrate are prevented from diffusing into the semiconductor element during the semiconductor manufacturing process, and the p-Si thin film transistor is formed. In the case of, the increase in off-current is suppressed, and good characteristics can be obtained.
【００１４】さらに、本発明の半導体装置では、前記被
膜の半導体層側に酸素を含む珪素化合物の膜が形成され
ているため半導体層のＳｉ結晶が大きく成長し、移動度
の高い薄膜トランジスタを得ることができる。Further, in the semiconductor device of the present invention, since the silicon compound film containing oxygen is formed on the semiconductor layer side of the film, the Si crystal of the semiconductor layer grows large and a thin film transistor with high mobility can be obtained. You can
【００１５】さらに、本発明の半導体装置の製造方法で
は、前記被膜を同一成膜装置内で連続して成膜している
ため、パーティクルが混入することがなく、良質な被膜
を効率良く形成できる。Further, in the method for manufacturing a semiconductor device of the present invention, since the film is continuously formed in the same film forming apparatus, particles are not mixed and a high quality film can be efficiently formed. ..
【００１６】[0016]
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１７】＜実施例１＞図１〜図３は本発明の一実施
例を示した図であり、図１はガラス基板の一面に被膜を
形成した状態、図２はガラス基板の全面に被膜を形成し
た状態、図３は被膜を形成したガラス基板上に半導体素
子である薄膜トランジスタを形成した状態を示した図で
ある。<Embodiment 1> FIGS. 1 to 3 are views showing an embodiment of the present invention. FIG. 1 shows a state in which a coating is formed on one surface of a glass substrate, and FIG. 2 shows a coating on the entire surface of a glass substrate. FIG. 3 is a view showing a state in which a thin film transistor, which is a semiconductor element, is formed on a glass substrate on which a film is formed.
【００１８】図においてガラス基板１上にはＳｉＮxＯy
層２、およびＳｉＮz層３からなる被膜がこの順に形成
されている。図１及び図３のガラス基板には一面にのみ
被膜が形成されているが、図２のガラス基板１には全面
に被膜が形成されている。図１及び図３に示したように
一面にのみ被膜２、３を形成した場合には成膜処理が容
易であるが、洗浄やエッチング等のプロセスにおいて被
膜していない面（裏面）からの不純物イオンの流出を考
慮する必要がある。また図２のように全面に被膜２、３
を形成した場合には、上述したような不純物イオンの流
出を防止することはできるが、２度にわけて被膜処理を
行う、ガラス基板１を立てた状態で被膜処理を行う等の
成膜処理時の工夫が必要となる。なおこの実施例ではガ
ラス基板１上にＳｉＮxＯy層２を形成し、その上にＳｉ
Ｎz層３を形成した２層の被膜の例を示しているが、こ
れらの層をさらに何層か積層することによって不純物イ
オンの流出をさらに確実に防止することができる。In the figure, SiN x O y is formed on the glass substrate 1.
A coating composed of the layer 2 and the SiN z layer 3 is formed in this order. The glass substrate of FIGS. 1 and 3 has a coating formed on only one surface thereof, whereas the glass substrate 1 of FIG. 2 has a coating formed on the entire surface. When the coatings 2 and 3 are formed on only one surface as shown in FIGS. 1 and 3, the film forming process is easy, but impurities from the surface (back surface) not coated in the process such as cleaning and etching It is necessary to consider the outflow of ions. In addition, as shown in FIG.
When the film is formed, it is possible to prevent the outflow of the impurity ions as described above, but the film forming process such as performing the film forming process in two steps or performing the film forming process in a state where the glass substrate 1 is erected. It is necessary to devise time. In this embodiment, the SiN x O y layer 2 is formed on the glass substrate 1 and the SiN x O y layer 2 is formed on the SiN x O y layer 2.
Although an example of a two-layer coating in which the N z layer 3 is formed is shown, the outflow of impurity ions can be more reliably prevented by stacking several layers of these layers.
【００１９】ガラス基板１上に被膜２、３を形成する成
膜方法としては例えば反応性スパッタ法が用いられる。
以下に反応性スパッタ法による成膜方法を説明する。As a film forming method for forming the coating films 2 and 3 on the glass substrate 1, for example, a reactive sputtering method is used.
The film forming method by the reactive sputtering method will be described below.
【００２０】まず、ガラス基板１上にＳｉＮxＯy膜２を
形成する。ＳｉＮxＯy膜２は、Ｓｉターゲットを用いて
窒素と酸素の混合ガス中でスパッタすることにより形成
する。First, the SiN x O y film 2 is formed on the glass substrate 1. The SiN x O y film 2 is formed by sputtering using a Si target in a mixed gas of nitrogen and oxygen.
【００２１】酸素の流量割合は０．１〜１０％、トータ
ル圧力は１〜２０ｍＴｏｒｒ、基板温度は１５０〜３０
０℃の条件で良好な成膜が行えた。膜圧は２００〜５０
０Å程度で密着性に関し十分な効果があった。The flow rate of oxygen is 0.1 to 10%, the total pressure is 1 to 20 mTorr, and the substrate temperature is 150 to 30.
Good film formation was possible under the condition of 0 ° C. Transmembrane pressure is 200-50
At about 0Å, there was a sufficient effect on adhesion.
【００２２】次にＳｉＮxＯy膜２上にＳｉＮz膜３を形
成する。窒素ガス中において、Ｓｉをターゲットとして
スパッタすることによりＳｉＮxＯy層２上にＳｉＮz膜
３が形成される。ガス圧は１〜２０ｍＴｏｒｒ、基板温
度は１５０〜３００℃の条件で良好な成膜が行えた。膜
厚は、５００〜３０００Å程度で、不純物の抑制に関し
十分な効果があった。Next, the SiN z film 3 is formed on the SiN x O y film 2. The SiN z film 3 is formed on the SiN x O y layer 2 by sputtering with Si as a target in nitrogen gas. Good film formation was possible under the conditions of a gas pressure of 1 to 20 mTorr and a substrate temperature of 150 to 300 ° C. The film thickness was about 500 to 3000 Å, which was sufficiently effective in suppressing impurities.
【００２３】上記のようにしてＳｉＮxＯy膜２、ＳｉＮ
z膜３が形成されるが、この成膜時において、流入ガス
中にアルゴン等の不活性ガスを混入させてもよく、ま
た、ＳｉＮxＯy膜２、ＳｉＮz膜３は同一装置内で連続
して成膜することにより、より効率良く、良質な成膜を
行うことができる、またこの実施例では反応性スパッタ
法を用いたが、ＣＶＤ法によってもＳｉＮxＯy，ＳｉＮ
z膜を形成することは可能である。As described above, the SiN x O y film 2 and SiN
Although the z film 3 is formed, an inert gas such as argon may be mixed into the inflowing gas at the time of this film formation, and the SiN x O y film 2 and the SiN z film 3 are formed in the same apparatus. By forming the films continuously, it is possible to perform the film formation more efficiently and with good quality. Further, although the reactive sputtering method was used in this embodiment, the SiN x O y , SiN can also be formed by the CVD method.
It is possible to form a z- film.
【００２４】ＳｉＮxＯy膜２、ＳｉＮz膜３によって被
覆されたガラス基板１上にはトランジスタ素子（半導体
素子）が形成される。トランジスタ素子の形成処理を図
３を参照して説明する。A transistor element (semiconductor element) is formed on the glass substrate 1 covered with the SiN x O y film 2 and the SiN z film 3. The process of forming the transistor element will be described with reference to FIG.
【００２５】まず、ＳｉＮz膜３上に、トランジスタ素
子のチャンネル層となるｐ−Ｓｉ膜４を形成後、トラン
ジスタサイズにパターニングし、ゲート絶縁膜５を成膜
する。ゲート絶縁膜５には例えばＳｉＯ2が用いられる
が、他の絶縁膜であっても構わない。次にゲート膜を成
膜し、パターニングしてゲート部６を形成する。ゲート
膜としては例えばｐ−Ｓｉ膜が用いられるが、最終的に
導電性膜であれば他の材料であっても構わない。さら
に、ソース、ドレイン部７、８と引き出し電極とのオー
ミック接触をとるためのコンタクトホールを形成後、引
き出し電極１０を形成する。最後に、ｐ−Ｓｉ膜４の結
晶粒界のダングリングボンドをターミネートするため
に、水素化処理を行う。First, a p-Si film 4 to be a channel layer of a transistor element is formed on the SiN z film 3 and then patterned into a transistor size to form a gate insulating film 5. For example, SiO 2 is used for the gate insulating film 5, but another insulating film may be used. Next, a gate film is formed and patterned to form the gate portion 6. As the gate film, for example, a p-Si film is used, but other materials may be used as long as they are finally conductive films. Further, after forming contact holes for making ohmic contact between the source / drain portions 7 and 8 and the extraction electrode, the extraction electrode 10 is formed. Finally, in order to terminate the dangling bond at the crystal grain boundary of the p-Si film 4, a hydrogenation process is performed.
【００２６】以上のようにして作製したｐ−Ｓｉトラン
ジスタのオフ電流特性は、石英基板やＳｉＮz被覆ガラ
スのオフ電流レベル（〜１０-11Ａ）と同等であり、ガ
ラス基板からの不純物が抑制できたことが分かる。ま
た、ＳｉＮxＯy膜を設けたことにより、ＳｉＮzの単層
膜に比べて密着性は良好になり、トランジスタ素子作製
の全工程に耐え得るガラスとの十分な密着性が得られ
た。また、ＳｉＮz膜により、ガラス基板１中の不純物
イオンが薄膜トランジスタ素子（半導体素子）中に拡散
されるのを防止することができた。The off-current characteristics of the p-Si transistor manufactured as described above are equivalent to the off-current level (-10 -11 A) of a quartz substrate or SiN z coated glass, and impurities from the glass substrate are suppressed. You can see that it was done. Further, by providing the SiN x O y film, the adhesiveness becomes better than that of the SiN z single-layer film, and sufficient adhesiveness with glass that can withstand all the steps of manufacturing a transistor element was obtained. In addition, the SiN z film could prevent the impurity ions in the glass substrate 1 from diffusing into the thin film transistor element (semiconductor element).
【００２７】＜実施例２＞図４は本発明の他の実施例で
あり、半導体装置の断面構成図である。この実施例にお
いて、トランジスタ素子部分は図３の構成と同様であ
り、同一番号で示し説明を省略する。<Embodiment 2> FIG. 4 shows another embodiment of the present invention and is a sectional view of a semiconductor device. In this embodiment, the transistor element portion has the same structure as that of FIG.
【００２８】ガラス基板１上には被膜１２が形成されて
いる。この被膜１２の組成はＳｉＮxＯyであり、ｙの値
がガラス基板との境界部から上方にかけて２から０まで
変化している。被膜１２は例えば反応性スパッタ法によ
り成膜される。以下、その成膜条件を示す。A coating 12 is formed on the glass substrate 1. The composition of the coating film 12 is SiN x O y , and the value of y changes from 2 to 0 from the boundary with the glass substrate to the upper side. The coating film 12 is formed by, for example, a reactive sputtering method. The film forming conditions are shown below.
【００２９】ＳｉＮxＯy膜はＳｉターゲットを用いて窒
素と酸素の混合ガス中でスパッタすることにより形成す
る。成膜初期時に酸素の流量割合を１００〜１０％で行
い、成膜進行に伴い酸素の流量割合を０％に落とし、酸
素の流量割合０％で一定膜成膜する。このような条件で
成膜することによりｙの値を２から０まで連続的に変化
させたＳｉＮxＯy膜が形成できる。また、トータル圧力
は１〜２０ｍＴｏｒｒ、基板温度は１５０〜３００℃の
条件で良好な成膜が行えた。膜厚は５００〜３０００Å
程度で、密着性及び不純物制御に関し十分な効果があっ
た。なお、本実施例では窒素と酸素の混合ガスで成膜し
たが、アルゴン等の不活性ガスをさらに混合して成膜し
ても構わない。また、本実施例では反応性スパッタ法を
用いたが、ＣＶＤ法により成膜してもよい。なおｙの値
を２から０まで連続的に変化させたＳｉＮxＯy膜は上記
のように同一装置内で連続して成膜することにより、よ
り効率良く良質な膜が成膜できる。The SiN x O y film is formed by sputtering using a Si target in a mixed gas of nitrogen and oxygen. The flow rate of oxygen is set to 100 to 10% at the initial stage of film formation, the flow rate of oxygen is reduced to 0% as the film formation progresses, and a constant film is formed at a flow rate of 0% of oxygen. By forming a film under such conditions, a SiN x O y film in which the value of y is continuously changed from 2 to 0 can be formed. Also, good film formation could be performed under the conditions of a total pressure of 1 to 20 mTorr and a substrate temperature of 150 to 300 ° C. Film thickness is 500-3000Å
However, there was a sufficient effect on the adhesion and the control of impurities. In addition, in this embodiment, the film formation is performed by using a mixed gas of nitrogen and oxygen, but the film formation may be performed by further mixing an inert gas such as argon. Although the reactive sputtering method is used in this embodiment, the film may be formed by the CVD method. The SiN x O y film in which the value of y is continuously changed from 2 to 0 can be formed efficiently and with good quality by continuously forming the film in the same apparatus as described above.
【００３０】このようにして成膜された被膜１２はガラ
ス基板面においては、ｙの値が２程度のＳｉＮxＯyが形
成されているため基板に対して十分な密着性を有し、半
導体装置の形成プロセスにおける洗浄、エッチング、熱
処理、イオン注入、プラズマ処理等によっても剥がれ落
ちることがなかった。また、ｙの値が０のＳｉＮxＯy膜
が一定膜厚形成されているため、ガラス基板１から半導
体素子（トランジスタ素子）への不純物の拡散が抑制さ
れた。なおこの実施例ではＳｉＮxＯy膜をガラス基板の
片面にのみ形成しているが、全面に形成してもよい。The coating 12 thus formed has sufficient adhesion to the substrate because SiN x O y having a y value of about 2 is formed on the glass substrate surface. It did not peel off even by cleaning, etching, heat treatment, ion implantation, plasma treatment, etc. in the device forming process. Further, since the SiN x O y film having a y value of 0 is formed to have a constant film thickness, diffusion of impurities from the glass substrate 1 to the semiconductor element (transistor element) was suppressed. Although the SiN x O y film is formed only on one surface of the glass substrate in this embodiment, it may be formed on the entire surface.
【００３１】＜実施例３＞図６は本発明のさらに他の実
施例であり、断面構成図である。<Third Embodiment> FIG. 6 is a sectional view showing the structure of a third embodiment of the present invention.
【００３２】ガラス基板１上にはＳｉＮxＯy膜１３、Ｓ
ｉＮ膜１４、ＳｉＯ2膜１５が形成されている。これら
の被膜は例えば反応性スパッタ法により成膜される。以
下、その成膜条件を示す。On the glass substrate 1, the SiN x O y film 13, S
An iN film 14 and a SiO 2 film 15 are formed. These coatings are formed by, for example, the reactive sputtering method. The film forming conditions are shown below.
【００３３】まず、ガラス基板１上に、ＳｉＮxＯy膜１
３を形成する。ＳｉＮxＯy膜１３は、Ｓｉターゲットに
よる反応性スパッタ法において基板温度２００℃、ＲＦ
Ｐｏｗｅｒ７５０Ｗ、ガス圧力１２ｍＴｏｒｒ、Ｎ2
ガス流量５０ｓｃｃｍ、Ｏ2ガス流量５ｓｃｃｍ以下に
て６００Å成膜する。次いで、同一チャンバー内で連続
して、Ｏ2ガスを流さない以外は、成膜条件を変えずに
ＳｉＮz膜１４を２４００Å成膜する。さらに、同一チ
ャンバー内でターゲットをＳｉＯ2に変え、基板温度２
００℃、ＲＦ Ｐｏｗｅｒ７５０Ｗ、ガス圧力５ｍＴｏ
ｒｒ，Ａｒガス流量７０ｓｃｃｍ、Ｏ2ガス流量３０ｓ
ｃｃｍにてＳｉＯ2膜１５を約５００Å成膜する。First, the SiN x O y film 1 is formed on the glass substrate 1.
3 is formed. The SiN x O y film 13 is formed by reactive sputtering using a Si target at a substrate temperature of 200 ° C. and RF
Power 750W, gas pressure 12mTorr, N 2
A 600Å film is formed at a gas flow rate of 50 sccm and an O 2 gas flow rate of 5 sccm or less. Then, the SiN z film 14 is continuously formed in the same chamber by 2400 Å without changing the film forming conditions except that the O 2 gas is not supplied. Furthermore, the target was changed to SiO 2 in the same chamber, and the substrate temperature was changed to 2
00 ℃, RF Power750W, gas pressure 5mTo
rr, Ar gas flow rate 70 sccm, O 2 gas flow rate 30 s
A SiO 2 film 15 of about 500 Å is formed at ccm.
【００３４】次に、プラズマＣＶＤ装置にてａ−Ｓｉ膜
を約１０００Å成膜し、これを炉アニールすることによ
りｐ−Ｓｉ膜とする。この後ｐ−Ｓｉ膜４を所定の形状
とするためのレジストパターンを形成し、エッチングを
行う。この後、ゲート絶縁膜５をスパッタ装置にて約１
０００Å成膜する。次に、ゲート電極６となるｐ−Ｓｉ
膜を減圧ＣＶＤ装置にて約２０００Å成膜し、この上に
ゲート電極６を所定の形状に加工するためのレジストパ
ターンを形成し、反応性イオンエッチャーにてエッチン
グを行う。この後、全面にＰ+をイオン注入し、活性化
アニールを行うことによりゲート電極６の低抵抗化及び
ソース、ドレイン領域７、８の活性化及び低抵抗化を行
う。さらに、常圧ＣＶＤ装置にてＳｉＯ2膜を約５００
０Å成膜し、一部にコンタクトホールを形成し、層間絶
縁膜９とする。このとき、ソース、ドレイン領域７、８
と後に形成するＡｌ電極１０が接続されるように同時に
ゲート絶縁膜５にもホールを開ける。続いて、スパッタ
装置によりＡｌを約１μｍ成膜し、所定の形状に加工し
てＡｌ電極１０を形成した。Next, an a-Si film of about 1000 liters is formed by a plasma CVD apparatus, and this is annealed in a furnace to form a p-Si film. After that, a resist pattern for forming the p-Si film 4 into a predetermined shape is formed and etching is performed. After that, the gate insulating film 5 is sputtered to about 1
000Å Deposition. Next, p-Si which becomes the gate electrode 6
A film is formed to a thickness of about 2000Å by a low pressure CVD apparatus, a resist pattern for forming the gate electrode 6 into a predetermined shape is formed thereon, and etching is performed by a reactive ion etcher. After that, P + ions are implanted into the entire surface, and activation annealing is performed to reduce the resistance of the gate electrode 6 and activate and reduce the resistance of the source / drain regions 7 and 8. Furthermore, the SiO 2 film is removed to about 500 by an atmospheric pressure CVD device.
A 0Å film is formed and a contact hole is formed in a part thereof to form an interlayer insulating film 9. At this time, the source and drain regions 7 and 8
At the same time, a hole is opened in the gate insulating film 5 so that the Al electrode 10 to be formed later is connected. Subsequently, a film of Al having a thickness of about 1 μm was formed by a sputtering apparatus and processed into a predetermined shape to form an Al electrode 10.
【００３５】表１は本実施例におけるＳｉＮxＯy膜１３
の成膜条件のうちＯ2ガス流量を変化させた時のトラン
ジスタ作製プロセスにおける膜の剥離の有無を示したも
のである。表１よりＯ2ガス流量が１０ｓｃｃｍを超え
ると膜の組成がＳｉＯ2に近くなり密着性が低下するこ
とが分かる。また、Ｏ2流量が少なすぎると基板との剥
離が発生する。Table 1 shows the SiN x O y film 13 in this embodiment.
Among the film forming conditions, the presence or absence of film peeling in the transistor manufacturing process when the O 2 gas flow rate is changed is shown. From Table 1, it can be seen that when the O 2 gas flow rate exceeds 10 sccm, the composition of the film becomes close to that of SiO 2 and the adhesiveness deteriorates. If the O 2 flow rate is too low, peeling from the substrate will occur.
【００３６】[0036]
【表１】 [Table 1]
【００３７】また、表２は本実施例におけるＳｉＮxＯy
膜１３の膜厚を変えたときのトランジスタ作製プロセス
における被膜の剥離の有無を示したものである。表２よ
りＳｉＮxＯy膜１３の膜厚が３００Å以下の時に剥離を
起こすことがわかる。Table 2 shows SiN x O y in this example.
It shows the presence or absence of peeling of the film in the transistor manufacturing process when the film thickness of the film 13 is changed. Table 2 shows that peeling occurs when the film thickness of the SiN x O y film 13 is 300 Å or less.
【００３８】[0038]
【表２】 [Table 2]
【００３９】なお、本実施例においては基板と活性層と
の間に積層する３層の膜をスパッタ装置により成膜する
際に、ＳｉＮxＯy膜１３およびＳｉＮz膜１４をＳｉタ
ーゲットにてＳｉＯ2膜１５をＳｉＯ2ターゲットにて成
膜したがこれにこだわるものではない。成膜方法はスパ
ッタ法以外にＣＶＤ法によって成膜を行ってもよい。な
お、成膜条件によってはＳｉＮxＯyが必要でない場合も
ある。In this embodiment, the SiN x O y film 13 and the SiN z film 14 are Si targets when a three-layer film laminated between the substrate and the active layer is formed by a sputtering apparatus. The SiO 2 film 15 was formed using a SiO 2 target, but the present invention is not limited to this. As the film forming method, a CVD method may be used instead of the sputtering method. Depending on the film forming conditions, SiN x O y may not be necessary.
【００４０】本実施例によると、ガラス基板上に薄膜ト
ランジスタを作製する場合にも素子部への不純物の拡散
が押えられ、尚かつａ−Ｓｉ膜を熱処理することにより
ｐ−Ｓｉ膜を得る方法においても良質のｐ−Ｓｉ膜を得
ることが出来る。また、基板とＳｉＮz膜との間にＳｉ
ＮxＯy膜を積層しているためＳｉＮz膜の剥離の問題も
解決される。さらに、これらの膜を同一チャンバー内で
連続して成膜しているためパーティクル等の不純物の混
入を防止することができる。According to the present embodiment, even when a thin film transistor is manufactured on a glass substrate, diffusion of impurities to the element portion is suppressed, and a p-Si film is obtained by heat-treating the a-Si film. Also makes it possible to obtain a good quality p-Si film. In addition, Si is formed between the substrate and the SiN z film.
Since the N x O y films are laminated, the problem of peeling of the SiN z film can be solved. Furthermore, since these films are continuously formed in the same chamber, it is possible to prevent impurities such as particles from being mixed.
【００４１】[0041]
【発明の効果】本発明によれば、酸素を含む珪素化合物
の被膜が基板側に形成されているため、ガラス基板等の
絶縁性基板との密着性が良く、基板上に設けられた被膜
が、半導体装置の作製プロセス中に剥がれ落ちる等の問
題が生じることがない。According to the present invention, since the film of the silicon compound containing oxygen is formed on the substrate side, the film has good adhesion to an insulating substrate such as a glass substrate and the film provided on the substrate is excellent. Further, there is no problem such as peeling off during the manufacturing process of the semiconductor device.
【００４２】また、窒素を含む珪素化合物の膜が酸素を
含む珪素化合物とともに形成されているため、半導体作
製プロセス中に、ガラス基板中の不純物イオンが半導体
素子中へ拡散するのが防止され、ｐ−Ｓｉ薄膜トランジ
スタの場合には、オフ電流の増大が抑制され、良好な特
性を得ることができる。Further, since the silicon compound film containing nitrogen is formed together with the silicon compound containing oxygen, impurity ions in the glass substrate are prevented from diffusing into the semiconductor element during the semiconductor manufacturing process. In the case of a -Si thin film transistor, an increase in off current is suppressed, and good characteristics can be obtained.
【００４３】さらに、本発明によれば、前記被膜の半導
体層側に酸素を含む珪素化合物の被膜が形成されている
ため半導体層のＳｉ結晶が大きく成長し、移動度の高い
薄膜トランジスタを得ることができる。Further, according to the present invention, since a film of a silicon compound containing oxygen is formed on the semiconductor layer side of the film, Si crystal of the semiconductor layer grows large and a thin film transistor having high mobility can be obtained. it can.
【００４４】さらに、本発明の半導体装置の製造方法で
は、前記被膜を同一成膜装置内で連続して成膜している
ため、パーティクルが混入することがなく、良質な絶縁
体を効率良く形成できる。Further, in the method for manufacturing a semiconductor device of the present invention, since the film is continuously formed in the same film forming apparatus, particles are not mixed and a high-quality insulator is efficiently formed. it can.
【図１】本発明の一実施例であり、一面に絶縁体を形成
したガラス基板の断面図FIG. 1 is a cross-sectional view of a glass substrate which is an embodiment of the present invention and has an insulator formed on one surface thereof.
【図２】本発明の一実施例であり、全面に絶縁体を形成
したガラス基板の断面図FIG. 2 is a cross-sectional view of a glass substrate that is an embodiment of the present invention and has an insulator formed on the entire surface.
【図３】図１のガラス基板により形成された、実施例１
に係る半導体装置の構成を示した断面図FIG. 3 is a first example formed of the glass substrate of FIG.
Sectional view showing the configuration of the semiconductor device according to the present invention.
【図４】本発明の一実施例であり、実施例２に係る半導
体装置の構成を示した断面図FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment, which is an embodiment of the present invention.
【図５】従来の半導体装置の問題点を説明するための説
明図FIG. 5 is an explanatory diagram for explaining problems of the conventional semiconductor device.
【図６】本発明の一実施例であり、実施例３に係る半導
体装置の構成を示した断面図FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention.
１ ガラス基板 ２ ＳｉＮxＯy膜 ３ ＳｉＮz膜 １２ ＳｉＮxＯy膜（０≦ｙ≦２） １３ ＳｉＮxＯy膜（ｙ≠０） １４ ＳｉＮz膜（ｚ≠０） １５ ＳｉＯ2膜1 Glass substrate 2 SiN x O y film 3 SiN z film 12 SiN x O y film (0 ≦ y ≦ 2) 13 SiN x O y film (y ≠ 0) 14 SiN z film (z ≠ 0) 15 SiO 2 film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 土本 修平 大阪府大阪市阿倍野区長池町22番22号 シ ヤープ株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuhei Tsuchimoto 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation
Claims (8)
該被膜上に順次形成された半導体層、ゲート絶縁膜、ゲ
ート電極で構成される薄膜トランジスタとからなる半導
体素子において、 前記被膜が少なくとも、窒素を含む珪素化合物の膜と酸
素を含む珪素化合物の膜とからなり、前記酸素を含む珪
素化合物の膜が基板側に形成されていることを特徴とす
る半導体素子。1. An insulating substrate and a coating film provided on the substrate,
A semiconductor element comprising a thin film transistor including a semiconductor layer, a gate insulating film, and a gate electrode sequentially formed on the film, wherein the film includes at least a silicon compound film containing nitrogen and a silicon compound film containing oxygen. And a film of the silicon compound containing oxygen is formed on the substrate side.
Ｏy膜（ｙ≠０）と、半導体層側に形成されたＳｉＮZ膜
（Ｚ≠０）とからなることを特徴とする請求項１記載の
半導体素子。2. The SiN x having the film formed on the substrate side.
The semiconductor element according to claim 1, comprising an O y film (y ≠ 0) and a SiN Z film (Z ≠ 0) formed on the semiconductor layer side.
からｙの値が０以上２以下に連続的に変化していること
を特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the coating film is SiN x O y , and the value of y continuously changes from 0 to 2 from the substrate side.
該被膜上に順次形成された半導体層、ゲート絶縁膜、ゲ
ート電極で構成された薄膜トランジスタとからなる半導
体素子において、前記被膜が少なくとも、窒素を含む珪
素化合物の膜と酸素を含む珪素化合物の膜とからなり、
前記酸素を含む珪素化合物からなる膜が前記半導体層側
に形成されていることを特徴とする半導体素子。4. An insulating substrate and a coating provided on the substrate,
A semiconductor element comprising a semiconductor layer sequentially formed on the film, a gate insulating film, and a thin film transistor composed of a gate electrode, wherein the film contains at least a silicon compound film containing nitrogen and a silicon compound film containing oxygen. Consists of
A semiconductor element, wherein a film made of the silicon compound containing oxygen is formed on the semiconductor layer side.
膜（Ｚ≠０）と半導体層側に形成されたＳｉＯ2膜とか
らなることを特徴とする請求項４記載の半導体素子。5. The SiN Z having the film formed on the substrate side.
The semiconductor element according to claim 4, comprising a film (Z ≠ 0) and a SiO 2 film formed on the semiconductor layer side.
該被膜上に順次形成された半導体層、ゲート絶縁膜、ゲ
ート電極で構成された薄膜トランジスタとからなる半導
体素子において、 前記被膜が少なくとも、窒素を含む珪素化合物の膜と酸
素を含む珪素化合物の膜とからなり、前記酸素を含む珪
素化合物からなる膜が前記基板側と前記半導体層側に形
成されていることを特徴とする半導体素子。6. An insulating substrate and a coating provided on the substrate,
A semiconductor element comprising a semiconductor layer sequentially formed on the film, a gate insulating film, and a thin film transistor composed of a gate electrode, wherein the film comprises at least a silicon compound film containing nitrogen and a silicon compound film containing oxygen. And a film made of the silicon compound containing oxygen is formed on the substrate side and the semiconductor layer side.
Ｏy膜（ｙ≠０）と該ＳｉＮxＯy膜上に形成されたＳｉ
ＮZ膜（Ｚ≠０）と半導体層側に形成されたＳｉＯ2膜と
からなることを特徴とする請求項６記載の半導体素子。7. The SiN x having the film formed on the substrate side.
O y film (y ≠ 0) and Si formed on the SiN x O y film
7. The semiconductor device according to claim 6, comprising an N Z film (Z ≠ 0) and a SiO 2 film formed on the semiconductor layer side.
とも、窒素を含む珪素化合物からなる膜と酸素を含む珪
素化合物からなる膜で被膜した後、該被膜上に薄膜トラ
ンジスタを形成する半導体素子の製造方法であって、前
記絶縁性基板上の被膜を同一成膜装置内で連続して成膜
することを特徴とする半導体素子の製造方法。8. A method of manufacturing a semiconductor device, comprising forming at least one surface of an insulating substrate with at least a film made of a silicon compound containing nitrogen and a film made of a silicon compound containing oxygen, and then forming a thin film transistor on the film. A method of manufacturing a semiconductor element, wherein the coating film on the insulating substrate is continuously formed in the same film forming apparatus.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8368892A JP2834928B2 (en) | 1991-09-10 | 1992-04-06 | Semiconductor element |
| DE69229314T DE69229314T2 (en) | 1991-09-10 | 1992-09-10 | Semiconductor device and manufacturing method |
| EP92308227A EP0532314B1 (en) | 1991-09-10 | 1992-09-10 | A semiconductor device and a process for fabricating same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23056191 | 1991-09-10 | ||
| JP3-230561 | 1991-09-10 | ||
| JP8368892A JP2834928B2 (en) | 1991-09-10 | 1992-04-06 | Semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05129609A true JPH05129609A (en) | 1993-05-25 |
| JP2834928B2 JP2834928B2 (en) | 1998-12-14 |
Family
ID=26424723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8368892A Expired - Lifetime JP2834928B2 (en) | 1991-09-10 | 1992-04-06 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2834928B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000216403A (en) * | 1994-07-30 | 2000-08-04 | Semiconductor Energy Lab Co Ltd | Active matrix circuit |
| JP2006040881A (en) * | 2004-06-25 | 2006-02-09 | Semiconductor Energy Lab Co Ltd | Display device |
| US7271082B2 (en) | 1993-10-26 | 2007-09-18 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| JP2009065187A (en) * | 2008-10-29 | 2009-03-26 | Semiconductor Energy Lab Co Ltd | Manufacturing method of semiconductor device |
| JP2010028137A (en) * | 2009-10-30 | 2010-02-04 | Semiconductor Energy Lab Co Ltd | Method of forming single crystal silicon thin film on glass substrate |
-
1992
- 1992-04-06 JP JP8368892A patent/JP2834928B2/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7271082B2 (en) | 1993-10-26 | 2007-09-18 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US7452794B2 (en) | 1993-10-26 | 2008-11-18 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of a thin film semiconductor device |
| US7691692B2 (en) | 1993-10-26 | 2010-04-06 | Semiconductor Energy Laboratory Co., Ltd. | Substrate processing apparatus and a manufacturing method of a thin film semiconductor device |
| US8304350B2 (en) | 1993-10-26 | 2012-11-06 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| JP2000216403A (en) * | 1994-07-30 | 2000-08-04 | Semiconductor Energy Lab Co Ltd | Active matrix circuit |
| JP2006040881A (en) * | 2004-06-25 | 2006-02-09 | Semiconductor Energy Lab Co Ltd | Display device |
| JP2009065187A (en) * | 2008-10-29 | 2009-03-26 | Semiconductor Energy Lab Co Ltd | Manufacturing method of semiconductor device |
| JP4489823B2 (en) * | 2008-10-29 | 2010-06-23 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP2010028137A (en) * | 2009-10-30 | 2010-02-04 | Semiconductor Energy Lab Co Ltd | Method of forming single crystal silicon thin film on glass substrate |
| JP4642130B2 (en) * | 2009-10-30 | 2011-03-02 | 株式会社半導体エネルギー研究所 | Method for forming single crystal silicon thin film on glass substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2834928B2 (en) | 1998-12-14 |
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