JPH05129536A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH05129536A JPH05129536A JP3287614A JP28761491A JPH05129536A JP H05129536 A JPH05129536 A JP H05129536A JP 3287614 A JP3287614 A JP 3287614A JP 28761491 A JP28761491 A JP 28761491A JP H05129536 A JPH05129536 A JP H05129536A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- region
- insulating layer
- semiconductor substrate
- buried insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、バイポーラ型半導体
素子とＭＯＳ型半導体素子とを備えた半導体装置に関
し、特にＳＯＩ構造と溝型分離領域とを備えた半導体装
置及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bipolar semiconductor element and a MOS semiconductor element, and more particularly to a semiconductor device having an SOI structure and a trench isolation region and a method of manufacturing the same. ..
【０００２】[0002]
【従来の技術】ＳＯＩ（Silicon On Insulator）技術と
は、例えば、シリコン半導体基板中に酸素イオンを高エ
ネルギーで打ち込み高温の熱処理を加えることによって
酸素イオンとシリコン原子を結合させて酸化膜の埋設絶
縁層を基板中に形成するＳＩＭＯＸ（Seperation by IM
planted OXygen）法などに代表される、絶縁層（Insula
tor ）の上（On）にシリコン層（Silicon ）を形成する
技術の総称である。2. Description of the Related Art The SOI (Silicon On Insulator) technology is, for example, a method of implanting oxygen ions in a silicon semiconductor substrate with high energy and applying a high-temperature heat treatment to bond the oxygen ions and silicon atoms to each other, thereby embedding an oxide film in a buried insulating film SIMOX (Seperation by IM) that forms a layer in the substrate
Insula (Insula) represented by planted OXygen method
It is a general term for the technology of forming a silicon layer (Silicon) on (tor).
【０００３】ＭＯＳ（Metal-Oxside-Semiconductor）型
半導体素子においては、素子の動作の中心となるのはゲ
ート絶縁膜直下の半導体層（ウェル領域）の表面（また
は表面付近）に形成されるキャリアの通り道（チャネ
ル）であり、その下のチャネルの形成されないウェル部
分や、チャネルからの電極取り出し領域であソース（あ
るいはドレイン）領域とウェルとのダイオード接合は寄
生素子を形成し、素子動作を劣化させることになる。In a MOS (Metal-Oxside-Semiconductor) type semiconductor element, the center of operation of the element is the carrier formed on the surface (or near the surface) of the semiconductor layer (well region) immediately below the gate insulating film. It is a passage (channel) and the well portion below which the channel is not formed, or the diode junction between the source (or drain) region and the well in the electrode extraction region from the channel forms a parasitic element and deteriorates the element operation. It will be.
【０００４】ＭＯＳ型素子にＳＯＩ技術を適用して絶縁
層上に形成した非常に浅いシリコン層（〜０．１μｍ程
度）に素子を形成することにより、上記のような素子動
作に寄与しないウェル領域を極力減らす事ができるこ
と、ゲート下のウェル領域が狭いためにゲートによるキ
ャリア電荷の制御性が向上すること、ソース（ドレイ
ン）とウェルとの接合容量を大幅に減少させることがで
きること、さらに相補型ＭＯＳデバイスではＰチャネル
素子を形成するＮウェルとＮチャネル素子を形成するＰ
ウェルが完全に分離されるため、ラッチアップに対する
耐性が非常に高くなることなどの利点から、近年、研究
・開発が盛んに行われてきている。By applying the SOI technique to a MOS type element to form the element in a very shallow silicon layer (about 0.1 μm) formed on an insulating layer, a well region which does not contribute to the above element operation is formed. Can be reduced as much as possible, the controllability of carrier charge by the gate is improved because the well region under the gate is narrow, the junction capacitance between the source (drain) and the well can be significantly reduced, and the complementary type In a MOS device, an N well forming a P channel element and a P well forming an N channel element
Since the wells are completely separated, the resistance to latch-up becomes extremely high, and thus research and development have been actively conducted in recent years.
【０００５】この場合の一例として、ＳＩＭＯＸ法を適
用したＰチャネル型ＭＯＳトランジスタの製造方法にお
ける主要工程の断面図を図８乃至図１１に示す。図８乃
至図１１において、１はＮ- 型シリコン基板、２は酸化
膜絶縁層、３はシリコン層、４は素子分離用酸化膜、５
はゲート絶縁膜、６はゲート電極、７及び８はソース及
びドレイン領域、９は絶縁膜、１０はソース電極用配
線、１１はゲート電極用配線、１２はドレイン電極用配
線である。As an example of this case, FIGS. 8 to 11 are sectional views showing main steps in a method of manufacturing a P-channel type MOS transistor to which the SIMOX method is applied. 8 to 11, 1 is an N − -type silicon substrate, 2 is an oxide film insulating layer, 3 is a silicon layer, 4 is an element isolation oxide film, 5
Is a gate insulating film, 6 is a gate electrode, 7 and 8 are source and drain regions, 9 is an insulating film, 10 is a source electrode wiring, 11 is a gate electrode wiring, and 12 is a drain electrode wiring.
【０００６】まず、図８に示すように、Ｎ- 型シリコン
基板１全面に、イオン注入法により酸素イオンをシリコ
ン酸化膜（ＳｉＯ2 ）を形成するに十分な量を打ち込
み、高温の熱処理を加えることによりＮ- 型シリコン基
板１のシリコン原子と酸素原子を結合させ、Ｎ- 型シリ
コン基板１中に酸化膜絶縁層２を、表面に０．１μｍ程
度以下のシリコン層３が形成されるように形成する。First, as shown in FIG. 8, oxygen ions are implanted into the entire surface of the N − type silicon substrate 1 by an ion implantation method in an amount sufficient to form a silicon oxide film (SiO 2 ), and a high temperature heat treatment is applied. As a result, the silicon atoms and oxygen atoms of the N − type silicon substrate 1 are bonded to each other, so that the oxide film insulating layer 2 is formed in the N − type silicon substrate 1 and the silicon layer 3 of about 0.1 μm or less is formed on the surface. Form.
【０００７】次に、図９に示すように、素子形成領域以
外の領域には素子分離としてシリコン層３表面に公知の
ＬＯＣＯＳ分離法により分離用酸化膜４を形成し、素子
形成領域であるシリコン層３の表面を酸化してゲート絶
縁膜５を形成し、その後、基板全面にゲート電極材料
（例えば高不純物濃度の多結晶シリコン）を推積、公知
のリソグラフィ技術によりゲート電極のパターンをゲー
ト電極材料上に形成し、エッチング技術によりゲート電
極６を形成する。Next, as shown in FIG. 9, an isolation oxide film 4 is formed on the surface of the silicon layer 3 as an element isolation by a known LOCOS isolation method in an area other than the element formation area, and silicon for the element formation area is formed. The surface of the layer 3 is oxidized to form the gate insulating film 5, and then a gate electrode material (for example, polycrystalline silicon having a high impurity concentration) is deposited on the entire surface of the substrate, and the gate electrode pattern is formed by a known lithography technique. It is formed on the material and the gate electrode 6 is formed by an etching technique.
【０００８】次に、図１０に示すように、ゲート電極６
及び素子分離用酸化膜４を注入マスクとしてイオン注入
法により不純物を導入することにより自己整合的にソー
ス領域７及びドレイン領域８を形成する。これにより、
ゲート直下のシリコン層３はＭＯＳトランジスタのウェ
ルとなる。Next, as shown in FIG. 10, the gate electrode 6
Further, the source region 7 and the drain region 8 are formed in a self-aligned manner by introducing impurities by ion implantation using the element isolation oxide film 4 as an implantation mask. This allows
The silicon layer 3 immediately below the gate becomes the well of the MOS transistor.
【０００９】次に、図１１に示すように、全面を絶縁膜
９で覆った後、ソース電極用配線１０、ゲート電極用配
線１１、ドレイン電極用配線１２を形成して素子が完成
する。Next, as shown in FIG. 11, after covering the entire surface with the insulating film 9, the source electrode wiring 10, the gate electrode wiring 11, and the drain electrode wiring 12 are formed to complete the element.
【００１０】従来より、ＭＯＳ型素子を用いたデバイス
では、素子間の電気的分離を行う方法として、一般にシ
リコン基板表面を選択的に酸化して酸化膜を形成するＬ
ＯＣＯＳ法による分離が用いられており、その酸化膜厚
さは数千オングストローム程度必要であるが、ＳＯＩ構
造を適用すると酸化膜の厚さはシリコン層（〜０．１μ
ｍ）の厚さ分を酸化すれば素子全体を分離することがで
きるので製造時間が短縮でき、また酸化膜厚が薄くなる
ことにより酸化膜の素子形成領域への食い込み（バーズ
ビーク）や酸化膜周辺での酸化膜段差（バーズヘッド）
が減るため集積度を上げられるという利点がある。Conventionally, in a device using a MOS type element, as a method of electrically separating elements, generally, the surface of a silicon substrate is selectively oxidized to form an oxide film.
Separation by the OCOS method is used, and its oxide film thickness needs to be about several thousand angstroms. However, when the SOI structure is applied, the oxide film has a silicon layer thickness (up to 0.1 μm).
Since the entire device can be separated by oxidizing the thickness of m), the manufacturing time can be shortened, and the thin oxide film can cause the oxide film to bite into the device formation region (bird's beak) and the periphery of the oxide film. Oxide film step (birds head)
The advantage is that the degree of integration can be increased since
【００１１】一方、バイポーラ（Bipolar ）型素子にお
いても、ＳＯＩ技術の適用が研究されてきている。バイ
ポーラ素子に適用した場合の利点としては、主にコレク
タ領域と基板との接合によって形成される寄生ダイオー
ド、特にその大きな接合容量を低減できるところにあ
る。近年、ベース、エミッタ領域の形成方法がリソグラ
フィにおけるパターニング用マスクがいらない自己接合
プロセスになってきており、これら寄生容量は小さくな
ってきて全寄生容量に占めるコレクタ−基板間容量の比
率が大きくなっているのでこの方法は有効である。ただ
し、トランジスタの動作は、ＭＯＳ型素子の場合と異な
り、素子の主動作電流であるエミッタ電流が基板表面の
エミッタ領域からその下のベース領域を通って更に下の
コレクタ領域に達してコレクタ電流となるという縦方向
動作である。このために、コレクタ領域から基板表面ま
で電流を取り出す電流径路の電気抵抗を低減する目的
で、高不純物濃度の埋め込み（コレクタ）層を形成する
ことが多く、埋め込み層の厚さは数μｍ程度になること
も多い。これらのことから、ＳＯＩ構造においてバイポ
ーラ素子を形成するために必要なシリコン層の厚さは、
ＭＯＳ型素子に適用した場合に比べて非常に厚いことが
要求される。On the other hand, the application of SOI technology has also been studied for bipolar devices. When applied to a bipolar element, the advantage is that the parasitic diode formed mainly by the junction between the collector region and the substrate, especially its large junction capacitance can be reduced. In recent years, the method of forming the base and emitter regions has become a self-bonding process that does not require a patterning mask in lithography, and these parasitic capacitances have become smaller, and the ratio of the collector-substrate capacitance to the total parasitic capacitance has increased. Therefore, this method is effective. However, the operation of the transistor is different from the case of the MOS type element, and the emitter current, which is the main operating current of the element, passes from the emitter region on the substrate surface, passes through the base region below the emitter region, and reaches the collector region further below. It is a vertical movement. Therefore, a buried (collector) layer having a high impurity concentration is often formed in order to reduce the electric resistance of a current path for extracting a current from the collector region to the substrate surface, and the buried layer has a thickness of about several μm. Often becomes. From these facts, the thickness of the silicon layer required to form the bipolar device in the SOI structure is
It is required to be much thicker than when applied to a MOS type element.
【００１２】バイポーラ型素子を用いたデバイスでは、
素子の形成に必要な領域が基板表面から深い領域に渡る
ためＭＯＳ型デバイスのような薄い絶縁膜では素子間の
分離ができない。In the device using the bipolar type element,
Since a region necessary for forming elements extends from the substrate surface to a deep region, it is impossible to separate the elements with a thin insulating film such as a MOS type device.
【００１３】このため、基板中に形成した分離用のＰＮ
接合によって行うＰＮ分離法や、ＬＯＣＯＳ法を改良し
て１μｍ以上といった、厚い酸化膜を形成する酸化膜分
離法などが利用されている。これに対し、近年の高集積
化に対応し分離領域の幅を大幅に縮小できる分離領域形
成方法として、基板表面から深い溝を形成し溝内部を絶
縁物（シリコン酸化膜や多結晶シリコンなど）で充填す
るという溝型分離法が用いられるようになってきてい
る。ただし、この方法を用いた場合には、溝側面におけ
る接合リーク電流の発生を防ぐために溝内壁を酸化し酸
化膜を形成するなど、溝形成時の幅よりも最終的な幅が
大きくなるために、近年の高集積ＭＯＳデバイスの場合
のような１μｍ以下の分離幅にすることは難しい面があ
る。Therefore, the separating PN formed in the substrate
A PN separation method performed by bonding, an oxide film separation method for improving the LOCOS method to form a thick oxide film having a thickness of 1 μm or more, and the like are used. On the other hand, as a separation region forming method capable of significantly reducing the width of the separation region corresponding to the recent high integration, a deep groove is formed from the substrate surface and an insulating material (silicon oxide film, polycrystalline silicon, etc.) is formed inside the groove. The groove-type separation method of filling with is being used. However, when this method is used, since the inner wall of the groove is oxidized to form an oxide film in order to prevent generation of a junction leak current on the side surface of the groove, the final width becomes larger than the width at the time of groove formation. However, it is difficult to set the isolation width to 1 μm or less as in the case of the highly integrated MOS device in recent years.
【００１４】この場合の素子の製造方法の一例として、
ＳＯＩ構造（ＳＩＭＯＸ法）と溝型分離を適用したＮＰ
Ｎ型バイポーラトランジスタの製造方法における主要工
程の断面図を図１２乃至図１５に示す。図１２乃至図１
５において、１はＮ- 型シリコン基板、２は酸化膜絶縁
層、２１はＮ+ 埋め込み層、２２はエピタキシャル層、
３はＮ+ 埋め込み層２１とエピタキシャル層２２により
構成されたシリコン層、２３は溝型分離領域、２４はコ
レクタ電極取り出し領域、２５はエミッタ領域、２６は
ベース領域、２８はコレクタ電極、２９はエミッタ電
極、３０はベース電極、９は絶縁膜である。As an example of the method of manufacturing the element in this case,
NP with SOI structure (SIMOX method) and groove separation
12 to 15 are sectional views showing main steps in the method for manufacturing the N-type bipolar transistor. 12 to 1
In FIG. 5, 1 is an N − type silicon substrate, 2 is an oxide film insulating layer, 21 is an N + buried layer, 22 is an epitaxial layer,
3 is a silicon layer composed of the N + buried layer 21 and the epitaxial layer 22, 23 is a groove type isolation region, 24 is a collector electrode extraction region, 25 is an emitter region, 26 is a base region, 28 is a collector electrode, and 29 is an emitter. An electrode, 30 is a base electrode, and 9 is an insulating film.
【００１５】まず、図１２に示すように、前記図８で示
したＭＯＳ型素子の場合の製造方法と同様な方法により
ＳＯＩ構造を形成し、全面に埋め込み（コレクタ）層を
形成するために例えばアンチモン（Ｓｂ）を１０15／cm
2 程度注入する。First, as shown in FIG. 12, an SOI structure is formed by a method similar to the manufacturing method for the MOS type element shown in FIG. 8, and a buried (collector) layer is formed on the entire surface, for example. Antimony (Sb) 10 15 / cm
Inject about 2
【００１６】次に、図１３に示すように、注入されたイ
オンを熱処理により活性化し、Ｎ+ 埋め込み層２１を形
成し、その後Ｎ- エピタキシャル層２２を形成すること
により、半導体基板１上に酸化膜絶縁層２が形成され、
さらに酸化膜絶縁層２上にシリコン層３が形成され、バ
イポーラトランジスタを形成するのに十分な厚さのシリ
コン層を持ったＳＯＩ構造となる。Next, as shown in FIG. 13, the implanted ions are activated by heat treatment to form an N + buried layer 21 and then an N − epitaxial layer 22 to oxidize it on the semiconductor substrate 1. The film insulating layer 2 is formed,
Further, a silicon layer 3 is formed on the oxide film insulating layer 2 to form an SOI structure having a silicon layer having a sufficient thickness to form a bipolar transistor.
【００１７】次に、図１４に示すように、酸化膜絶縁層
２を終点検出として酸化膜絶縁層２に達するようにシリ
コン層３に溝を堀り、例えばシリコン酸化膜を溝に充填
することにより溝型分離領域２３が形成される。Next, as shown in FIG. 14, a groove is formed in the silicon layer 3 so as to reach the oxide film insulating layer 2 by detecting the oxide film insulating layer 2 as an end point, and for example, a silicon oxide film is filled in the groove. Thus, the groove type isolation region 23 is formed.
【００１８】次に、図１５に示すように、公知の接合形
成及び電極形成技術により、コレクタ電極取り出し領域
２４、エミッタ領域２５、ベース領域２６を形成し、絶
縁膜９で全面を覆った後、コレクタ電極２８、エミッタ
電極２９、ベース電極３０を形成して素子が完成する。Next, as shown in FIG. 15, a collector electrode extraction region 24, an emitter region 25, and a base region 26 are formed by known junction formation and electrode formation techniques, and after covering the entire surface with an insulating film 9, The collector electrode 28, the emitter electrode 29, and the base electrode 30 are formed to complete the device.
【００１９】一方、近年盛んに研究されてきている分野
として、同一半導体基板上にＭＯＳ型素子とバイポーラ
型素子（通常ＮＰＮトランジスタ）を形成するＢｉＣＭ
ＯＳ（Bipolar Complementary MOS ）型半導体デバイス
がある。ＢｉＣＭＯＳでは、バイポーラ型素子回路とＭ
ＯＳ型素子回路あるいは融合型回路などを適宜選択でき
ることから、バイポーラ素子の特徴である高速動作・高
電流駆動能力とＭＯＳ型素子の低消費電力・高集積性の
両方を生かすことができる。このため、ＭＯＳ型素子の
みを用いたデバイスでは達成できない高速動作を、ＭＯ
Ｓ型素子のみを用いたデバイスと同程度の低消費電力・
高集積度を持ちつつ行なわせることができる。On the other hand, as a field which has been actively studied in recent years, BiCM in which a MOS type element and a bipolar type element (usually NPN transistor) are formed on the same semiconductor substrate.
There is an OS (Bipolar Complementary MOS) type semiconductor device. In BiCMOS, a bipolar device circuit and M
Since the OS type element circuit or the fused type circuit can be appropriately selected, it is possible to take advantage of the features of the bipolar element, such as high speed operation and high current drive capability, and low power consumption and high integration of the MOS type element. Therefore, high-speed operation that cannot be achieved by a device using only MOS type devices
Low power consumption equivalent to devices using only S-type elements
It can be performed with a high degree of integration.
【００２０】ＢｉＣＭＯＳデバイスにおいては、ＭＯＳ
とバイポーラの両方の素子分離を行わなければいが、前
記の通りＭＯＳ部の素子間分離はトレンチ分離は使えな
いことから、両素子の基板表面部における分離形成法と
してＬＯＣＯＳ法などを用い、基板中における分離とし
ては通常、ＭＯＳ型素子領域ではＰＮ接合分離を、バイ
ポーラ型素子領域ではＰＮ接合分離（または溝型分離）
を用いることになる。In BiCMOS devices, MOS
Although it is necessary to perform both element isolation of bipolar and bipolar elements, as described above, trench isolation cannot be used for element isolation of the MOS part. Therefore, LOCOS method or the like is used as the isolation formation method on the substrate surface of both elements, and In the MOS type element region, PN junction isolation is usually used for isolation, and in the bipolar type element region, PN junction isolation (or groove type isolation) is usually used.
Will be used.
【００２１】この一例として、ＮＰＮバイポーラトラン
ジスタとＰＭＯＳトランジスタを同一基板の一方主面上
に形成したＢｉＣＭＯＳデバイスの断面図を図１６に示
す。図１６において、３１はＰ- 型半導体基板、その他
の図に用いられている符号で前記したＭＯＳ及びバイポ
ーラ型素子の説明に用いた図１１及び図１５と同一符号
は図１１及び図１５と同一内容または相当部分を示す。
この例においてはＭＯＳトランジスタとバイポーラトラ
ンジスタは、素子表面に形成された酸化膜４と、Ｐ- 型
半導体基板３１とシリコン層３、Ｎ+ 埋め込み層２１或
いはエピタキシャル層２２とのＰＮ接合によって分離さ
れている。As an example of this, FIG. 16 is a sectional view of a BiCMOS device in which an NPN bipolar transistor and a PMOS transistor are formed on one main surface of the same substrate. In FIG. 16, reference numeral 31 is a P − type semiconductor substrate, and reference numerals used in other figures are the same as those in FIGS. 11 and 15 used in the description of the MOS and bipolar type elements. Reference numerals are the same as those in FIGS. 11 and 15. Indicates the content or the corresponding part.
In this example, the MOS transistor and the bipolar transistor are separated by the PN junction between the oxide film 4 formed on the device surface and the P − type semiconductor substrate 31 and the silicon layer 3, the N + buried layer 21 or the epitaxial layer 22. There is.
【００２２】[0022]
【発明が解決しようとする課題】従来の半導体装置及び
その製造方法は以上のように構成されており、前述した
ようにＭＯＳ型素子の実効的な動作領域はゲート絶縁膜
５の直下でありバイポーラ型素子では基板表面深くにあ
る埋め込み層２１までである。従って、図１６からも明
らかなように、前述したような各々の素子に対するＳＯ
Ｉ構造を適用しようとしても、素子の動作領域の深さが
異なるために適用できないという問題点があった。The conventional semiconductor device and the manufacturing method thereof are configured as described above, and as described above, the effective operation region of the MOS type element is immediately below the gate insulating film 5 and the bipolar device. In the mold element, it is up to the buried layer 21 deep in the substrate surface. Therefore, as is clear from FIG. 16, the SO for each element as described above is
Even if the I structure is applied, there is a problem in that it cannot be applied because the operating regions of the elements have different depths.
【００２３】また、各々の素子に対応して従来例のＳＯ
Ｉ構造の製造方法により絶縁層を異なる深さに一度に形
成しようとすると、例えばＳＩＭＯＸ法などを用いた場
合では注入した酸素イオンとシリコン原子が結合すると
きに体積膨張が起こるので、深さの異なる領域を一つの
基板上に形成すると応力や結晶欠陥が発生することにな
り、接合のリーク電流の発生など素子の性能劣化及び歩
留まりの低下をもたらしてしまうという問題点があっ
た。Further, the conventional SO
When an insulating layer is formed at different depths at a time by the manufacturing method of the I structure, for example, when SIMOX method is used, volume expansion occurs when the implanted oxygen ions and silicon atoms are combined. When different regions are formed on one substrate, stress and crystal defects are generated, which leads to deterioration of device performance such as generation of a leak current at a junction and a decrease in yield.
【００２４】本発明は上記のよう問題点を解消するため
になされたもので、例えばＢｉＣＭＯＳ型デバイスのよ
うに素子の動作領域の深さが異なる半導体装置において
もＳＯＩ構造を適用し、ＳＯＩ構造を採用したＭＯＳ型
素子及びバイポーラ型素子の各々の利点を得て、高速化
・高性能化したＢｉＣＭＯＳデバイスを得るとともに、
ＢｉＣＭＯＳデバイスにＳＯＩ構造を採用するとき、体
積膨張による応力や結晶欠陥の発生に伴う素子の特性劣
化を防止することを目的としている。The present invention has been made to solve the above-mentioned problems, and the SOI structure is applied to a semiconductor device such as a BiCMOS type device in which the operating regions of the elements have different depths. Taking advantage of each of the adopted MOS type element and bipolar type element, a high speed and high performance BiCMOS device is obtained, and
When the SOI structure is adopted for the BiCMOS device, it is intended to prevent the characteristic deterioration of the element due to the stress due to volume expansion and the generation of crystal defects.
【００２５】[0025]
【課題を解決するための手段】第１の発明に係る半導体
装置の製造方法は、半導体基体の一方主面から所定深さ
の一部の領域に埋設絶縁層を形成したＳＯＩ構造を有す
る半導体装置の製造方法であって、前記半導体基体の前
記埋設絶縁層を形成すべき領域にイオン注入する工程
と、前記半導体基体の前記イオン注入した領域の周囲に
前記半導体基体の一方主面から前記イオン注入した領域
より深く溝を掘って溝型分離領域を形成する工程と、前
記溝型分離領域を形成した後、前記半導体基体に熱処理
を施して前記注入したイオンにより前記埋設絶縁層を形
成する工程とを備えて構成されている。A method of manufacturing a semiconductor device according to a first aspect of the present invention is a semiconductor device having an SOI structure in which a buried insulating layer is formed in a part of a predetermined depth from one main surface of a semiconductor substrate. A step of implanting ions into a region of the semiconductor substrate where the buried insulating layer is to be formed, and the ion implantation from one main surface of the semiconductor substrate around the ion implanted region of the semiconductor substrate. Forming a trench isolation region by digging a trench deeper than the formed region; and forming the trench isolation region, then subjecting the semiconductor substrate to heat treatment to form the buried insulating layer by the implanted ions. Is configured.
【００２６】第２の発明に係る半導体装置は、半導体基
体の一方主面上に第１の半導体素子と第２の半導体素子
とを有する半導体装置であって、前記半導体基体におけ
る前記第１の半導体素子の形成領域に形成された前記半
導体基体の一方主面より第１の深さにある第１の埋設絶
縁層と、前記第１の埋設絶縁層の周囲に形成された、前
記半導体基体の一方主面から前記第１の埋設絶縁層より
深い領域まで達する溝型分離領域と、前記半導体基体に
おける前記第２の半導体素子の形成領域に形成された前
記半導体基体の一方主面より第２の深さにある第２の埋
設絶縁層と、前記第２の埋設絶縁層の周囲に形成され
た、前記半導体基体の一方主面から前記第２の埋設絶縁
層より深い領域まで達する溝型分離領域とを備えて構成
されている。A semiconductor device according to a second invention is a semiconductor device having a first semiconductor element and a second semiconductor element on one main surface of a semiconductor substrate, and the first semiconductor in the semiconductor substrate. One of the semiconductor bases formed in the element formation region at a first depth from one main surface of the semiconductor base, and one of the semiconductor bases formed around the first buried insulation layer A groove-type isolation region reaching from the main surface to a region deeper than the first buried insulating layer, and a second depth from one main surface of the semiconductor substrate formed in the formation region of the second semiconductor element in the semiconductor substrate. A second buried insulating layer, and a groove-type isolation region formed around the second buried insulating layer and extending from one main surface of the semiconductor substrate to a region deeper than the second buried insulating layer. Is configured.
【００２７】第３の発明に係る半導体装置の製造方法
は、半導体基体の一方主面上に第１の半導体素子と第２
の半導体素子とを有する半導体装置の製造方法であっ
て、前記半導体基体表面に選択的に、前記第１及び第２
の半導体素子の形成領域においてそれぞれ注入深さが異
なるようにイオンを注入する工程と、前記注入深さの異
なる両イオン注入領域の各々の周囲に、前記半導体基体
の一方主面から各イオン注入領域より深く溝を掘って溝
型分離領域を形成する工程と、前記溝型分離領域を形成
した後、前記半導体基体に熱処理を施して前記注入した
イオンによって前記第１及び第２の半導体素子の形成領
域に深さの異なる埋設絶縁層を形成する工程とを備えて
構成されている。According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein a first semiconductor element and a second semiconductor element are provided on one main surface of a semiconductor substrate.
A method of manufacturing a semiconductor device having the semiconductor element according to claim 1, wherein the first and second semiconductor layers are selectively formed on the surface of the semiconductor substrate.
The step of implanting ions so that the implantation depths are different in the semiconductor element formation regions, and the ion implantation regions are formed from one main surface of the semiconductor substrate around each of the ion implantation regions having different implantation depths. Forming a groove-type isolation region by digging a groove deeper, and forming the first and second semiconductor elements with the implanted ions by heat-treating the semiconductor substrate after forming the groove-type isolation region. And a step of forming buried insulating layers having different depths in the regions.
【００２８】第４の発明に係る半導体装置は、半導体基
体の一方主面上に第１の半導体素子と第２の半導体素子
とを有する半導体装置であって、前記半導体基体の一方
主面から第１の深さにおいて、前記半導体基体の全面に
形成された第１の埋設絶縁層と、前記半導体基体の一方
主面から前記第１の深さよりも浅い第２の深さにおい
て、前記半導体基体の一部に形成された第２の埋設絶縁
層と、前記第２の埋設絶縁層の周囲に形成された、前記
半導体基体の一方主面から前記第２の埋設絶縁層より深
い領域まで達する溝型分離領域と、前記第２の埋設絶縁
層の無い前記第１の埋設絶縁層上の前記半導体基体に設
けられた前記第１の半導体素子の形成領域と、前記第２
の埋設絶縁層上の前記半導体基体に設けられた前記第２
の半導体素子の形成領域とを備えて構成されている。A semiconductor device according to a fourth invention is a semiconductor device having a first semiconductor element and a second semiconductor element on one main surface of a semiconductor substrate, wherein A first buried insulating layer formed over the entire surface of the semiconductor substrate at a depth of 1 and a second depth shallower than the first depth from the one main surface of the semiconductor substrate. A second buried insulating layer formed in a part, and a trench type formed around the second buried insulating layer and extending from one main surface of the semiconductor substrate to a region deeper than the second buried insulating layer. An isolation region; a formation region of the first semiconductor element provided on the semiconductor substrate on the first buried insulating layer without the second buried insulating layer;
The second insulating layer provided on the semiconductor substrate on the buried insulating layer of
And a semiconductor element forming region.
【００２９】第５の発明に係る半導体装置の製造方法
は、半導体基体の一方主面上に第１の半導体素子と第２
の半導体素子とを有する半導体装置の製造方法であっ
て、前記半導体基体の一方主面から第１の深さにおい
て、前記半導体基体の全面に第１の埋設絶縁層を形成す
る工程と、前記半導体基体の一方主面から前記第１の深
さよりも浅い第２の深さに達するように、前記半導体基
体の一方主面の一部に選択的にイオンを注入する工程
と、前記半導体基体の前記イオンを注入した領域の周囲
に前記半導体基体の一方主面から前記イオンを注入した
領域より深く溝を掘って溝型分離領域を形成する工程
と、前記溝型分離領域を形成した後、前記半導体基体に
熱処理を施して前記注入したイオンによって第２の埋設
絶縁層を形成する工程と、前記第２の埋設絶縁層の無い
前記第１の埋設絶縁層上の前記半導体基体に前記第１の
半導体素子を形成する工程と、前記第２の埋設絶縁層上
の前記半導体基体に前記第２の半導体素子を形成する工
程とを備えて構成されている。According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a first semiconductor element and a second semiconductor element are provided on one main surface of a semiconductor substrate.
And a step of forming a first buried insulating layer over the entire surface of the semiconductor substrate at a first depth from one main surface of the semiconductor substrate, the method comprising: Selectively implanting ions into a part of one main surface of the semiconductor substrate so as to reach a second depth shallower than the first depth from one main surface of the substrate; A step of forming a groove type isolation region by forming a groove deeper than the region into which the ions have been implanted from one main surface of the semiconductor substrate around the region into which the ion type has been implanted; and after forming the groove type isolation region, the semiconductor Heat-treating the substrate to form a second buried insulating layer by the implanted ions; and the first semiconductor on the semiconductor substrate on the first buried insulating layer without the second buried insulating layer. Process of forming elements It is configured and the step of forming the second semiconductor element to the semiconductor substrate on the second buried insulating layer.
【００３０】[0030]
【作用】第１の発明による半導体装置の製造方法におい
ては、半導体基体のイオン注入した領域の周囲に前記半
導体基体の一方主面から前記イオン注入した領域より深
く溝を掘って溝型分離領域を形成する工程を備えてお
り、素子分離用の溝型分離領域を形成するために深い溝
を形成する工程を、ＳＯＩ構造における埋設絶縁層を形
成する工程よりも先に行うようにしたので、埋設絶縁層
形成時における体積膨張による応力や結晶欠陥の発生を
抑えることができる。In the method of manufacturing a semiconductor device according to the first aspect of the present invention, a groove-type isolation region is formed by digging a groove from one main surface of the semiconductor substrate deeper than the ion-implanted region around the ion-implanted region of the semiconductor substrate. Since the step of forming the deep trench for forming the trench isolation region for element isolation is performed prior to the step of forming the buried insulating layer in the SOI structure, It is possible to suppress the occurrence of stress and crystal defects due to volume expansion during formation of the insulating layer.
【００３１】第２の発明による半導体装置においては、
第１の埋設絶縁層の周囲に形成された、前記半導体基体
の一方主面から第１の埋設絶縁層より深い領域まで達す
る溝型分離領域と、第２の埋設絶縁層の周囲に形成され
た、前記半導体基体の一方主面から前記第２の埋設絶縁
層より深い領域まで達する溝型分離領域とを備えている
ので、第１の半導体素子や第２の半導体素子の形成領域
から他の領域を分離することができるとともに、第１及
び第２の埋設絶縁層形成時における体積膨張による応力
や結晶欠陥の発生を抑えることができる。In the semiconductor device according to the second invention,
A groove-type isolation region formed around the first buried insulating layer and extending from one main surface of the semiconductor substrate to a region deeper than the first buried insulating layer, and formed around the second buried insulating layer. , A groove-type isolation region reaching from one main surface of the semiconductor substrate to a region deeper than the second buried insulating layer, so that the region from the formation region of the first semiconductor element or the second semiconductor element to the other region. In addition, it is possible to suppress the occurrence of stress and crystal defects due to volume expansion during the formation of the first and second buried insulating layers.
【００３２】第３の発明による半導体装置の製造方法に
おいては、注入深さの異なる両イオン注入領域の各々の
周囲に、半導体基体の一方主面から各イオン注入領域よ
り深く溝を掘って溝型分離領域を形成する工程を備えて
おり、素子分離用の溝型分離領域を形成するために深い
溝を形成する工程を、ＳＯＩ構造における埋設絶縁層を
形成する工程よりも先に行うようにしたので、第１及び
第２の埋設絶縁層形成時における体積膨張による応力や
結晶欠陥の発生を抑えることができる。また、半導体基
体表面に選択的に、第１及び第２の半導体素子の形成領
域においてそれぞれ注入深さが異なるようにイオンを注
入する工程を備えているので、深さの異なる第１及び第
２の埋設絶縁層を持つＳＯＩ構造を一度に形成すること
ができる。In the method for manufacturing a semiconductor device according to the third aspect of the present invention, a groove type is formed by digging a groove from one main surface of the semiconductor substrate deeper than each ion implantation region around each of the ion implantation regions having different implantation depths. The method includes a step of forming an isolation region, and the step of forming a deep groove for forming a groove type isolation region for element isolation is performed before the step of forming a buried insulating layer in an SOI structure. Therefore, it is possible to suppress the occurrence of stress and crystal defects due to volume expansion during the formation of the first and second buried insulating layers. Further, since the step of selectively implanting ions into the surface of the semiconductor substrate so that the implantation depths are different in the formation regions of the first and second semiconductor elements is provided, the first and second regions having different depths are provided. The SOI structure having the buried insulating layer can be formed at one time.
【００３３】第４の発明による半導体装置においては、
第２の埋設絶縁層の周囲に形成された、前記半導体基体
の一方主面から第２の埋設絶縁層より深い領域まで達す
る溝型分離領域を備えているので、第２の半導体素子の
形成領域と他の領域とを分離することができると伴に、
第２の埋設絶縁層形成時における体積膨張による応力や
結晶欠陥の発生を抑えることができる。また、半導体基
体の全面に形成された第１の埋設絶縁層と、第２の半導
体素子の形成領域に形成された前記第１の埋設絶縁層よ
りも浅い第２の埋設絶縁層とを備えており、第２の半導
体素子領域は第１及び第２の埋設絶縁層によって２重の
ＳＯＩ構造になり、１層のＳＯＩ構造の場合よりＳＯＩ
としての効果を上げることができる。In the semiconductor device according to the fourth invention,
Since a groove-type isolation region is formed around the second buried insulating layer and extends from one main surface of the semiconductor substrate to a region deeper than the second buried insulating layer, a second semiconductor element formation region is provided. Can be separated from other areas,
It is possible to suppress the occurrence of stress and crystal defects due to volume expansion during the formation of the second buried insulating layer. The semiconductor device further includes a first buried insulating layer formed on the entire surface of the semiconductor substrate and a second buried insulating layer shallower than the first buried insulating layer formed in the formation region of the second semiconductor element. The second semiconductor element region has a double SOI structure due to the first and second buried insulating layers, and has an SOI structure more than that of the single-layer SOI structure.
The effect as can be improved.
【００３４】第５の発明による半導体装置の製造方法に
おいては、半導体基体のイオンを注入した領域の周囲に
半導体基体の一方主面から前記イオンを注入した領域よ
り深く溝を掘って溝型分離領域を形成する工程を備えて
おり、素子分離用の溝型分離領域を形成するために深い
溝を形成する工程を、ＳＯＩ構造における第２の埋設絶
縁層を形成する工程よりも先に行うようにしたので、第
２の埋設絶縁層形成時における体積膨張による応力や結
晶欠陥の発生を抑えることができる。また、半導体基体
の一方主面から第１の深さにおいて、半導体基体の全面
に第１の埋設絶縁層を形成する工程と、前記半導体基体
の一方主面から前記第１の深さよりも浅い第２の深さに
達するように、前記半導体基体の一方主面の一部に選択
的にイオンを注入する工程と、前記半導体基体のイオン
を注入した領域の周囲に前記半導体基体の一方主面から
前記イオンを注入した領域より深く溝を掘って溝型分離
領域を形成する工程と、前記溝型分離領域を形成した
後、前記半導体基体に熱処理を施して前記注入したイオ
ンによって第２の埋設絶縁層を形成する工程を備えてお
り、第２の半導体素子領域は第１及び第２の埋設絶縁層
によって２重のＳＯＩ構造を容易に形成でき、１層のＳ
ＯＩ構造の場合よりＳＯＩとしての効果を上げることが
できる。In the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, a groove-type isolation region is formed by digging a groove around the ion-implanted region of the semiconductor substrate from one main surface of the semiconductor substrate deeper than the region into which the ion is implanted. And a step of forming a deep groove for forming a groove type isolation region for element isolation is performed prior to a step of forming a second buried insulating layer in the SOI structure. Therefore, it is possible to suppress the generation of stress and crystal defects due to volume expansion during the formation of the second buried insulating layer. A step of forming a first buried insulating layer on the entire surface of the semiconductor substrate at a first depth from one main surface of the semiconductor substrate; and a step of forming a first buried insulating layer from the one main surface of the semiconductor substrate to a depth less than the first depth. A step of selectively implanting ions into a part of one main surface of the semiconductor substrate so as to reach a depth of 2, and from the one main surface of the semiconductor substrate around the ion-implanted region of the semiconductor substrate. Forming a groove-type isolation region by digging a groove deeper than the ion-implanted region; and, after forming the groove-type isolation region, heat-treating the semiconductor substrate to form a second buried insulation by the ion-implanted ion. The second semiconductor element region can be easily formed with a double SOI structure by the first and second buried insulating layers, and a single layer S layer can be formed.
The effect as SOI can be improved more than in the case of the OI structure.
【００３５】[0035]
【実施例】以下、この発明の第１実施例を図１乃至図３
を用いて説明する。図１乃至図３に示す断面図は、ＮＰ
ＮバイポーラトランジスタとＰＭＯＳトランジスタを一
つの半導体基体上に形成した場合の半導体装置の製造方
法の主要工程の断面図である。そして、図１乃至図３に
おいて、１はＮ- 型シリコン基板、２ａ，２ｂは酸化膜
絶縁層、３ａ，３ｂはＳＯＩ構造におけるシリコン層、
１００はマスク膜、ＤＯはＮ- 型シリコン基板１に注入
した酸素イオン、ＤＭはＭＯＳトランジスタを形成する
ＭＯＳ型素子形成領域、ＤＢはバイポーラトランジスタ
を形成するバイポーラ型素子形成領域、４〜１２の図１
１と同一の符号は図１１と同一もしくは相当部分を示
し、また２１〜２６及び２８〜３０の図１５と同一の符
号は図１１と同一もしくは相当部分を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.
Will be explained. The sectional views shown in FIGS. 1 to 3 are NPs.
FIG. 9 is a cross-sectional view of main steps of a method for manufacturing a semiconductor device when an N bipolar transistor and a PMOS transistor are formed on one semiconductor substrate. 1 to 3, 1 is an N − -type silicon substrate, 2a and 2b are oxide film insulating layers, 3a and 3b are silicon layers in an SOI structure,
Reference numeral 100 is a mask film, DO is oxygen ions implanted into the N − type silicon substrate 1, DM is a MOS type element formation region for forming a MOS transistor, DB is a bipolar type element formation region for forming a bipolar transistor, and FIGS. 1
The same reference numerals as 1 denote the same or corresponding portions as in FIG. 11, and the same reference numerals as 21 to 26 and 28 to 30 denote the same or corresponding portions in FIG. 11.
【００３６】まず、図１に示すように、次のイオン注入
工程で注入に対するマスクとなるマスク膜１００をＮ-
型シリコン基板１上のＭＯＳ型素子形成領域に選択的に
形成し、そしてシリコン基板１中にシリコン酸化膜を形
成するに十分な量の酸素イオンをマスク膜１００の有無
に応じて深さの異なるように打ち込む。つまり、マスク
膜１００の形成されているＭＯＳ型素子形成領域ＤＭに
注入された酸素イオンＤＯは、マスク膜１００の影響で
Ｎ- 型シリコン基板１表面から浅い位置にとどまり、マ
スク膜１００の形成されていないバイポーラ型素子形成
領域ＤＢに注入された酸素イオンＤＯは、Ｎ- 型シリコ
ン基板１表面から深い位置まで達する。First, as shown in FIG. 1, a mask film 100, which serves as a mask for implantation in the next ion implantation step, is formed with N −.
Type oxygen substrate is selectively formed in a MOS type element formation region on the type silicon substrate 1, and a sufficient amount of oxygen ions for forming a silicon oxide film in the silicon substrate 1 has different depths depending on the presence or absence of the mask film 100. Type in. That is, the oxygen ions DO implanted in the MOS type element formation region DM in which the mask film 100 is formed remain under a shallow position from the surface of the N − type silicon substrate 1 due to the influence of the mask film 100, and the mask film 100 is formed. Oxygen ions DO implanted in the bipolar element formation region DB not yet reached reach a deep position from the surface of the N − type silicon substrate 1.
【００３７】次に、図２に示すように、マスク膜１００
を除去した後、注入深さの異なる酸素イオンＤＯを有す
るＭＯＳ型素子形成領域ＤＭとバイポーラ型素子形成領
域ＤＢそれぞれの周囲に深い溝を形成し、その後、高温
の熱処理を加えることによりＮ- 型シリコン基板１でシ
リコン原子と酸素イオンを結合させてバイポーラ型素子
形成領域ＤＢにはＮ- 型シリコン基板１表面から深い位
置に絶縁層２ａを形成し、ＭＯＳ形成領域ＤＭにはＮ-
型シリコン基板１表面から浅い位置に絶縁層２ｂを形成
する。この時、溝があるため、シリコン原子と酸素イオ
ンを結合させるときに生ずる体積膨張による応力や結晶
欠陥の発生を防止して、接合のリーク電流の発生など素
子の性能劣化及び歩留まりの低下を防ぐことができる。Next, as shown in FIG. 2, the mask film 100.
After the removal, the deep trenches are formed around each of the MOS type element formation region DM and the bipolar type element formation region DB having the oxygen ions DO with different implantation depths, and then a high temperature heat treatment is applied to the N − type. in the silicon substrate 1 by bonding the silicon atoms and oxygen ions in the bipolar element forming region DB N - -type silicon substrate 1 surface at a deep position to form an insulating layer 2a, the MOS formation region DM N -
The insulating layer 2b is formed at a shallow position from the surface of the mold silicon substrate 1. At this time, since there is a groove, stress and crystal defects due to volume expansion that occur when bonding silicon atoms and oxygen ions are prevented from occurring, and deterioration of device performance such as generation of leak current at the junction and decrease in yield are prevented. be able to.
【００３８】最後に、図３に示すように、シリコン酸化
膜等で溝を充填して溝型分離領域２３を形成した後、例
えば、バイポーラ埋め込み層２１を形成するためのイオ
ンを高加速エネルギーで注入する等、その後の工程は、
従来技術の項で述べたと同様な方法あるいはその他の公
知の製造方法により、バイポーラ型素子及びＭＯＳ型素
子を形成する。Finally, as shown in FIG. 3, after forming the groove type isolation region 23 by filling the groove with a silicon oxide film or the like, for example, ions for forming the bipolar buried layer 21 are accelerated with high acceleration energy. Subsequent steps such as injection,
The bipolar type element and the MOS type element are formed by the same method as described in the section of the prior art or other known manufacturing methods.
【００３９】次に、この発明の第２実施例について図４
乃至図７を用いて説明する。図４乃至図７に示す断面図
は、ＮＰＮバイポーラトランジスタとＰＭＯＳトランジ
スタを一つの半導体基体上に形成した場合の半導体装置
の製造方法の主要工程の断面図である。そして、図４乃
至図７において、１はＮ- 型シリコン基板、２ａは酸化
膜絶縁層、２ｂは酸化膜絶縁層、３はシリコン層、ＤＯ
はＮ- 型シリコン基板１に注入された酸素イオン、ＤＢ
はＮＰＮバイポーラトランジスタを形成するバイポーラ
型素子形成領域、ＤＭはＰＭＯＳトランジスタを形成す
るＭＯＳ型素子形成領域、１００はマスク膜、また図３
と同一符号のものは図３と同一内容もしくは相当部分を
示す。Next, the second embodiment of the present invention will be described with reference to FIG.
It will be described with reference to FIGS. The cross-sectional views shown in FIGS. 4 to 7 are cross-sectional views of the main steps of the method for manufacturing the semiconductor device when the NPN bipolar transistor and the PMOS transistor are formed on one semiconductor substrate. 4 to 7, 1 is an N − -type silicon substrate, 2a is an oxide film insulating layer, 2b is an oxide film insulating layer, 3 is a silicon layer, and DO.
Is oxygen ions implanted into the N − type silicon substrate 1, DB
Is a bipolar element formation region for forming an NPN bipolar transistor, DM is a MOS type element formation region for forming a PMOS transistor, 100 is a mask film, and FIG.
Items having the same reference numerals as those in FIG.
【００４０】まず、図４のように、Ｎ- 型シリコン基板
１全面にシリコン酸化膜を形成するに十分な量の酸素イ
オンを打ち込み、高温の熱処理を加えることにより基板
シリコン原子と酸素イオンを結合させて基板表面から深
い位置に第１の絶縁層２ａを形成する。First, as shown in FIG. 4, a sufficient amount of oxygen ions are formed to form a silicon oxide film on the entire surface of the N -- type silicon substrate 1, and heat treatment at high temperature is applied to bond the substrate silicon atoms and oxygen ions. Then, the first insulating layer 2a is formed at a deep position from the surface of the substrate.
【００４１】次に、図５に示すように、ＭＯＳ型素子形
成領域ＤＭに次のイオン注入工程で注入に対するマスク
となるマスク膜１００を選択的に形成し、しかる後マス
ク膜１００をマスクとしてＭＯＳ型素子形成領域ＤＭに
選択的にシリコン酸化膜を形成するに十分な量の酸素イ
オンをを打ち込む。Next, as shown in FIG. 5, a mask film 100 serving as a mask for implantation is selectively formed in the MOS type element formation region DM in the next ion implantation step, and thereafter, the mask film 100 is used as a mask to form a MOS. Sufficient oxygen ions are implanted into the mold element formation region DM to selectively form a silicon oxide film.
【００４２】次に、図６に示すように、マスク膜１００
を除去した後、ＭＯＳ型素子形成領域ＤＭとバイポーラ
型素子形成領域ＤＢのそれぞれの周囲に深い溝を形成
し、しかる後、高温の熱処理を加えることによりＮ- 型
シリコン基板１のシリコン原子と酸素イオンを結合させ
てＭＯＳ型素子形成領域ＤＭにはＮ- 型シリコン基板１
表面から浅い位置に絶縁層２ｂを形成する。この時、溝
があるため、シリコン原子と酸素原子を結合させるとき
に生ずる体積膨張による応力や結晶欠陥の発生を防止し
て、接合のリーク電流の発生など素子の性能劣化及び歩
留まりの低下を防ぐことができる。Next, as shown in FIG. 6, the mask film 100.
After the removal, the deep groove is formed around each of the MOS type element formation region DM and the bipolar type element formation region DB, and then a high temperature heat treatment is applied to the silicon type oxygen and oxygen atoms of the N − type silicon substrate 1. N − type silicon substrate 1 is formed in the MOS type element forming region DM by combining ions.
The insulating layer 2b is formed at a position shallow from the surface. At this time, since there is a groove, stress and crystal defects due to volume expansion that occur when bonding silicon atoms and oxygen atoms are prevented from occurring, and deterioration of device performance such as generation of junction leakage current and reduction of yield are prevented. be able to.
【００４３】最後に、図７に示すように、シリコン酸化
膜等で溝を充填して溝型分離領域２３を形成した後、バ
イポーラ埋め込み層２１を形成するためのイオンを高加
速エネルギーで注入する等、従来技術の項で述べたと同
様な方法あるいはその他の公知の製造方法によりバイポ
ーラ型素子及びＭＯＳ型素子を形成する。なお、上記第
１及び第２実施例では、第１の素子として縦型バイポー
ラトランジスタ、第２の素子としてＭＯＳトランジスタ
を用いた例を示したが、第２の素子として上記各実施例
のＭＯＳトランジスタのゲート絶縁膜５を開口してベー
ス電極を形成した横型バイポーラトランジスタを用いて
もよく、上記第１及び第２実施例と同様の効果を奏す
る。Finally, as shown in FIG. 7, after the trench is filled with a silicon oxide film or the like to form the trench type isolation region 23, ions for forming the bipolar buried layer 21 are implanted with high acceleration energy. A bipolar type element and a MOS type element are formed by the same method as described in the section of the prior art or other known manufacturing methods. In the first and second embodiments, the vertical bipolar transistor is used as the first element and the MOS transistor is used as the second element. However, the MOS transistor of each of the above embodiments is used as the second element. A lateral bipolar transistor in which the gate insulating film 5 is opened to form a base electrode may be used, and the same effects as those of the first and second embodiments are obtained.
【００４４】[0044]
【発明の効果】以上のように、請求項１記載の半導体装
置の製造方法によれば、半導体基体のイオン注入した領
域の周囲に前記半導体基体の一方主面から前記イオン注
入した領域より深く溝を掘って溝型分離領域を形成する
工程を備えており、埋設絶縁層形成時における体積膨張
による応力や結晶欠陥の発生を抑えることができ、応力
や結晶欠陥の発生に伴う素子の特性劣化を防止すること
ができるという効果がある。As described above, according to the method of manufacturing a semiconductor device of the first aspect, a groove is formed around the ion-implanted region of the semiconductor substrate deeper than the ion-implanted region from one main surface of the semiconductor substrate. It is possible to suppress the occurrence of stress and crystal defects due to volume expansion during the formation of the buried insulating layer, and to prevent the deterioration of the device characteristics due to the occurrence of stress and crystal defects. The effect is that it can be prevented.
【００４５】また、請求項２記載の半導体装置によれ
ば、第１の埋設絶縁層の周囲に形成された第１の絶縁層
より深い溝型分離領域と、第２の半導体素子の形成領域
の周囲に形成された、前記半導体基体の一方主面から前
記第２の埋設絶縁層より深い領域まで達する溝型分離領
域とを備えているので、第１の半導体素子や第２の半導
体素子の形成領域から他の領域を分離することができる
とともに、第１及び第２の埋設絶縁層形成時における体
積膨張による応力や結晶欠陥の発生を抑えることがで
き、応力や結晶欠陥の発生に伴う素子の特性劣化を防止
することができるという効果がある。According to another aspect of the semiconductor device of the present invention, there are a trench type isolation region formed around the first buried insulating layer and deeper than the first insulating layer, and a second semiconductor element forming region. Forming the first semiconductor element or the second semiconductor element, since it has a groove-type isolation region formed around the one main surface of the semiconductor substrate and reaching a region deeper than the second buried insulating layer. It is possible to separate the other region from the region, and it is possible to suppress the generation of stress and crystal defects due to the volume expansion during the formation of the first and second buried insulating layers, and it is possible to prevent the stress and crystal defects from occurring in the device. There is an effect that characteristic deterioration can be prevented.
【００４６】また、請求項３記載の半導体装置の製造方
法によれば、注入深さの異なる両イオン注入領域の各々
の周囲に、半導体基体の一方主面から各イオン注入領域
より深く溝を掘って溝型分離領域を形成する工程を備え
ており、素子分離用の溝型分離領域を形成するために深
い溝を形成する工程を、ＳＯＩ構造における埋設絶縁層
を形成する工程よりも先に行うようにしたので、第１及
び第２の埋設絶縁層形成時における体積膨張による応力
や結晶欠陥の発生を抑えることができ、応力や結晶欠陥
の発生に伴う素子の特性劣化を防止することができると
いう効果がある。また、半導体基体表面に選択的に、第
１及び第２の半導体素子の形成領域においてそれぞれ注
入深さが異なるようにイオンを注入する工程を備えてい
るので、深さの異なる第１及び第２の埋設絶縁層を持つ
ＳＯＩ構造を一度に形成することができ、工程を簡素化
できるという効果がある。Further, according to the method of manufacturing a semiconductor device of the third aspect, a groove is formed in the periphery of each of the ion implantation regions having different implantation depths from one main surface of the semiconductor substrate deeper than the ion implantation regions. Forming a groove type isolation region, and performing a step of forming a deep groove for forming a groove type isolation region for element isolation is performed before a step of forming a buried insulating layer in the SOI structure. Therefore, it is possible to suppress the generation of stress and crystal defects due to the volume expansion during the formation of the first and second buried insulating layers, and it is possible to prevent the deterioration of the element characteristics due to the generation of stress and crystal defects. There is an effect. Further, since the step of selectively implanting ions into the surface of the semiconductor substrate so that the implantation depths are different in the formation regions of the first and second semiconductor elements is provided, the first and second regions having different depths are provided. The SOI structure having the buried insulating layer can be formed at one time, and the process can be simplified.
【００４７】また、請求項４記載の半導体装置によれ
ば、第２の埋設絶縁層の周囲に形成された、前記半導体
基体の一方主面から第２の埋設絶縁層より深い領域まで
達する溝型分離領域を備えているので、第２の半導体素
子の形成領域と他の領域とを分離することができると伴
に、第２の埋設絶縁層形成時における体積膨張による応
力や結晶欠陥の発生を抑えることができる。また、半導
体基体の全面に形成された第１の埋設絶縁層と、第２の
半導体素子の形成領域に形成された前記第１の埋設絶縁
層よりも浅い第２の埋設絶縁層とを備えており、第２の
半導体素子領域は第１及び第２の埋設絶縁層によって２
重のＳＯＩ構造になり、１層のＳＯＩ構造の場合よりＳ
ＯＩとしての効果を上げることができ、素子の特性を向
上することができるという効果がある。According to another aspect of the semiconductor device of the present invention, a trench type formed around the second buried insulating layer and extending from one main surface of the semiconductor substrate to a region deeper than the second buried insulating layer. Since the separation region is provided, it is possible to separate the formation region of the second semiconductor element from other regions, and at the same time, the occurrence of stress and crystal defects due to volume expansion during formation of the second embedded insulating layer. Can be suppressed. The semiconductor device further includes a first buried insulating layer formed on the entire surface of the semiconductor substrate and a second buried insulating layer shallower than the first buried insulating layer formed in the formation region of the second semiconductor element. And the second semiconductor element region is formed by the first and second buried insulating layers.
Becomes a double SOI structure, and S is more than in the case of the single-layer SOI structure.
There is an effect that the effect as OI can be improved and the characteristics of the device can be improved.
【００４８】また、請求項５記載の半導体装置の製造方
法によれば、半導体基体のイオンを注入した領域の周囲
に半導体基体の一方主面から前記イオンを注入した領域
より深く溝を掘って溝型分離領域を形成する工程を備え
ており、素子分離用の溝型分離領域を形成するために深
い溝を形成する工程を、ＳＯＩ構造における第２の埋設
絶縁層を形成する工程よりも先に行うようにしたので、
第２の絶縁層形成時における体積膨張による応力や結晶
欠陥の発生を抑えることができ、応力や結晶欠陥の発生
に伴う素子の特性劣化を防止することができるという効
果がある。また、半導体基体の全面に第１の埋設絶縁層
を形成する工程と、前記半導体基体の一方主面から前記
第１の深さよりも浅い第２の深さに達するように、前記
半導体基体の一方主面の一部に選択的にイオンを注入す
る工程と、前記半導体基体のイオンを注入した領域の周
囲に前記半導体基体の一方主面から前記イオンを注入し
た領域より深く溝を掘って溝型分離領域を形成する工程
と、前記溝型分離領域を形成した後、前記半導体基体に
熱処理を施して前記注入したイオンによって第２の埋設
絶縁層を形成する工程を備えており、第２の半導体素子
領域は第１及び第２の埋設絶縁層によって２重のＳＯＩ
構造を容易に形成でき、１層のＳＯＩ構造の場合よりＳ
ＯＩとしての効果を上げることができ、素子の特性を向
上することができるという効果がある。According to a fifth aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein a groove is formed by digging a groove around a region of a semiconductor substrate into which ions have been implanted from a main surface of the semiconductor substrate deeper than a region into which the ions have been implanted. The method includes a step of forming a mold isolation region, and a step of forming a deep groove for forming a groove type isolation region for element isolation is performed before a step of forming a second buried insulating layer in the SOI structure. I decided to do it,
There is an effect that it is possible to suppress the generation of stress and crystal defects due to volume expansion during formation of the second insulating layer, and it is possible to prevent the characteristic deterioration of the element due to the generation of stress and crystal defects. In addition, a step of forming a first buried insulating layer on the entire surface of the semiconductor base, and one of the semiconductor bases is formed so as to reach a second depth shallower than the first depth from one main surface of the semiconductor base. A step of selectively implanting ions in a part of the main surface, and a groove type in which a groove is formed around an ion-implanted region of the semiconductor substrate deeper than a region in which the ions are implanted from one main surface of the semiconductor substrate. The method further comprises the steps of forming an isolation region and, after forming the trench isolation region, subjecting the semiconductor substrate to a heat treatment to form a second buried insulating layer by the implanted ions. The element region has a double SOI by the first and second buried insulating layers.
The structure can be easily formed, and S can be formed more than in the case of the single-layer SOI structure.
There is an effect that the effect as OI can be improved and the characteristics of the device can be improved.
【図１】この発明の第１実施例による半導体装置の製造
方法の主要工程を示す断面図である。FIG. 1 is a sectional view showing main steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
【図２】この発明の第１実施例による半導体装置の製造
方法の主要工程を示す断面図である。FIG. 2 is a cross-sectional view showing the main steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
【図３】この発明の第１実施例による半導体装置の製造
方法の主要工程を示す断面図である。FIG. 3 is a cross-sectional view showing the main steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
【図４】この発明の第２実施例による半導体装置の製造
方法の主要工程を示す断面図である。FIG. 4 is a sectional view showing main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
【図５】この発明の第２実施例による半導体装置の製造
方法の主要工程を示す断面図である。FIG. 5 is a cross-sectional view showing the main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
【図６】この発明の第２実施例による半導体装置の製造
方法の主要工程を示す断面図である。FIG. 6 is a cross-sectional view showing the main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
【図７】この発明の第２実施例による半導体装置の製造
方法の主要工程を示す断面図である。FIG. 7 is a cross-sectional view showing the main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
【図８】ＳＯＩ構造を採用した従来のＭＯＳ型半導体素
子の製造方法の主要工程を示す断面図である。FIG. 8 is a cross-sectional view showing the main steps of a conventional method for manufacturing a MOS type semiconductor device adopting an SOI structure.
【図９】ＳＯＩ構造を採用した従来のＭＯＳ型半導体素
子の製造方法の主要工程を示す断面図である。FIG. 9 is a cross-sectional view showing the main steps of a conventional method for manufacturing a MOS type semiconductor device adopting an SOI structure.
【図１０】ＳＯＩ構造を採用した従来のＭＯＳ型半導体
素子の製造方法の主要工程を示す断面図である。FIG. 10 is a cross-sectional view showing the main steps of a conventional method for manufacturing a MOS type semiconductor device adopting an SOI structure.
【図１１】ＳＯＩ構造を採用した従来のＭＯＳ型半導体
素子の製造方法の主要工程を示す断面図である。FIG. 11 is a cross-sectional view showing main steps of a conventional method for manufacturing a MOS type semiconductor device adopting an SOI structure.
【図１２】ＳＯＩ構造を採用した従来のバイポーラ型半
導体素子の製造方法の主要工程を示す断面図である。FIG. 12 is a cross-sectional view showing the main steps of a conventional method for manufacturing a bipolar semiconductor device having an SOI structure.
【図１３】ＳＯＩ構造を採用した従来のバイポーラ型半
導体素子の製造方法の主要工程を示す断面図である。FIG. 13 is a cross-sectional view showing the main steps of a conventional method for manufacturing a bipolar semiconductor device having an SOI structure.
【図１４】ＳＯＩ構造を採用した従来のバイポーラ型半
導体素子の製造方法の主要工程を示す断面図である。FIG. 14 is a cross-sectional view showing the main steps of a conventional method for manufacturing a bipolar semiconductor device having an SOI structure.
【図１５】ＳＯＩ構造を採用した従来のバイポーラ型半
導体素子の製造方法の主要工程を示す断面図である。FIG. 15 is a cross-sectional view showing the main steps of a conventional method for manufacturing a bipolar semiconductor device having an SOI structure.
【図１６】従来のＢｉＣＭＯＳ型半導体素子の構造を示
す断面図である。FIG. 16 is a cross-sectional view showing the structure of a conventional BiCMOS type semiconductor device.
１ Ｎ- 型シリコン基板 ２ 絶縁層 ３ シリコン層 ４ 素子分離用酸化膜 ５ ゲート絶縁膜 ６ ゲート電極 ７ ソース領域 ８ ドレイン領域 ９ 絶縁膜 １０ ソース電極配線 １１ ゲート電極配線 １２ ドレイン電極配線 ２１ Ｎ+ 埋め込み層 ２２ Ｎ- エピタキシャル層 ２３ 溝型分離領域 ２４ コレクタ電極引き出し領域 ２５ エミッタ領域 ２６ ベース領域 ２８ コレクタ電極配線 ２９ エミッタ電極配線 ３８ ベース電極配線 １００ マスク膜1 N − Type Silicon Substrate 2 Insulating Layer 3 Silicon Layer 4 Oxide Film for Element Isolation 5 Gate Insulating Film 6 Gate Electrode 7 Source Region 8 Drain Region 9 Insulating Film 10 Source Electrode Wiring 11 Gate Electrode Wiring 12 Drain Electrode Wiring 21 N + Buried Layer 22 N - Epitaxial layer 23 Groove-type isolation region 24 Collector electrode extraction region 25 Emitter region 26 Base region 28 Collector electrode wiring 29 Emitter electrode wiring 38 Base electrode wiring 100 Mask film
─────────────────────────────────────────────────────
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【手続補正書】[Procedure amendment]
【提出日】平成４年３月５日[Submission date] March 5, 1992
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００３５[Correction target item name] 0035
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００３５】[0035]
【実施例】以下、この発明の第１実施例を図１乃至図３
を用いて説明する。図１乃至図３に示す断面図は、ＮＰ
ＮバイポーラトランジスタとＰＭＯＳトランジスタを一
つの半導体基体上に形成した場合の半導体装置の製造方
法の主要工程の断面図である。そして、図１乃至図３に
おいて、１はＮ- 型シリコン基板、２ａ，２ｂは酸化膜
絶縁層、３ａ，３ｂはＳＯＩ構造におけるシリコン層、
１００はマスク膜、ＤＯはＮ- 型シリコン基板１に注入
した酸素イオン、ＤＭはＭＯＳトランジスタを形成する
ＭＯＳ型素子形成領域、ＤＢはバイポーラトランジスタ
を形成するバイポーラ型素子形成領域、４〜１２の図１
１と同一の符号は図１１と同一もしくは相当部分を示
し、また２１〜２６及び２８〜３０の図１５と同一の符
号は図１５と同一もしくは相当部分を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.
Will be explained. The sectional views shown in FIGS. 1 to 3 are NPs.
FIG. 9 is a cross-sectional view of main steps of a method for manufacturing a semiconductor device when an N bipolar transistor and a PMOS transistor are formed on one semiconductor substrate. 1 to 3, 1 is an N − -type silicon substrate, 2a and 2b are oxide film insulating layers, 3a and 3b are silicon layers in an SOI structure,
Reference numeral 100 is a mask film, DO is oxygen ions implanted into the N − type silicon substrate 1, DM is a MOS type element formation region for forming a MOS transistor, DB is a bipolar type element formation region for forming a bipolar transistor, and FIGS. 1
Same reference numerals 1 and designate the same or corresponding parts in FIG. 11, also 21 to 26 and the same reference numerals as in FIG. 15 of 28 to 30 denote the same or corresponding parts in FIG 5.
Claims (5)
部の領域に埋設絶縁層を形成したＳＯＩ構造を有する半
導体装置の製造方法であって、 前記半導体基体の前記埋設絶縁層を形成すべき領域にイ
オン注入する工程と、 前記半導体基体の前記イオン注入した領域の周囲に前記
半導体基体の一方主面から前記イオン注入した領域より
深く溝を掘って溝型分離領域を形成する工程と、 前記溝型分離領域を形成した後、前記半導体基体に熱処
理を施して前記注入したイオンにより前記埋設絶縁層を
形成する工程と、 を備えた半導体装置の製造方法。1. A method of manufacturing a semiconductor device having an SOI structure in which a buried insulating layer is formed in a part of a predetermined depth from one main surface of the semiconductor substrate, wherein the buried insulating layer of the semiconductor substrate is formed. Ion-implanting a region to be formed, and forming a groove-type isolation region around the ion-implanted region of the semiconductor substrate by digging a groove deeper than the ion-implanted region from one main surface of the semiconductor substrate. A step of forming a heat treatment on the semiconductor substrate to form the buried insulating layer by the implanted ions after forming the groove type isolation region.
素子と第２の半導体素子とを有する半導体装置であっ
て、 前記半導体基体における前記第１の半導体素子の形成領
域に形成された前記半導体基体の一方主面より第１の深
さにある第１の埋設絶縁層と、 前記第１の埋設絶縁層の周囲に形成された、前記半導体
基体の一方主面から前記第１の埋設絶縁層より深い領域
まで達する溝型分離領域と、 前記半導体基体における前記第２の半導体素子の形成領
域に形成された前記半導体基体の一方主面より第２の深
さにある第２の埋設絶縁層と、 前記第２の埋設絶縁層の周囲に形成された、前記半導体
基体の一方主面から前記第２の埋設絶縁層より深い領域
まで達する溝型分離領域と、 を備えた半導体装置。2. A semiconductor device having a first semiconductor element and a second semiconductor element on one main surface of a semiconductor substrate, the semiconductor device being formed in a formation region of the first semiconductor element in the semiconductor substrate. A first buried insulating layer at a first depth from one main surface of the semiconductor base; and a first buried from the one main surface of the semiconductor base formed around the first buried insulating layer A trench isolation region that reaches a region deeper than the insulating layer, and a second buried insulating layer that is at a second depth from one main surface of the semiconductor substrate formed in the formation region of the second semiconductor element in the semiconductor substrate. A semiconductor device, comprising: a layer; and a trench isolation region formed around the second buried insulating layer and extending from one main surface of the semiconductor substrate to a region deeper than the second buried insulating layer.
素子と第２の半導体素子とを有する半導体装置の製造方
法であって、 前記半導体基体表面に選択的に、前記第１及び第２の半
導体素子の形成領域においてそれぞれ注入深さが異なる
ようにイオンを注入する工程と、 前記注入深さの異なる両イオン注入領域の各々の周囲
に、前記半導体基体の一方主面から各イオン注入領域よ
り深く溝を掘って溝型分離領域を形成する工程と、 前記溝型分離領域を形成した後、前記半導体基体に熱処
理を施して前記注入したイオンによって前記第１及び第
２の半導体素子の形成領域に深さの異なる埋設絶縁層を
形成する工程と、 を備えた半導体装置の製造方法。3. A method of manufacturing a semiconductor device having a first semiconductor element and a second semiconductor element on one main surface of a semiconductor substrate, wherein the first and second semiconductor elements are selectively formed on the surface of the semiconductor substrate. 2. Implanting ions so that the implantation depths are different in the formation regions of the second semiconductor element; and ion implantation from one main surface of the semiconductor substrate around each of the ion implantation regions having different implantation depths. Forming a groove-type isolation region by digging a groove deeper than the region; and, after forming the groove-type isolation region, heat-treating the semiconductor substrate and implanting the ions into the first and second semiconductor elements. A method of manufacturing a semiconductor device, comprising: forming buried insulating layers having different depths in a formation region.
素子と第２の半導体素子とを有する半導体装置であっ
て、 前記半導体基体の一方主面から第１の深さにおいて、前
記半導体基体の全面に形成された第１の埋設絶縁層と、 前記半導体基体の一方主面から前記第１の深さよりも浅
い第２の深さにおいて、前記半導体基体の一部に形成さ
れた第２の埋設絶縁層と、 前記第２の埋設絶縁層の周囲に形成された、前記半導体
基体の一方主面から前記第２の埋設絶縁層より深い領域
まで達する溝型分離領域と、 前記第２の埋設絶縁層の無い前記第１の埋設絶縁層上の
前記半導体基体に設けられた前記第１の半導体素子の形
成領域と、 前記第２の埋設絶縁層上の前記半導体基体に設けられた
前記第２の半導体素子の形成領域と、 を備えた半導体装置。4. A semiconductor device having a first semiconductor element and a second semiconductor element on one main surface of a semiconductor substrate, wherein the semiconductor is at a first depth from one main surface of the semiconductor substrate. A first buried insulating layer formed on the entire surface of the base; and a second buried insulating layer formed on a part of the semiconductor base at a second depth shallower than the first depth from one main surface of the semiconductor base. A buried insulating layer, a groove-type isolation region formed around the second buried insulating layer and extending from one main surface of the semiconductor substrate to a region deeper than the second buried insulating layer, A formation region of the first semiconductor element provided on the semiconductor substrate on the first buried insulating layer without a buried insulating layer; and a first region provided on the semiconductor substrate on the second buried insulating layer. And a semiconductor device forming region .
素子と第２の半導体素子とを有する半導体装置の製造方
法であって、 前記半導体基体の一方主面から第１の深さにおいて、前
記半導体基体の全面に第１の埋設絶縁層を形成する工程
と、 前記半導体基体の一方主面から前記第１の深さよりも浅
い第２の深さに達するように、前記半導体基体の一方主
面の一部に選択的にイオンを注入する工程と、 前記半導体基体の前記イオンを注入した領域の周囲に前
記半導体基体の一方主面から前記イオンを注入した領域
より深く溝を掘って溝型分離領域を形成する工程と、 前記溝型分離領域を形成した後、前記半導体基体に熱処
理を施して前記注入したイオンによって第２の埋設絶縁
層を形成する工程と、 前記第２の埋設絶縁層の無い前記第１の埋設絶縁層上の
前記半導体基体に前記第１の半導体素子を形成する工程
と、 前記第２の埋設絶縁層上の前記半導体基体に前記第２の
半導体素子を形成する工程と、 を備えた半導体装置の製造方法。5. A method of manufacturing a semiconductor device having a first semiconductor element and a second semiconductor element on one main surface of a semiconductor substrate, the method comprising: A step of forming a first buried insulating layer on the entire surface of the semiconductor substrate, and one of the semiconductor substrate so as to reach a second depth shallower than the first depth from one main surface of the semiconductor substrate. A step of selectively implanting ions into a part of the main surface, and digging a groove around the ion-implanted region of the semiconductor substrate deeper than the region into which the ions are implanted from one main surface of the semiconductor substrate; A step of forming a mold isolation region; a step of forming a second buried insulating layer by performing heat treatment on the semiconductor substrate to form the implanted ions after forming the trench type separation region; and the second buried insulation. The first padding without layers A semiconductor device comprising: a step of forming the first semiconductor element on the semiconductor base on an insulating layer; and a step of forming the second semiconductor element on the semiconductor base on the second embedded insulating layer. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3287614A JPH05129536A (en) | 1991-11-01 | 1991-11-01 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3287614A JPH05129536A (en) | 1991-11-01 | 1991-11-01 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129536A true JPH05129536A (en) | 1993-05-25 |
Family
ID=17719553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3287614A Pending JPH05129536A (en) | 1991-11-01 | 1991-11-01 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129536A (en) |
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