JPH05102473A - Manufacture of mos type semiconductor device - Google Patents
Manufacture of mos type semiconductor deviceInfo
- Publication number
- JPH05102473A JPH05102473A JP28390191A JP28390191A JPH05102473A JP H05102473 A JPH05102473 A JP H05102473A JP 28390191 A JP28390191 A JP 28390191A JP 28390191 A JP28390191 A JP 28390191A JP H05102473 A JPH05102473 A JP H05102473A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- silicon film
- polycrystalline silicon
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、例えば、短チャネルＭ
ＯＳトランジスタにおけるしきい値電圧の低下やパンチ
スルー耐圧の低下を防止した構造のＭＯＳ型半導体装置
の製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to, for example, a short channel M.
The present invention relates to a method for manufacturing a MOS semiconductor device having a structure that prevents a decrease in threshold voltage and a decrease in punch-through breakdown voltage in an OS transistor.
【０００２】[0002]
【従来の技術】ＭＯＳ型半導体装置の微細化に伴って、
例えばＭＯＳトランジスタのチャネル長が短くなると、
ドレイン領域からの空乏層がソース領域にまで達し易く
なり、しきい値電圧の低下やパンチスルー耐圧の低下が
生じる。2. Description of the Related Art With the miniaturization of MOS semiconductor devices,
For example, if the channel length of a MOS transistor becomes short,
The depletion layer from the drain region easily reaches the source region, and the threshold voltage and punch-through breakdown voltage are reduced.
【０００３】このようなしきい値電圧の低下やパンチス
ルー耐圧の低下を防止するために、半導体基板自体の不
純物濃度を高くしてドレイン領域からの空乏層の伸びを
抑制することが考えられるが、半導体基板自体の不純物
濃度を高くすると、半導体基板内に形成したソース・ド
レイン領域での接合容量が増大して、素子の動作速度が
低下するという問題が生じる。In order to prevent such a decrease in threshold voltage and a decrease in punch-through breakdown voltage, it is considered that the impurity concentration of the semiconductor substrate itself is increased to suppress the extension of the depletion layer from the drain region. When the impurity concentration of the semiconductor substrate itself is increased, the junction capacitance in the source / drain regions formed in the semiconductor substrate increases, which causes a problem that the operating speed of the device decreases.
【０００４】そこで、特開平１−１２３４７４号公報に
は、ゲート電極直下のチャネル領域下に、半導体基板の
不純物濃度が高い高濃度領域を部分的に形成することが
提案されている。Therefore, Japanese Unexamined Patent Publication (Kokai) No. 1-123474 proposes to partially form a high-concentration region having a high impurity concentration in the semiconductor substrate under the channel region immediately below the gate electrode.
【０００５】この公報に記載の製造方法では、まず、図
２（ａ）に示すように、ｐ型のＳｉ基板２１の表面にゲ
ート酸化膜であるＳｉＯ2 膜２２を形成した後、Ｓｉ基
板２１の全面からｐ型の不純物をイオン注入して、Ｓｉ
基板２１の比較的深い位置に高濃度のｐ+ 層２３を形成
する。In the manufacturing method described in this publication, first, as shown in FIG. 2A, a SiO 2 film 22 as a gate oxide film is formed on the surface of a p-type Si substrate 21, and then the Si substrate 21 is formed. P-type impurities are ion-implanted from the entire surface of the
A high concentration p + layer 23 is formed at a relatively deep position of the substrate 21.
【０００６】次いで、図２（ｂ）に示すように、多結晶
Ｓｉ膜２４でゲート電極を形成した後、この多結晶Ｓｉ
膜２４をマスクとしてｎ型の不純物をイオン注入し、ｐ
+ 層２３のうちで多結晶Ｓｉ膜２４の直下の部分以外の
部分を補償層２５とする。この結果、ゲート電極直下の
チャネル領域下にのみ高濃度のｐ+ 層２３が残る。Next, as shown in FIG. 2B, after a gate electrode is formed of the polycrystalline Si film 24, this polycrystalline Si film 24 is formed.
N-type impurities are ion-implanted using the film 24 as a mask, and p
A portion of the + layer 23 other than the portion immediately below the polycrystalline Si film 24 is used as the compensation layer 25. As a result, the high-concentration p + layer 23 remains only under the channel region immediately below the gate electrode.
【０００７】そこで、この高濃度のｐ+ 層２３と直接接
触しないようにソース・ドレイン領域を形成することが
でき、しかも、この高濃度のｐ+ 層２３の存在によって
ドレイン領域からの空乏層の伸びを抑制することができ
るので、ソース・ドレイン領域での接合容量を増大させ
ることなく、しきい値電圧の低下やパンチスルー耐圧の
低下を防止することができる。[0007] Therefore, it is possible to form the source and drain regions so as not to directly contact with the high concentration p + layer 23, moreover, the depletion layer from the drain region by the presence of the high concentration p + layer 23 Since the elongation can be suppressed, it is possible to prevent the threshold voltage and the punch-through breakdown voltage from decreasing without increasing the junction capacitance in the source / drain regions.
【０００８】[0008]
【発明が解決しようとする課題】ところが、上述した従
来の製造方法では、ゲート電極を形成する前に、Ｓｉ基
板２１の全面からイオン注入を行って、ｐ+ 層２３を形
成するため、ゲート電極形成後に、ｎ型不純物のイオン
注入を行って、ゲート電極直下の部分以外のｐ+ 層２３
の部分を補償層２５とする必要がある。However, in the above-described conventional manufacturing method, since the p + layer 23 is formed by performing ion implantation from the entire surface of the Si substrate 21 before forming the gate electrode, the gate electrode is formed. After the formation, ion implantation of n-type impurities is performed to form the p + layer 23 other than the portion immediately below the gate electrode.
It is necessary to make the part of the compensation layer 25.
【０００９】しかし、このような逆導電型のイオン注入
による不純物補償では、その逆導電型イオン注入の条件
制御が非常に難しく、その結果、不純物補償を高い精度
で行うことができないので、信頼性の高いＭＯＳトラン
ジスタを得ることができなかった。However, in the impurity compensation by the reverse conductivity type ion implantation as described above, it is very difficult to control the conditions of the reverse conductivity type ion implantation, and as a result, the impurity compensation cannot be performed with high accuracy, so that the reliability is high. It was not possible to obtain a high MOS transistor.
【００１０】また、上述した従来の製造方法では、不純
物のイオン注入を、ゲート電極形成前と形成後で、２回
行わなければならないために、Ｓｉ基板２１の受けるダ
メージが大きくなり、ＭＯＳトランジスタの特性の点で
も問題があった。Further, in the above-described conventional manufacturing method, since the ion implantation of the impurity has to be performed twice before and after the gate electrode is formed, the Si substrate 21 is greatly damaged and the MOS transistor is damaged. There was also a problem in terms of characteristics.
【００１１】そこで、本発明の目的は、ゲート電極直下
の半導体基板内に高濃度領域を形成することによって、
例えばＭＯＳトランジスタのしきい値電圧の低下やパン
チスルー耐圧の低下を防止する構造を、信頼性が高く且
つ特性の劣化も少ない方法で製造することができるＭＯ
Ｓ型半導体装置の製造方法を提供することである。Therefore, an object of the present invention is to form a high-concentration region in the semiconductor substrate just below the gate electrode,
For example, a structure that prevents the threshold voltage of a MOS transistor from decreasing and the punch-through breakdown voltage from decreasing can be manufactured by a method with high reliability and little deterioration in characteristics.
A method of manufacturing an S-type semiconductor device is provided.
【００１２】[0012]
【課題を解決するための手段】上述した課題を解決する
ために、本発明のＭＯＳ型半導体装置の製造方法は、半
導体基板上に形成されたゲート絶縁膜上に第１の多結晶
シリコン膜を形成する工程と、ゲート電極のパターンに
対応したパターンの開口を有するマスク層を前記第１の
多結晶シリコン膜上に形成する工程と、前記マスク層を
マスクとしてイオン注入を行い、前記半導体基板の内部
の所定深さ位置に、前記半導体基板と同一の導電型で且
つ不純物濃度の高い高濃度領域を形成する工程と、前記
マスク層の前記開口の内部の前記第１の多結晶シリコン
膜上に、この第１の多結晶シリコン膜を種結晶として第
２の多結晶シリコン膜を選択成長させる工程と、前記マ
スク層、並びに、前記第２の多結晶シリコン膜直下の部
分を除いた前記第１の多結晶シリコン膜の部分を除去す
る工程と、残った前記第１の多結晶シリコン膜の部分及
び前記第２の多結晶シリコン膜から構成されるゲート電
極をイオン注入のマスクとして用い、前記半導体基板内
に所定深さのソース・ドレイン領域を形成する工程とを
有している。In order to solve the above-mentioned problems, a method for manufacturing a MOS type semiconductor device according to the present invention comprises a first polycrystalline silicon film formed on a gate insulating film formed on a semiconductor substrate. A step of forming, a step of forming a mask layer having an opening of a pattern corresponding to the pattern of the gate electrode on the first polycrystalline silicon film, ion implantation using the mask layer as a mask, Forming a high-concentration region of the same conductivity type as the semiconductor substrate and having a high impurity concentration at a predetermined depth position inside, and on the first polycrystalline silicon film inside the opening of the mask layer. , A step of selectively growing the second polycrystalline silicon film by using the first polycrystalline silicon film as a seed crystal, the mask layer, and the first portion excluding the portion immediately below the second polycrystalline silicon film. Removing the part of the polycrystalline silicon film, and using the gate electrode composed of the remaining part of the first polycrystalline silicon film and the remaining part of the second polycrystalline silicon film as a mask for ion implantation, Forming a source / drain region having a predetermined depth in the substrate.
【００１３】[0013]
【作用】本発明のＭＯＳ型半導体装置の製造方法におい
ては、ゲート電極のパターンに対応したパターンの開口
を有するマスク層をマスクとして用いてイオン注入を行
い、これによって、ゲート電極直下の半導体基板内に、
その半導体基板と同一導電型の高濃度領域を形成し、し
かる後、そのマスク層の開口内で多結晶シリコンを選択
成長させることにより、ゲート電極を形成する。In the method of manufacturing a MOS type semiconductor device according to the present invention, ion implantation is performed using a mask layer having a pattern opening corresponding to the pattern of the gate electrode as a mask, whereby the semiconductor substrate immediately below the gate electrode is formed. To
A high-concentration region of the same conductivity type as that of the semiconductor substrate is formed, and then, polycrystalline silicon is selectively grown in the opening of the mask layer to form a gate electrode.
【００１４】従って、１回のイオン注入によって、ゲー
ト電極直下の所定位置にのみ高濃度領域を形成すること
ができ、従来のような不純物補償を行う必要はない。Therefore, the high-concentration region can be formed only at a predetermined position just below the gate electrode by one-time ion implantation, and it is not necessary to perform impurity compensation as in the conventional case.
【００１５】しかも、イオン注入の際に用いたマスク層
を、ゲート電極形成の際にも利用するので、工程数の増
加はなく、また、高濃度領域とゲート電極との位置合わ
せも自己整合的に行われる。Moreover, since the mask layer used for the ion implantation is also used for forming the gate electrode, the number of steps is not increased, and the alignment between the high concentration region and the gate electrode is self-aligned. To be done.
【００１６】[0016]
【実施例】以下、本発明をＭＯＳトランジスタの製造方
法に適用した一実施例を図１を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a method for manufacturing a MOS transistor will be described below with reference to FIG.
【００１７】まず、図１（ａ）に示すように、ｐ型のＳ
ｉ基板１１の表面にゲート酸化膜であるＳｉＯ2 膜１２
を形成する。First, as shown in FIG. 1A, p-type S
A SiO 2 film 12 as a gate oxide film is formed on the surface of the i substrate 11.
To form.
【００１８】次に、図１（ｂ）に示すように、このＳｉ
Ｏ2 膜１２の上に薄い多結晶Ｓｉ膜１３を形成する。な
お、この多結晶Ｓｉ膜１３は、後述する如く、その上に
第２の多結晶Ｓｉ膜を選択成長させる時に、その種結晶
となるに充分な膜厚であれば良い。一方、この多結晶Ｓ
ｉ膜１３のゲート電極部分以外の部分は後に全てエッチ
ング除去されるので、そのエッチングを考慮すると、そ
の膜厚は、できるだけ薄いのが好ましい。Next, as shown in FIG.
A thin polycrystalline Si film 13 is formed on the O 2 film 12. As will be described later, the polycrystalline Si film 13 may have a film thickness sufficient to become a seed crystal when the second polycrystalline Si film is selectively grown thereon. On the other hand, this polycrystalline S
Since the i-film 13 except the gate electrode part is etched away later, it is preferable that the film thickness is as thin as possible in consideration of the etching.
【００１９】次に、図１（ｃ）に示すように、この多結
晶Ｓｉ膜１３の上にＳｉＯ2 膜１４を形成し、このＳｉ
Ｏ2 膜１４に、ゲート電極のパターンに対応したパター
ンの開口１４ａを形成する。即ち、ＳｉＯ2 膜１４を、
ゲート電極のパターンを反転させたパターンのマスクを
用いてエッチングし、開口１４ａを形成する。Next, as shown in FIG. 1C, a SiO 2 film 14 is formed on the polycrystalline Si film 13, and the Si 2 film 14 is formed.
An opening 14a having a pattern corresponding to the pattern of the gate electrode is formed in the O 2 film 14. That is, the SiO 2 film 14 is
Etching is performed using a mask having a pattern obtained by inverting the pattern of the gate electrode to form the opening 14a.
【００２０】次に、図１（ｄ）に示すように、このＳｉ
Ｏ2 膜１４をマスクとして用い、ｐ型の不純物であるホ
ウ素を所定のエネルギーでＳｉ基板１１にイオン注入す
ることにより、Ｓｉ基板１１よりも不純物濃度が高いｐ
+ 型の高濃度領域１５を、Ｓｉ基板１１の所定の深さ位
置に形成する。Next, as shown in FIG.
Using the O 2 film 14 as a mask, boron, which is a p-type impurity, is ion-implanted into the Si substrate 11 with a predetermined energy, so that the impurity concentration of p is higher than that of the Si substrate 11.
The + type high concentration region 15 is formed at a predetermined depth position of the Si substrate 11.
【００２１】次に、図１（ｅ）に示すように、ＳｉＯ2
膜の開口１４ａ内に露出している多結晶Ｓｉ膜１３を種
結晶として、開口１４ａ内にのみ第２の多結晶Ｓｉ膜を
選択成長させる。Next, as shown in FIG. 1 (e), SiO 2
With the polycrystalline Si film 13 exposed in the opening 14a of the film as a seed crystal, the second polycrystalline Si film is selectively grown only in the opening 14a.
【００２２】次に、図１（ｆ）に示すように、ＳｉＯ2
膜１４をエッチング除去し、更に、ＳｉＯ2 膜１４の下
にあった多結晶Ｓｉ膜１３の部分もエッチング除去す
る。これにより、開口１４ａのパターンに対応したパタ
ーンの第２の多結晶Ｓｉ膜とその下の多結晶Ｓｉ膜１３
の部分がゲート電極１６として残る。Next, as shown in FIG. 1 (f), SiO 2
The film 14 is removed by etching, and the portion of the polycrystalline Si film 13 under the SiO 2 film 14 is also removed by etching. As a result, the second polycrystalline Si film having a pattern corresponding to the pattern of the opening 14a and the polycrystalline Si film 13 thereunder are formed.
Remains as the gate electrode 16.
【００２３】次に、同図に示すように、このゲート電極
１６をマスクとしてｎ型の不純物をＳｉ基板１１に低濃
度にイオン注入することにより、ｎ- 層１７を、ｐ+ 型
の高濃度領域１５よりも浅い位置まで形成する。Next, as shown in the same figure, by using this gate electrode 16 as a mask, n-type impurities are ion-implanted into the Si substrate 11 at a low concentration, so that the n − layer 17 is made into a p + -type high concentration. It is formed to a position shallower than the region 15.
【００２４】その後、ＳｉＯ2 からなるサイドウォール
１８をゲート電極１６の側部に形成し、このサイドウォ
ール１８とゲート電極１６をマスクとして、ｎ型の不純
物をＳｉ基板１１に高濃度にイオン注入することによ
り、ｎ+ 層１９を形成する。After that, a side wall 18 made of SiO 2 is formed on the side portion of the gate electrode 16, and n-type impurities are ion-implanted into the Si substrate 11 at a high concentration using the side wall 18 and the gate electrode 16 as a mask. As a result, the n + layer 19 is formed.
【００２５】このようにして、ｎ- 層１７とｎ+ 層１９
とからなるソース・ドレイン領域を形成し、ＬＤＤ構造
のＭＯＳトランジスタを形成する。In this way, the n − layer 17 and the n + layer 19 are formed.
A source / drain region composed of and is formed to form a MOS transistor having an LDD structure.
【００２６】なお、既述した如く、ｐ+ 型の高濃度領域
１５は、ゲート電極のパターンに対応したパターンの開
口１４ａを通じて、Ｓｉ基板１１の比較的深い位置に形
成される。一方、ｎ- 層１７は、ゲート電極１６をマス
クとして形成されるが、ｐ+ 型の高濃度領域１５よりも
浅い位置までしか形成されず、また、ｎ+ 層１９は、ゲ
ート電極１６とサイドウォール１８をマスクとして形成
される。従って、ｎ- 層１７及びｎ+ 層１９の何れも
が、ｐ+ 型の高濃度領域１５から離間した状態で形成さ
れ、ソース・ドレイン領域での接合容量の増大は生じな
い。As described above, the p + -type high concentration region 15 is formed at a relatively deep position of the Si substrate 11 through the opening 14a having a pattern corresponding to the pattern of the gate electrode. On the other hand, the n − layer 17 is formed using the gate electrode 16 as a mask, but is formed only to a position shallower than the p + type high-concentration region 15, and the n + layer 19 is formed on the gate electrode 16 and the side. The wall 18 is formed as a mask. Therefore, both the n − layer 17 and the n + layer 19 are formed apart from the p + -type high concentration region 15, and the junction capacitance in the source / drain region does not increase.
【００２７】[0027]
【発明の効果】本発明のＭＯＳ型半導体装置の製造方法
によれば、ゲート電極直下の半導体基板内に形成する高
濃度領域を、ゲート電極形成前の１回のイオン注入工程
で形成することができ、従来のような不純物補償を行う
必要がない。従って、不純物補償による信頼性の低下が
なく、また、不純物補償のためのイオン注入による半導
体基板の損傷も生じない。According to the method of manufacturing a MOS semiconductor device of the present invention, the high concentration region formed in the semiconductor substrate immediately below the gate electrode can be formed by one ion implantation step before the gate electrode is formed. Therefore, it is not necessary to perform the impurity compensation as in the conventional case. Therefore, the reliability is not lowered by the impurity compensation, and the semiconductor substrate is not damaged by the ion implantation for the impurity compensation.
【００２８】この結果、しきい値電圧の低下やパンチス
ルー耐圧の低下が防止されたＭＯＳ型半導体装置を、信
頼性が高く且つ特性の劣化も少ない方法で製造すること
ができる。As a result, it is possible to manufacture the MOS type semiconductor device in which the lowering of the threshold voltage and the lowering of the punch-through breakdown voltage are prevented by a method having high reliability and less deterioration in characteristics.
【図１】本発明の一実施例によるＭＯＳトランジスタの
製造方法を工程順に示す断面図である。FIG. 1 is a cross-sectional view showing a method of manufacturing a MOS transistor according to an embodiment of the present invention in the order of steps.
【図２】従来の製造方法を工程順に示す断面図である。FIG. 2 is a cross-sectional view showing a conventional manufacturing method in process order.
１１ Ｓｉ基板 １２ ＳｉＯ2 膜 １３ 多結晶Ｓｉ膜 １４ ＳｉＯ2 膜 １４ａ 開口 １５ ｐ+ 型高濃度領域 １６ ゲート電極 １７ ｎ- 層 １８ サイドウォール １９ ｎ+ 層Reference Signs List 11 Si substrate 12 SiO 2 film 13 Polycrystalline Si film 14 SiO 2 film 14a Opening 15 p + type high concentration region 16 Gate electrode 17 n − layer 18 Sidewall 19 n + layer
Claims (1)
上に第１の多結晶シリコン膜を形成する工程と、 ゲート電極のパターンに対応したパターンの開口を有す
るマスク層を前記第１の多結晶シリコン膜上に形成する
工程と、 前記マスク層をマスクとしてイオン注入を行い、前記半
導体基板の内部の所定深さ位置に、前記半導体基板と同
一の導電型で且つ不純物濃度の高い高濃度領域を形成す
る工程と、 前記マスク層の前記開口の内部の前記第１の多結晶シリ
コン膜上に、この第１の多結晶シリコン膜を種結晶とし
て第２の多結晶シリコン膜を選択成長させる工程と、 前記マスク層、並びに、前記第２の多結晶シリコン膜直
下の部分を除いた前記第１の多結晶シリコン膜の部分を
除去する工程と、 残った前記第１の多結晶シリコン膜の部分及び前記第２
の多結晶シリコン膜から構成されるゲート電極をイオン
注入のマスクとして用い、前記半導体基板内に所定深さ
のソース・ドレイン領域を形成する工程とを有すること
を特徴とするＭＯＳ型半導体装置の製造方法。1. A step of forming a first polycrystalline silicon film on a gate insulating film formed on a semiconductor substrate, and a mask layer having an opening of a pattern corresponding to a pattern of a gate electrode is formed on the first polycrystalline silicon film. A step of forming on the crystalline silicon film, and ion implantation using the mask layer as a mask to form a high-concentration region having the same conductivity type as the semiconductor substrate and a high impurity concentration at a predetermined depth position inside the semiconductor substrate. And a step of selectively growing a second polycrystalline silicon film on the first polycrystalline silicon film inside the opening of the mask layer using the first polycrystalline silicon film as a seed crystal. And a step of removing the mask layer and the portion of the first polycrystalline silicon film excluding the portion immediately below the second polycrystalline silicon film, and the remaining portion of the first polycrystalline silicon film Fine the second
Forming a source / drain region of a predetermined depth in the semiconductor substrate by using the gate electrode composed of the polycrystalline silicon film as a mask for ion implantation. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28390191A JPH05102473A (en) | 1991-10-04 | 1991-10-04 | Manufacture of mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28390191A JPH05102473A (en) | 1991-10-04 | 1991-10-04 | Manufacture of mos type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05102473A true JPH05102473A (en) | 1993-04-23 |
Family
ID=17671654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28390191A Withdrawn JPH05102473A (en) | 1991-10-04 | 1991-10-04 | Manufacture of mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05102473A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100955937B1 (en) * | 2008-01-18 | 2010-05-03 | 주식회사 하이닉스반도체 | Method of manufacturing MOSET device |
-
1991
- 1991-10-04 JP JP28390191A patent/JPH05102473A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100955937B1 (en) * | 2008-01-18 | 2010-05-03 | 주식회사 하이닉스반도체 | Method of manufacturing MOSET device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990107 |