JPH0497588A - Solder resist formation method - Google Patents
Solder resist formation methodInfo
- Publication number
- JPH0497588A JPH0497588A JP21557490A JP21557490A JPH0497588A JP H0497588 A JPH0497588 A JP H0497588A JP 21557490 A JP21557490 A JP 21557490A JP 21557490 A JP21557490 A JP 21557490A JP H0497588 A JPH0497588 A JP H0497588A
- Authority
- JP
- Japan
- Prior art keywords
- solder resist
- via hole
- resist ink
- mask film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims description 14
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000005507 spraying Methods 0.000 claims description 5
- 239000007921 spray Substances 0.000 abstract description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はソルダレジストの形成方法に関し、特に写真現
像法によるソルダレジストの形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of forming a solder resist, and particularly to a method of forming a solder resist using a photographic development method.
従来ソルダレジストの形成方法は、スクリーン印刷法と
写真現像法との２方法が採用されて来たが、プリント板
の高密度化１表面実装技術の進展により、現在では写真
現像法が主流になりつつある。Traditionally, two methods have been used to form solder resist: screen printing and photo development, but due to the increased density of printed circuit boards and advances in surface mounting technology, photo development has now become mainstream. It's coming.
写真現像法は、第２図（ａ＞の如く、まず、回路パター
ン２．スルーホール、バイアホール３が形成された基板
１にソルダーレジストインク４を塗布する。塗布方法と
しては、スクリーン印刷。In the photo development method, as shown in FIG. 2 (a), first, a solder resist ink 4 is applied to a substrate 1 on which a circuit pattern 2, through holes, and via holes 3 are formed.The application method is screen printing.
カーテンコーター、ロールコータ−、スプレーコーター
が用いられている。Curtain coaters, roll coaters, and spray coaters are used.
しかしながら、近年の表面実装技術の進展は、狭小ピッ
チ間のはんだブリッジを防止する目的で、パッド間への
ソルダレジストライン形成が不可欠になっており、この
ため、０．１ｍｍがそれ以下の細いソルダレジストライ
ンの形成が比較的容易なスプレーコーターの採用が増加
しつつある。However, with recent advances in surface mounting technology, it has become essential to form solder resist lines between pads in order to prevent solder bridges between narrow pitches. Spray coaters, which can relatively easily form resist lines, are increasingly being used.
塗布方法にかかわらず、塗布後、溶剤分を揮発させる指
触乾燥を行ない、さらに、第２図（ｂ）の如く、マスク
フィルム８を基板１に接合して露光し、次いで第２図（
Ｃ）の如く、現像、硬化を行なって所定のパターン形状
のソルダレジストマを形成する。Regardless of the coating method, after coating, dry to the touch to volatilize the solvent, then bond the mask film 8 to the substrate 1 and expose to light as shown in FIG. 2(b).
As shown in C), development and curing are performed to form a solder resist in a predetermined pattern shape.
上述した従来のソルダレジスト形成方法には、以下の欠
点があった。The conventional solder resist forming method described above had the following drawbacks.
ソルダレジストインクの塗布方法としてスプレーコータ
ーを採用すると、バイアホールの内壁面には、バイアホ
ール全体を露光しても第２図（Ｃ）の如く、ソルダレジ
ストマを形成することができなかった。この原因は、ス
プレー塗布ではバイアホール内壁面には、塗布後、穴壁
に沿って数μｍ程度しか付着せず、また、露光による光
量も光の方向とスルーホール穴壁とが平行であるため、
ソルダレジストインクが受ける光量が弱く感光が不十分
な結果、現像後に内壁面のソルダレジストインクが除去
されてしまうためである６部品を実装しないスルーホー
ル、即ち、バイアホールは、フローはんだ付は時、はん
だが部品面に昇ってこないようにするため、バイアホー
ル内壁面全面をソルダーマスクでおおうかバイアホール
をテントすることが必要である。When a spray coater was used as a method for applying the solder resist ink, no solder resist could be formed on the inner wall surface of the via hole, as shown in FIG. 2(C), even if the entire via hole was exposed. The reason for this is that spray coating only adheres to the inner wall surface of the via hole by a few micrometers along the hole wall after coating, and the amount of light from exposure is also because the direction of the light is parallel to the wall of the through hole. ,
This is because the amount of light received by the solder resist ink is weak and the exposure is insufficient, resulting in the solder resist ink on the inner wall surface being removed after development. To prevent solder from rising to the component surface, it is necessary to cover the entire inner wall of the via hole with a solder mask or to tent the via hole.
スプレー塗布は、穴内へのインク付着量が少ないため、
現像時間が短かいことや、回路の凹凸に沿って均一に塗
膜が形成でき、回路上の膜厚を一定以上に確保すること
が容易なこと、さらに、細線形成も比較的容易であるこ
と等のため採用されてきているものであるが、前述した
バイアホールの被膜性のため適用を限定せざるを得なか
った。Spray application has a small amount of ink adhering to the hole, so
The development time is short, the coating film can be formed uniformly along the irregularities of the circuit, it is easy to maintain a certain film thickness on the circuit, and it is also relatively easy to form fine lines. However, its application has been limited due to the coating properties of the via holes mentioned above.
本発明の目的は、バイアホール内壁面をツルタレシスト
で被膜することが可能なソルダレジストの形成方法を提
供することにある。An object of the present invention is to provide a method for forming a solder resist that allows the inner wall surface of a via hole to be coated with a tsurutaresist.
本発明のソルダレジスト形成方法は、回路パターン、部
品実装用スルーホール、バイアホールか形成された基板
にスプレー塗布により該基板の表裏両面および前記バイ
アホール穴壁面に感光性のソルダレジストインクを全面
塗布する工程と、前記基板に第１のマスクフィルムを接
合し前記バイアホール穴壁面の前記ソルダレジストイン
クを露光する工程と、前記基板に第２のマスクフィルム
を接合し表裏両面の前記ソルダレジストインクを露光す
る工程と、前記露光したソルダレジストインクを現像し
硬化させる工程とを含んで構成されている。The solder resist forming method of the present invention is to apply a photosensitive solder resist ink over the entire surface of the board on which circuit patterns, through holes for component mounting, and via holes have been formed by spray coating on both the front and back surfaces of the board and on the wall surfaces of the via holes. bonding a first mask film to the substrate and exposing the solder resist ink on the wall surface of the via hole; bonding a second mask film to the substrate and applying the solder resist ink on both the front and back surfaces. The method includes a step of exposing to light, and a step of developing and curing the exposed solder resist ink.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の第１の実施例を説明す
る工程順に示した断面図である。FIGS. 1(a) to 1(d) are sectional views showing a first embodiment of the present invention in order of steps.
第１の実施側番よ、まず、第１図（ａ）の如く、スプレ
ー塗布により、基板１の表裏両面およびバイアホール３
の内壁面に感光性ソルダレジストインク４を全面塗布す
る。For the first implementation side, first, as shown in FIG.
A photosensitive solder resist ink 4 is applied to the entire inner wall surface.
次に、第１図（ｂ）の如く、バイアホール３の内壁面を
ソルダレジストインク４で被膜すべきバイアホール３の
位置にのみ透明である第１のマスクフィルム５を基板１
に接合し、バイアホール３の内壁面に光が当たるように
散乱光を照射してバイアホール３の内壁面のソルダレジ
ストインク４を露光する。Next, as shown in FIG. 1(b), a transparent first mask film 5 is applied to the substrate 1 only at the position of the via hole 3 where the inner wall surface of the via hole 3 is to be coated with the solder resist ink 4.
, and the solder resist ink 4 on the inner wall surface of the via hole 3 is exposed by irradiating scattered light so that the light hits the inner wall surface of the via hole 3 .
次いで、第１図（Ｃ）の如く、第２のマスクフィルム６
を基板１に接合し、基板１の表裏両面のソルダレジスト
インク４を所定のパターン形状で露光する。Next, as shown in FIG. 1(C), a second mask film 6 is applied.
is bonded to the substrate 1, and the solder resist ink 4 on both the front and back surfaces of the substrate 1 is exposed in a predetermined pattern shape.
次に、第１図（ｄ）の如く、現像し、熱または熱と紫外
線とを併用してソルダレジストインク４を硬化してソル
ダレジスト７を形成した。Next, as shown in FIG. 1(d), the solder resist ink 4 was developed and cured using heat or a combination of heat and ultraviolet rays to form a solder resist 7.
尚、第１のマスクフィルム５の透光部の大きさは、バイ
アホール３と同径、ないしは、バイアホール３のランド
径と同径の範囲のものを採用することが、バイアホール
３の内壁を確実に露光すること等から良い結果が得られ
た。It should be noted that the size of the transparent portion of the first mask film 5 should be the same diameter as the via hole 3 or within the same diameter range as the land diameter of the via hole 3. Good results were obtained by ensuring reliable exposure.
第２の実施例は、第１の実施例と同様、第１図（ａ）の
如く、スプレー塗布によりソルダレジストインク４を全
面塗布する。In the second embodiment, as in the first embodiment, solder resist ink 4 is applied over the entire surface by spray coating, as shown in FIG. 1(a).
次に、第２のマスクフィルム６を基板１に接合して、基
板１の表裏両面のソルダレジストインク４を所定のパタ
ーン形状で露光する。Next, the second mask film 6 is bonded to the substrate 1, and the solder resist ink 4 on both the front and back surfaces of the substrate 1 is exposed in a predetermined pattern shape.
次いで、第１の実施例と同様の第１のマスフィルム５を
用いて第１のマスクフィルム５を基板１に接合して、バ
イアホール３の内壁面に光が当たるよう散乱光を照射し
てバイアホール３の内壁面のソルダレジストインク４を
露光する
以下、第１の実施例と同様、現像、硬化作業を行なって
ソルダレジスト７を形成しな。Next, the first mask film 5 is bonded to the substrate 1 using the same first mass film 5 as in the first embodiment, and scattered light is irradiated so that the light hits the inner wall surface of the via hole 3. After exposing the solder resist ink 4 on the inner wall surface of the via hole 3, development and curing operations are performed to form the solder resist 7 in the same manner as in the first embodiment.
以上の説明から明らかなように本発明は、基板にスプレ
ー塗布により基板の表裏両面およびバイアホールの穴壁
面に感光性のソルダレジストインクを全面塗布する工程
と、基板に第１のマスクフィルムを接合しバイアホール
壁面のソルダレジストインクを露光する工程と、基板に
第２のマスクフィルムを接合し表裏両面のソルダレジス
トインクを露光する工程とを設けることにより、バイア
ホールの内壁面をソルダーレジストで被膜することが可
能になり、実装時のはんだ昇りやバイアホールの穴壁へ
のはんだ付着を防止できる効果が確認できた。As is clear from the above description, the present invention includes a step of applying photosensitive solder resist ink to both the front and back surfaces of the substrate and the wall surfaces of the via holes by spray coating, and bonding the first mask film to the substrate. By providing a step of exposing the solder resist ink on the wall surface of the via hole, and a step of bonding the second mask film to the substrate and exposing the solder resist ink on both the front and back surfaces, the inner wall surface of the via hole can be coated with the solder resist. We confirmed the effectiveness of preventing solder from rising during mounting and from adhering to the walls of via holes.
第１図（ａ）〜（ｄ）は本発明の第１の実施例を説明す
る工程順に示した断面図、第２図（ａ）〜（ｃ）は従来
のソルダレジストの形成方法を説明する工程順に示した
断面図である。
１・・・基板、２・・・回路パターン、３・・・バイア
ホール、４・・・ソルダーレジストインク、５・・・第
１のマスクフィルム、６・・・第２のマスクフィルム、
７・・ソルダレジスト、８・・・マスクフィルム。FIGS. 1(a) to (d) are cross-sectional views showing the steps of the first embodiment of the present invention, and FIGS. 2(a) to (c) are sectional views showing the conventional method of forming a solder resist. It is sectional drawing shown in order of a process. DESCRIPTION OF SYMBOLS 1... Board, 2... Circuit pattern, 3... Via hole, 4... Solder resist ink, 5... First mask film, 6... Second mask film,
7...Solder resist, 8...Mask film.
Claims (1)
ルが形成された基板にスプレー塗布により該基板の表裏
両面および前記バイアホール穴壁面に感光性のソルダレ
ジストインクを全面塗布する工程と、前記基板に第１の
マスクフィルムを接合し前記バイアホール穴壁面の前記
ソルダレジストインクを露光する工程と、前記基板に第
２のマスクフィルムを接合し表裏両面の前記ソルダレジ
ストインクを露光する工程と、前記露光したソルダレジ
ストインクを現像し硬化させる工程とを含むことを特徴
とするソルダレジストの形成方法。a step of applying a photosensitive solder resist ink over the entire surface of the board on which a circuit pattern, through holes for component mounting, and via holes are formed, by spray coating on both the front and back sides of the board and on the wall surface of the via hole; a step of bonding a second mask film to the substrate and exposing the solder resist ink on the wall surface of the via hole; a step of bonding a second mask film to the substrate and exposing the solder resist ink on both the front and back surfaces; A method for forming a solder resist, comprising the steps of developing and curing resist ink.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21557490A JP2844879B2 (en) | 1990-08-15 | 1990-08-15 | Method of forming solder resist |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21557490A JP2844879B2 (en) | 1990-08-15 | 1990-08-15 | Method of forming solder resist |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0497588A true JPH0497588A (en) | 1992-03-30 |
| JP2844879B2 JP2844879B2 (en) | 1999-01-13 |
Family
ID=16674691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21557490A Expired - Fee Related JP2844879B2 (en) | 1990-08-15 | 1990-08-15 | Method of forming solder resist |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2844879B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5462837A (en) * | 1993-09-03 | 1995-10-31 | Nec Corporation | Method of fabricating high density printed circuit board |
| US6174562B1 (en) * | 1996-07-09 | 2001-01-16 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and device on printed boards |
| JP2007335563A (en) * | 2006-06-14 | 2007-12-27 | Eastern Co Ltd | Dust-proof resin substrate, and its manufacturing method |
| WO2014119232A1 (en) * | 2013-01-30 | 2014-08-07 | 株式会社デンソー | Method for fabrication of multilayer substrate for bga-type component mounting |
| JP2015050310A (en) * | 2013-08-31 | 2015-03-16 | 京セラサーキットソリューションズ株式会社 | Method for manufacturing wiring board |
| CN107529281A (en) * | 2017-09-30 | 2017-12-29 | 生益电子股份有限公司 | A kind of PCB preparation method and PCB |
| CN111867271A (en) * | 2020-07-21 | 2020-10-30 | 大连崇达电路有限公司 | Method for manufacturing variegated ink solder mask of thick copper plate |
-
1990
- 1990-08-15 JP JP21557490A patent/JP2844879B2/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5462837A (en) * | 1993-09-03 | 1995-10-31 | Nec Corporation | Method of fabricating high density printed circuit board |
| US6174562B1 (en) * | 1996-07-09 | 2001-01-16 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and device on printed boards |
| JP2007335563A (en) * | 2006-06-14 | 2007-12-27 | Eastern Co Ltd | Dust-proof resin substrate, and its manufacturing method |
| KR101256099B1 (en) * | 2006-06-14 | 2013-04-23 | 가부시키가이샤 이스턴 | Method of producing dust-proof resin substrate |
| WO2014119232A1 (en) * | 2013-01-30 | 2014-08-07 | 株式会社デンソー | Method for fabrication of multilayer substrate for bga-type component mounting |
| JP2014168039A (en) * | 2013-01-30 | 2014-09-11 | Denso Corp | Process of manufacturing multilayer substrate for mounting bga components |
| US9930790B2 (en) | 2013-01-30 | 2018-03-27 | Denso Corporation | Method for manufacturing multilayer substrate for having BGA-type component thereon |
| JP2015050310A (en) * | 2013-08-31 | 2015-03-16 | 京セラサーキットソリューションズ株式会社 | Method for manufacturing wiring board |
| CN107529281A (en) * | 2017-09-30 | 2017-12-29 | 生益电子股份有限公司 | A kind of PCB preparation method and PCB |
| CN107529281B (en) * | 2017-09-30 | 2019-09-20 | 生益电子股份有限公司 | A kind of production method and PCB of PCB |
| CN111867271A (en) * | 2020-07-21 | 2020-10-30 | 大连崇达电路有限公司 | Method for manufacturing variegated ink solder mask of thick copper plate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2844879B2 (en) | 1999-01-13 |
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