JPH0497423A - Adder - Google Patents
AdderInfo
- Publication number
- JPH0497423A JPH0497423A JP21600490A JP21600490A JPH0497423A JP H0497423 A JPH0497423 A JP H0497423A JP 21600490 A JP21600490 A JP 21600490A JP 21600490 A JP21600490 A JP 21600490A JP H0497423 A JPH0497423 A JP H0497423A
- Authority
- JP
- Japan
- Prior art keywords
- carry
- circuit
- signal
- bit
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 241000030538 Thecla Species 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は加算器に係り、特に桁上げ先見回路（以下ＣＬ
Ａと略す）を用いた加算器に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an adder, and particularly to a carry look-ahead circuit (hereinafter referred to as CL).
This invention relates to an adder using an adder (abbreviated as A).
従来のＣＬＡを用いた加算器は、第２図に示すように、
各ビット加算ブロック１内のり・・ｌプルキャリー伝達
制御信号Ｐのｎビ・／ト分の論理積をとった信号で、最
下位ビット加算ブロックへ入力されるキャリーをｎビッ
ト分バイパスさせるための制御信号Ｂ′としている。こ
こで、各ビット加算ブロック１のリップルキャリー制御
信号Ｐは各ビット毎の２つの入力データの［Ｅｘｃ ｌ
ｕｓ １ｖｅ−ＯＲ〕をとったものである。The conventional adder using CLA is as shown in Fig. 2.
In each bit addition block 1, it is a signal obtained by ANDing n bits of pull carry transmission control signal P, and is a control for bypassing the carry input to the least significant bit addition block by n bits. The signal is designated as B'. Here, the ripple carry control signal P of each bit addition block 1 is [Exc l
us 1ve-OR].
第２図において、Ｅ−ＯＲゲートと電界効果トランジス
タとからなる１ビツト全加算ブロツク１が、多数配列さ
れ、加算器入力ｎビットデータＸ（ｎ）、Ｙ（ｎ）、加
算器入力キャリー信号Ｃｉ、が入力され、演算結果ｎビ
ットデータ５（ｎ）、加算器出力キャリー信号Ｃｃ＋
ｕ Ｌが出力される。加算プロ・ツク１がらの１ビツト
キヤリ一バイパス制御信号Ｂは、ｒ１人力ＡＮＤ回路に
入力され、ｎピッ１〜キヤリーバイパス制御信号Ｂ′を
出力し、さらに２人力ＡＮＤ回路４を介して、２人力Ｏ
Ｒ回路５を経て、出力キャリー信号Ｃ１ｅとして出力さ
れる。In FIG. 2, a large number of 1-bit full addition blocks 1 consisting of E-OR gates and field effect transistors are arranged, and adder input n-bit data X(n), Y(n), adder input carry signal Ci , is input, the operation result is n-bit data 5(n), and the adder output carry signal Cc+
uL is output. The 1-bit carry-bypass control signal B from the adder circuit 1 is input to the r1 manual AND circuit, which outputs the n-pi1 to carry-bypass control signal B', and further passes through the 2-man AND circuit 4 to the 2 Human power O
It passes through the R circuit 5 and is output as an output carry signal C1e.
従来の加算器は、各ビ・ント加算プロ・ツク１のキヤリ
−バイパス制御信号Ｂに、各ビット加算ブロックのデー
タ２人力の（ＥＯＲ）をとった信号、つまりリップルキ
ャリー伝達制御信号Ｐをそのまま流用していたため、キ
ャリーがｎビット分の加算ブロックをバイパスする条件
は限られていた。The conventional adder uses the carry-bypass control signal B of each bit addition block 1 as a signal obtained by taking the EOR of the data 2 of each bit addition block, that is, the ripple carry transmission control signal P. Because of the diversion, there were limited conditions for the carry to bypass the addition block for n bits.
よってｎビット加算ブロック内でキャリーが発生し、そ
のキャリーがｎビット加算ブロック外へ出て行く条件で
、最下位ビット加算ブロックへキャリーが入力される場
合に、ＣＬＡ回路が動作せず、リップルキャリーライン
のスピードが直接加算全体のスピードとなり、加算器の
高速化への妨げとなっていた。Therefore, if a carry occurs in the n-bit addition block and the carry is input to the least significant bit addition block under the condition that the carry goes out of the n-bit addition block, the CLA circuit will not operate and a ripple carry will occur. The speed of the line directly became the speed of the entire addition, which was an obstacle to increasing the speed of the adder.
本発明の目的は、前記問題点と解決し、高速で加算でき
るようにした加算器と提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an adder that can perform addition at high speed.
本発明の加算器の構成は、各ビット毎の入力データの論
理和をとる回路と、ｎビット分の論理和回路出力を受け
る論理積回路とを有するｎビア ｔ−キャリーバイパス
制御信号発生回路を備えでいることを特徴とする。The configuration of the adder of the present invention includes an n-via t-carry bypass control signal generation circuit having a circuit that takes the logical sum of input data for each bit, and an AND circuit that receives the output of the logical sum circuit for n bits. Characterized by being prepared.
〔実施例〕 次に図面を参照しながら本発明を説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の加算器を示すブロック図で
ある。第１図において、本実施例は、１ビツト加算ブロ
ツク１がＯＲ回路を含み、構成される。FIG. 1 is a block diagram showing an adder according to an embodiment of the present invention. In FIG. 1, in this embodiment, a 1-bit addition block 1 includes an OR circuit.
この１ビツト加算ブロツク１は、加算器入力Ｘ（ｉ）、
Ｙ（ｉ）＜ｉ＝０．１．−ｎ−１＞と下位ブロックが
らのキャリー信号ｃ１．を入力して、演算結果５（ｊ）
とキャリー信号Ｃａ ｕ Ｉを出力する１ビツトのりノ
ブルキャリー加算プロ・・ｌりである。This 1-bit addition block 1 has adder inputs X(i),
Y(i)<i=0.1. -n-1> and the carry signal c1. from the lower block. Input the calculation result 5(j)
This is a 1-bit node carry addition program which outputs a carry signal Ca u I and a carry signal Ca u I.
ＯＲ回路２は、Ｘ（ｉ）、’ｒ−（ｉ）（ｉ＝０゜１、
・・、ｎ−１）の２信号の論理和をとる回路ブロックで
あり、１ビツトキヤリ一バイパス制御信号を出力する。The OR circuit 2 has X(i), 'r-(i) (i=0°1,
..., n-1), and outputs a 1-bit carry-bypass control signal.
ｎ人カＡＮＤ回路３は、各ヒ・／トのキャリーバイパス
制御信号のＣＡＮＤ）をとり、「ｌビット分のキャリー
バイパスを制御する信号を出力する。２人カＡＮＤ回路
４は、ＡＮＤ回路３の出力が”ｌ”のときキャリー信号
ｃ１．．がらのキャリーを伝搬し、ＡＮＤ回路３の出力
が“０”のときは、キャリー信号Ｃ１゜がらのキャリー
をマスクする働きをする。２人力ＯＲ回路５は、リップ
ルキャリーラインから来るキャリーと、ＣＬＡき通って
来るキャリーのうち速い信号とが決まり次第、キャリー
信号Ｃ０Ｕ、を出力する回路である。この加算器入力Ｘ
（ｉ）、Ｙ（ｉ＞が、共に°゛０”でなければ、当ビッ
トのキャリーバイパス制御信号Ｂが”１”となり、キャ
リーのバイパスを許可する。The n-person AND circuit 4 takes the carry-bypass control signals of each person (CAND) and outputs a signal for controlling the carry-bypass for l bits. When the output of the AND circuit 3 is "L", the carry from the carry signal c1.. is propagated, and when the output of the AND circuit 3 is "0", it functions to mask the carry from the carry signal C1. Circuit 5 is a circuit that outputs a carry signal C0U as soon as the faster signal of the carry coming from the ripple carry line and the carry passing through CLA is determined.This adder input X
If both (i) and Y(i>) are not 0, the carry bypass control signal B of the relevant bit becomes 1, permitting carry bypass.
更にｎビット分即ちｎ本のキャリーバイパス制御信号Ｂ
が“１°゛になると、ｎ入力ＡＮＤ回路３の出力が“１
”となり、キャリー信号Ｃ０がらのキャリーをバイパス
させることができる。このとき、キャリー信号Ｃ１１ｌ
の入力が“○”即ちキャリーが入って来なければキャリ
ー信号Ｃ０，、ｔの出力はりップルキャリーラインから
来るキャリーが出力され、またキャリー信号Ｃ＋ｆｉの
入力が“１”つまりキャリーが入って来れば、キャリー
信号Ｃｏｕｔの出力はリップルキャリーラインから来る
キャリーと、ＣＬＡを通って来るキャリーの内速い方と
が決まり次第、キャリーが出方される。Furthermore, n bits, that is, n carry bypass control signals B
becomes “1°”, the output of the n-input AND circuit 3 becomes “1°”.
”, and the carry from the carry signal C0 can be bypassed. At this time, the carry signal C11l
If the input of is "○", that is, there is no carry coming in, the output of the carry signal C0,,t is the carry coming from the ripple carry line, and the input of the carry signal C+fi is "1", which means that the carry is not coming in. For example, the carry signal Cout is output as soon as the faster one of the carry coming from the ripple carry line and the carry coming through the CLA is determined.
以上説明したように、本発明は、各ビットキャリーバイ
パス制御信号を各ビット加算ブロックのデータ２人力の
論理和とし、キャリーがＣＬＡ回路を通ること、つまり
ｎヒフ８分バイパスする入力データの組み合わせ条件が
増えたことで、リップルキャリーのラインでのみキャリ
ーを伝達していた条件でもＣＬＡ回路を使うようになり
、ブタに依存する平均演算時間が短くなるという効果を
有する。As explained above, in the present invention, each bit carry bypass control signal is the logical sum of two data of each bit addition block, and the combination condition of the input data is such that the carry passes through the CLA circuit, that is, the input data is bypassed by n high 8 minutes. As a result of this increase, the CLA circuit is now used even under conditions where carry is transmitted only on the ripple carry line, which has the effect of shortening the average calculation time that depends on the pig.
第１図は本発明の一実施例の加算器のブロック図、第２
図は従来の加算器のブロック図である。
］・・・１ビット全加算ブロック、２・・・１ビ・ｌト
キャリーバイパス制御信号発生回路、３−・・ｎ大カＡ
ＮＤ＠Ｂ、４・−・２人カＡＮＤ回路、５・２人ヵＯＲ
回路、Ｘ （ｎ） 、 Ｙ （ｎ）−加算器入力ｎビッ
トデータ、Ｃ１゜・・・加算器入力キャリー信号、Ｃｏ
ｕｔ・・・加算器出力キャリー信号、５（ｎ）・・・演
算結果ｎビットデータ、Ｂ・・・１ビツトキヤリ一バイ
パス制御信号、Ｂ′・・・ｎビットキャリーバイパス制
御信号、Ｐ−・・リップルキャリー伝達制御信号。FIG. 1 is a block diagram of an adder according to an embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional adder. ]...1-bit full addition block, 2...1-bit carry bypass control signal generation circuit, 3-...n large power A
ND@B, 4--2 person AND circuit, 5-2 person OR
Circuit, X (n), Y (n) - Adder input n-bit data, C1゜... Adder input carry signal, Co
ut...Adder output carry signal, 5(n)...Arithmetic result n-bit data, B...1-bit carry-bypass control signal, B'...n-bit carry-bypass control signal, P-... Ripple carry transfer control signal.
Claims (1)
、前記ｎビット分の論理和回路の出力を入力とする論理
積回路とを有するｎビットキャリーバイパス制御信号発
生回路とを備えたことを特徴とする加算器。comprising an n-bit carry bypass control signal generation circuit having a circuit for calculating the logical sum of each bit of the input data of the adder, and an logical product circuit whose input is the output of the logical sum circuit for the n bits; An adder featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2216004A JP2552028B2 (en) | 1990-08-16 | 1990-08-16 | Adder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2216004A JP2552028B2 (en) | 1990-08-16 | 1990-08-16 | Adder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0497423A true JPH0497423A (en) | 1992-03-30 |
| JP2552028B2 JP2552028B2 (en) | 1996-11-06 |
Family
ID=16681802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2216004A Expired - Lifetime JP2552028B2 (en) | 1990-08-16 | 1990-08-16 | Adder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2552028B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9594317B2 (en) | 2014-01-09 | 2017-03-14 | Samsung Electronics Co., Ltd. | Organic photoreceptor, and electrophotographic cartridge and electrophotographic imaging apparatus including the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5930328A (en) * | 1982-08-14 | 1984-02-17 | Agency Of Ind Science & Technol | Unit cell for logical operation |
-
1990
- 1990-08-16 JP JP2216004A patent/JP2552028B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5930328A (en) * | 1982-08-14 | 1984-02-17 | Agency Of Ind Science & Technol | Unit cell for logical operation |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9594317B2 (en) | 2014-01-09 | 2017-03-14 | Samsung Electronics Co., Ltd. | Organic photoreceptor, and electrophotographic cartridge and electrophotographic imaging apparatus including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2552028B2 (en) | 1996-11-06 |
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