JPH0492469A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0492469A JPH0492469A JP2208965A JP20896590A JPH0492469A JP H0492469 A JPH0492469 A JP H0492469A JP 2208965 A JP2208965 A JP 2208965A JP 20896590 A JP20896590 A JP 20896590A JP H0492469 A JPH0492469 A JP H0492469A
- Authority
- JP
- Japan
- Prior art keywords
- sin
- insulating film
- capacitor
- ferroelectric
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 abstract description 8
- 238000000137 annealing Methods 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 239000002075 main ingredient Substances 0.000 abstract 2
- 230000015654 memory Effects 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910016006 MoSi Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 235000008708 Morus alba Nutrition 0.000 description 1
- 240000000249 Morus alba Species 0.000 description 1
- 229910003781 PbTiO3 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 102100030551 Protein MEMO1 Human genes 0.000 description 1
- 101710176845 Protein MEMO1 Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、強誘電体を用いた、メモ１ハその中でも特に
電気的に書き換え可能な不揮発性メモリの構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of an electrically rewritable non-volatile memory using a ferroelectric material, particularly a memo 1.
本発明は、強誘電体膜を用いた、キャパシタを半導体基
板上に集積したメモリの構造において、半導体基板上に
形成されたトランジスタなどの能動素子と、強誘電体か
らなるキャパシタとの間に主成分がＳｉｎからなる絶縁
膜を形成したことにより、トランジスタ特性に優れ、か
つ強誘電体キャパシタの比誘電率などの特性の優れたメ
モリを得るようにしたものである。The present invention provides a memory structure in which a capacitor is integrated on a semiconductor substrate using a ferroelectric film, in which a capacitor formed mainly between an active element such as a transistor formed on a semiconductor substrate and a capacitor made of a ferroelectric material is provided. By forming an insulating film composed of Sin, it is possible to obtain a memory having excellent transistor characteristics and excellent characteristics such as the dielectric constant of a ferroelectric capacitor.
従来の半導体不揮発性メモリとしては、絶縁ゲート中の
トラップまたは浮遊ゲートにシリコン基板からの電荷を
注入することによりシリコン基板の表面ポデンシャルが
変調される現象を用いた、ＭＩＳ型トランジスタが一般
に使用されており、ＥｐＲｏＭ（紫外線消去型不揮発性
メモリ）やＥＥＦＲＯＭ（電気的書き換え可能型不揮発
性メモリ）などとして実用化されている。Conventional semiconductor non-volatile memories generally use MIS transistors, which utilize a phenomenon in which the surface potential of the silicon substrate is modulated by injecting charge from the silicon substrate into a trap or floating gate in an insulated gate. It has been put into practical use as EpRoM (ultraviolet erasable nonvolatile memory) and EEFROM (electrically rewritable nonvolatile memory).
しかしこれらの不揮発性メモリは、情報の書き換え電圧
が、通常約２０Ｖ前後と高いことや、書き換え時間が非
常に長い（例えばＥＥＰＲＯＭの場合数十ｍ ｓｅｃ
）などの欠点を有す。また、情報の書き換え回数が、約
１０５回程度であり、非常に少なく、繰り返し使用する
場合には問題が多い。However, in these nonvolatile memories, the voltage for rewriting information is usually high, around 20 V, and the rewriting time is extremely long (for example, in the case of EEPROM, it is several tens of milliseconds).
) and other disadvantages. Further, the number of times information is rewritten is about 105 times, which is very small, and there are many problems when using it repeatedly.
電気的に分極が反転可能である強誘電体を用いた、不揮
発性メモリについては、書き込み時間と読み出し時間が
原理的にほぼ同じであり、また電源を切っても分極は保
持されるため、理想的な不揮発性メモリとなる可能性を
有す桑。このよった強誘電体を用いた不揮発性メモリに
ついては、例えば米国特許４１４９３０２の様に、シリ
コン基板上に強誘電体からなるキャパシタを集積した構
造や、米国特許３８５２７００のようにＭ 工Ｓ型トラ
ンジスタのゲート部分に強誘電体膜を配置した不揮発性
メモリなどの提案がなされている。また、最近では、第
５図のようなＭＯＳ型半導体装置に積層した構造の不揮
発性メモリが工ＥＤＭ’８７ｐｐ、８５０−８５１に提
案されている。第６図において、５０１はＰ型Ｓｉ基板
であり、６０２は素子分離用のＬＯＯＯ３酸化膜、５０
５はソースとなるＮ型拡散層であり、５０４はドレイン
となるＮ型拡散層であゑ。３０５はゲート電極であり、
５０６は層間絶縁膜である。３０８はゲート絶縁膜であ
る。３０９が強誘電体膜であり、電極６１０と３１１に
より挾まれ、キャパシタを構成している。６０７は第２
層間絶縁膜であり、５１２が配線電極となるＡ１である
。さてこのような構造の強誘電体メモリにおいては、強
誘電体の特性を向上させるため、酸素を含む雰囲気中で
アニールする必要がある。このような酸素アニールを行
なうと、トランジスタのしきい値電圧などの特性の変動
が起きる。そこで本発明はこのような課題を解決するも
ので、その目的とする所は、強誘電体の特性の向上のた
めに酸素アニールをしてもトランジスタなどの特性の変
動のない強誘電体メモリ、特に不揮発性メモリを提供す
るところにある。Non-volatile memory, which uses ferroelectric materials whose polarization can be electrically reversed, is ideal because the write time and read time are basically the same, and the polarization is maintained even when the power is turned off. Mulberry has the potential to become a non-volatile memory. Regarding non-volatile memories using such ferroelectric materials, for example, there are structures in which ferroelectric capacitors are integrated on a silicon substrate as in U.S. Pat. No. 4,149,302, and M-type S-type transistors as in U.S. Pat. Proposals have been made for nonvolatile memories in which a ferroelectric film is placed in the gate portion of the device. Recently, a nonvolatile memory having a structure stacked on a MOS type semiconductor device as shown in FIG. 5 has been proposed in Engineering EDM'87pp, 850-851. In FIG. 6, 501 is a P-type Si substrate, 602 is a LOOO3 oxide film for element isolation, and 50
5 is an N-type diffusion layer that becomes a source, and 504 is an N-type diffusion layer that becomes a drain. 305 is a gate electrode;
506 is an interlayer insulating film. 308 is a gate insulating film. A ferroelectric film 309 is sandwiched between electrodes 610 and 311 to form a capacitor. 607 is the second
This is an interlayer insulating film, and 512 is A1 which becomes a wiring electrode. Now, in a ferroelectric memory having such a structure, in order to improve the characteristics of the ferroelectric material, it is necessary to perform annealing in an atmosphere containing oxygen. When such oxygen annealing is performed, characteristics such as the threshold voltage of the transistor change. The present invention is intended to solve these problems, and its purpose is to provide a ferroelectric memory in which the characteristics of transistors, etc. do not change even when oxygen annealing is performed to improve the characteristics of the ferroelectric. In particular, it provides non-volatile memory.
本発明は、強誘電体膜を用いた、キャパシタを半導体基
板上に集積したメモリの構造において、半導体基板上に
形成されたトランジスタなどの能動素子と、強誘電体か
らなるキャパシタとの間に主成分がＳｉｎからなる絶縁
膜を形成したことを特徴とする。The present invention provides a memory structure in which a capacitor is integrated on a semiconductor substrate using a ferroelectric film, in which a capacitor formed mainly between an active element such as a transistor formed on a semiconductor substrate and a capacitor made of a ferroelectric material is provided. The present invention is characterized in that an insulating film containing a component of Sin is formed.
第１図は１本発明の半導体装置の一実施例に於ける主要
断面図である。以下、第１図に従い、本発明の半導体装
置を説明する。ここでは説明の都合上８１基析を用い、
Ｎチャンネルトランジスタを用いた例につき説明する。FIG. 1 is a main sectional view of an embodiment of a semiconductor device according to the present invention. The semiconductor device of the present invention will be described below with reference to FIG. For convenience of explanation, 81 bases are used here.
An example using an N-channel transistor will be explained.
１０１はＰ型Ｓ１基板であり、例えば２００ｈｍ、αの
比抵抗のウェハを用いる。１０２は素子分離用の絶縁膜
であり、例えば、従来技術であるＬＯＣＯ３法により酸
化膜を６００ＯＡ形成する１０３はソースとなるＮ型拡
散層であり、例えばリンを８０ＫｅＶ５Ｅ１５ｃｒｎ−
２イオン注入することにより形成する。１０４はドレイ
ンとなるＮ型拡散層であり、１０６と同時にイオン注入
により形成する。１０５はゲート電極であり、例えばリ
ンでドープされたボ’ＪＳｉを用いる。１０８はゲート
電極であり、例えば熱酸化法により、５ｉ０２膜を２５
ＯＡ形成する。１０９が強誘電体膜であるＰｂＴｉ０．
、ＰＺＴ（ＰｂＺｒＯ８、ＰｂＴｉ０．、ＰＬＺＴ（Ｌ
ａ、ＰｂＺｒ０゜、ＰｂＴｉＯ３）であり、例えばスパ
ッタ法などにより形成する。１１１は強誘電体膜の電極
のうちの一方の電極（以下、下部電極とよぶ）で有り、
例えば、Ｐｔ、Ａｌ、ＭｏＳｉ、ＷＳｉなどであり、例
えばスパッタ法で形成する。ｉｉｏは強誘電体膜の電極
のうちのもう一方の電極（以下、上部電極という）で有
り、例えば、Ｐｔ、ＡＩ。101 is a P-type S1 substrate, for example, a wafer of 200 hm and a specific resistance of α is used. 102 is an insulating film for element isolation; for example, an oxide film of 600 OA is formed using the conventional LOCO3 method; 103 is an N-type diffusion layer that becomes a source;
It is formed by implanting two ions. Reference numeral 104 denotes an N-type diffusion layer which becomes a drain, and is formed simultaneously with 106 by ion implantation. A gate electrode 105 is made of, for example, Bo'JSi doped with phosphorus. 108 is a gate electrode, for example, a 5i02 film is formed at 25 by thermal oxidation method.
Forms OA. PbTi0.109 is a ferroelectric film.
, PZT(PbZrO8, PbTi0., PLZT(L
a, PbZr0°, PbTiO3), and is formed by, for example, a sputtering method. 111 is one of the electrodes of the ferroelectric film (hereinafter referred to as the lower electrode);
For example, it is made of Pt, Al, MoSi, WSi, etc., and is formed by, for example, a sputtering method. Iio is the other electrode (hereinafter referred to as the upper electrode) of the electrodes of the ferroelectric film, and is made of, for example, Pt or AI.
ＭｏＳｉ、ＷＳｉなどであり、例えばスパッタ法で形成
する。１０６と１０７は層間絶縁膜であり、例えば気相
成長法によりＳ ｉ Ｏ，膜をそれぞれ５０００Ａ形成
する。１１５が本発明の趣旨によるＳｉｎを主成分とす
る絶縁膜であり、第１図の場合には、１１１の下部電極
と１０６の眉間絶縁膜の間に、気相成長法により形成す
る。１１２は１０３のソース拡散層と１１０の上部電極
を接続する配線電極であり、例えばＡ１で形成する。な
お、この１１２の配線電極はその他の配線、例えばＭＯ
Ｓ ）ランジスタ間の接続に使っても良い。It is made of MoSi, WSi, etc., and is formed by, for example, a sputtering method. Reference numerals 106 and 107 are interlayer insulating films, each of which is made of SiO and has a thickness of 5000 Å, for example, formed by vapor phase growth. 115 is an insulating film mainly composed of Sin according to the spirit of the present invention, and in the case of FIG. 1, it is formed between the lower electrode 111 and the glabellar insulating film 106 by a vapor growth method. A wiring electrode 112 connects the source diffusion layer 103 and the upper electrode 110, and is made of A1, for example. Note that these 112 wiring electrodes are connected to other wirings, such as MO
S) May be used to connect between transistors.
さて本発明の作用であるが、第１図のような構造にする
ことにより、強誘電体のキャパシタ、を形成後、酸素を
含む雰囲気中でアニールした場合でも、酸素は１１６の
Ｓｉｎで阻止され、Ｓｉｎの下のＭＯＳ）ランシスタに
は影響がでな（なり、例えばＭＯＳ）ランシスタのしき
い値電圧もアニール前と変化がない値が得られた。Now, as for the effect of the present invention, by creating a structure as shown in Fig. 1, even when a ferroelectric capacitor is formed and then annealed in an atmosphere containing oxygen, oxygen is blocked by 116 Sin. , MOS under Sin) was not affected (for example, MOS), and the threshold voltage of the transistor was also unchanged from before annealing.
第２図は、本発明の半導体装置の他の実施例に於ける主
要断面図である。FIG. 2 is a main cross-sectional view of another embodiment of the semiconductor device of the present invention.
第２図の実施例を、第１図の実施例と比較した場合の特
徴は、１０７の層間絶縁膜と、１１３のＳｉｎ膜との間
に、さらに２０１のＳ ｉ Ｏ２を主成分とする絶縁膜
を形成した点にある。The feature when comparing the embodiment shown in FIG. 2 with the embodiment shown in FIG. The point lies in the formation of a film.
第１図においては、１１１の下部電極は１１５のＳｉｎ
と直接接していたため、アニール条件によっては、Ｓｉ
ｎのストレスにより剥がれなどの問題が発生した。第２
図のように下部電極とＳｉｎの間にＳ ｉ Ｏ２を挾む
ことにより、本発明の効果、即ち、酸素を含む雰囲気中
でアニールしてもＭＯＳ）ランシスタの特性がかわらず
、かつ、剥がれなどの問題は解決された。In FIG. 1, the lower electrode 111 is the sinusoid of 115.
Depending on the annealing conditions, the Si
Problems such as peeling occurred due to the stress of n. Second
By sandwiching SiO2 between the lower electrode and the Sin as shown in the figure, the effects of the present invention can be achieved, that is, the characteristics of the MOS (MOS) transistor do not change even when annealed in an oxygen-containing atmosphere, and peeling etc. issue has been resolved.
本発明のように、強誘電体膜からなるキャパ７りが、集
積された半導体装置において、トランジスタなどの能動
素子と、強誘電体からなるキャパシタとの間に、主成分
がＳｉｎからなる絶縁膜を形成することにより、強誘電
体膜の特性の向上のために酸素アニールを行なってもト
ランジスタなどの特性の変動のない半導体装置が得られ
るという効果を有する。As in the present invention, in a semiconductor device in which a capacitor 7 made of a ferroelectric film is integrated, an insulating film mainly composed of Sin is provided between an active element such as a transistor and a capacitor made of a ferroelectric material. By forming this, it is possible to obtain a semiconductor device such as a transistor whose characteristics do not change even if oxygen annealing is performed to improve the characteristics of the ferroelectric film.
第１図は、本発明の半導体装置の一実施例に於ける・主
要断面図であり、第２図は、本発明の半導体装置のたの
実施例に於ける主要断面図である。
第５図は、従来の半導体装置に於ける主要断面図である
。
１０１．５０１・・・・・・８１基板
１０２．５０２・・・・・・素子分離絶縁膜ｉｏｎ、５
０５・・・・・・ソース拡散層１０４．５０４・・・・
・・ドレイン拡散層１０５．５０５・・・・・・ゲート
電極１０６．１０７，３０６，５０７・・・・・・層間
絶縁膜
１０８．３０８・・・・・・ゲート電極１０９．５０９
・・・・・・強誘電体膜０．３１０・・・・・・上部電
極
１．５１１・・・・・・下部電極
２．３１２・・・・・・配線電極
３・・・・・・・・・・・・・・・・・・ｓｉＮ膜１・
・・・・・・・・・・・・・・・・・Ｓ ｉ Ｏ２膜以
上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴木喜三部（他１名）第
Ａ
冒
筆FIG. 1 is a main cross-sectional view of one embodiment of the semiconductor device of the present invention, and FIG. 2 is a main cross-sectional view of another embodiment of the semiconductor device of the present invention. FIG. 5 is a main cross-sectional view of a conventional semiconductor device. 101.501...81 Substrate 102.502...Element isolation insulating film ion, 5
05... Source diffusion layer 104.504...
...Drain diffusion layer 105.505...Gate electrode 106.107, 306, 507...Interlayer insulating film 108.308...Gate electrode 109.509
...Ferroelectric film 0.310 ... Upper electrode 1.511 ... Lower electrode 2.312 ... Wiring electrode 3 ... ......SiN film 1.
・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・
Claims (3)
成された同一半導体基板上に集積された半導体装置にお
いて、前記半導体基板上に形成されたトランジスタなど
の能動素子と、前記強誘電体からなるキャパシタとの間
に、主成分がＳｉｎからなる絶縁膜がすくなくとも形成
されていることを特徴とする半導体装置。(1) In a semiconductor device in which a capacitor made of a ferroelectric film is integrated on the same semiconductor substrate on which an active element is formed, an active element such as a transistor formed on the semiconductor substrate and the ferroelectric film are integrated. 1. A semiconductor device characterized in that at least an insulating film mainly composed of Sin is formed between the capacitor and the capacitor.
分がＳｉｎからなる絶縁膜との間に、ＳｉＯ＿２を主成
分とする絶縁膜が形成されていることを特徴とする請求
項１記載の半導体装置。(2) An insulating film mainly composed of SiO_2 is formed between the capacitor made of the ferroelectric material and the insulating film mainly composed of Sin. Semiconductor equipment.
１及び２記載の半導体装置。(3) The semiconductor device according to claim 1 or 2, wherein the Sin contains oxygen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02208965A JP3111416B2 (en) | 1990-08-07 | 1990-08-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02208965A JP3111416B2 (en) | 1990-08-07 | 1990-08-07 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11147799A Division JP3270020B2 (en) | 1999-04-19 | 1999-04-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0492469A true JPH0492469A (en) | 1992-03-25 |
| JP3111416B2 JP3111416B2 (en) | 2000-11-20 |
Family
ID=16565092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02208965A Expired - Lifetime JP3111416B2 (en) | 1990-08-07 | 1990-08-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3111416B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6984861B2 (en) * | 2003-07-28 | 2006-01-10 | Kabushiki Kaisha Toshiba | Semiconductor memory device having a ferroelectric capacitor |
| US7023036B2 (en) | 2001-10-02 | 2006-04-04 | Matsushita Electric Industrial Co., Ltd. | Ferroelectric element and actuator using the same, and ink jet head and ink jet recording device |
-
1990
- 1990-08-07 JP JP02208965A patent/JP3111416B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7023036B2 (en) | 2001-10-02 | 2006-04-04 | Matsushita Electric Industrial Co., Ltd. | Ferroelectric element and actuator using the same, and ink jet head and ink jet recording device |
| US6984861B2 (en) * | 2003-07-28 | 2006-01-10 | Kabushiki Kaisha Toshiba | Semiconductor memory device having a ferroelectric capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3111416B2 (en) | 2000-11-20 |
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