JPH0487356A - Production of hybrid integrated circuit - Google Patents
Production of hybrid integrated circuitInfo
- Publication number
- JPH0487356A JPH0487356A JP2201223A JP20122390A JPH0487356A JP H0487356 A JPH0487356 A JP H0487356A JP 2201223 A JP2201223 A JP 2201223A JP 20122390 A JP20122390 A JP 20122390A JP H0487356 A JPH0487356 A JP H0487356A
- Authority
- JP
- Japan
- Prior art keywords
- sub
- integrated circuit
- board
- hard substrate
- adhesive resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 28
- 230000015654 memory Effects 0.000 claims abstract description 11
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 239000011347 resin Substances 0.000 claims abstract description 9
- 239000004840 adhesive resin Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 230000001070 adhesive effect Effects 0.000 claims description 22
- 239000000853 adhesive Substances 0.000 claims description 21
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 claims description 2
- 239000004642 Polyimide Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 229920006332 epoxy adhesive Polymers 0.000 claims 1
- 229920006223 adhesive resin Polymers 0.000 abstract description 7
- 238000003491 array Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 description 9
- 239000010410 layer Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 230000009191 jumping Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 etc. Substances 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000010019 resist printing Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は大容量のバス構造を備える混成集積回路の製造
方法に関し、特にそのバス相互およびバスと搭載素子と
の配線接続構造を改善した混成集積回路の製造方法に関
する。[Detailed Description of the Invention] (A) Industrial Application Field The present invention relates to a method for manufacturing a hybrid integrated circuit having a large-capacity bus structure, and in particular improves the wiring connection structure between the buses and between the bus and mounted elements. The present invention relates to a method for manufacturing a hybrid integrated circuit.
（ロ）従来の技術
第４図を参照して従来の混成集積回路およびその製造方
法を説明する。(b) Prior Art A conventional hybrid integrated circuit and its manufacturing method will be explained with reference to FIG.
第４図は混成集積回路の平面図であって、混成集積回路
は絶縁金属基板（７０）と、導電路（７２）と、中継バ
ンド（７４）と、外部リード用パッド（７６）と、ボン
ディングワイア（７８）と、第１のゲートアレイ（８０
）、マイクロコンピュータ（８２）、メモリ（８４）、
第２のゲートアレイ（８６）、その他の周辺集積回路（
８８）等の複数の集積回路素子と、チップ抵抗（９０）
等で示されている。FIG. 4 is a plan view of the hybrid integrated circuit, which includes an insulated metal substrate (70), a conductive path (72), a relay band (74), an external lead pad (76), and a bonding circuit. wire (78) and the first gate array (80).
), microcomputer (82), memory (84),
Second gate array (86), other peripheral integrated circuits (
A plurality of integrated circuit elements such as 88) and a chip resistor (90)
etc.
絶縁金属基板（７０）には絶縁処理されたアルミニウム
基板が主として用いられ、この絶縁金属基板（７０）に
貼着した銅箔をホトエツチングする等して所定形状に配
線パターンが形成され、後述する集積回路素子を固着す
るためのパッド、その電極を接続するためのパッド、中
継パッド（７４）等の導電路（７２）および外部リード
用パッド（７６）等が形成される。The insulated metal substrate (70) is mainly an insulated aluminum substrate, and a wiring pattern is formed in a predetermined shape by photo-etching the copper foil attached to the insulated metal substrate (70). Pads for fixing circuit elements, pads for connecting their electrodes, conductive paths (72) such as relay pads (74), pads for external leads (76), and the like are formed.
上記した導電路（７２）の所定位置には、第１および第
２のゲートアレイ（８０）（８６）、マイクロコンピュ
ータ（８２）、メモリ（８４）および周辺集積回路（８
８）を形成するチップ状の素子がＡｇペーストにより固
着され、チンプ゛コンデンサ、チップ抵抗素子等の電子
部品が接続強度、コンタクト抵抗を考慮して半田固着さ
れる。At predetermined positions of the conductive path (72), there are first and second gate arrays (80) (86), a microcomputer (82), a memory (84), and a peripheral integrated circuit (86).
The chip-shaped elements forming 8) are fixed with Ag paste, and electronic components such as chip capacitors and chip resistance elements are fixed with solder taking connection strength and contact resistance into consideration.
斯る大規模な混成集積回路は多種の電気機器に使用され
、近年ではプリンタコントローラとしても使用される。Such large-scale hybrid integrated circuits are used in a wide variety of electrical equipment, and in recent years have also been used as printer controllers.
一般的なプリンタコントローラを混成集積回路として実
現する場合につき簡単に説明すると、例えば第１のゲー
トアレイ（８０）はセントロニクス仕様のパラレル・デ
ータ、センサ人力およびプリンタのフロントパネル・ス
イッチ信号等を人力してマイクロコンピュータ（８２）
に人力する人力インターフェースとして機能し、第２の
ゲートアレイ（８６）はマイクロコンピュータ（８２）
の命令に基づいて文字フォントを印字ヘッドに出力し、
また牛ヤリッジリターンあるいはフィードフォワード信
号等の制御信号等を出力する出力インターフェースとし
て機能する。また、マイクロコンピュータ（８２）には
例えば１６ビツトの入出力ボートと２０ビツトのアドレ
ス空間を有する８０ピンのマイクロコンピュータが使用
され、メモリ（８４）には例えば２５６にビット、２８
ピンのメモリが使用される。To briefly explain the case where a general printer controller is realized as a hybrid integrated circuit, for example, the first gate array (80) uses manual input such as Centronics specification parallel data, sensor input, printer front panel switch signals, etc. Microcomputer (82)
The second gate array (86) functions as a human power interface for the microcomputer (82).
Outputs the character font to the print head based on the instructions of
It also functions as an output interface for outputting control signals such as cow-yarrow return or feed-forward signals. Further, the microcomputer (82) is, for example, an 80-pin microcomputer having a 16-bit input/output port and a 20-bit address space, and the memory (84) is, for example, 256 bits and 28 bits.
Pin memory is used.
上記構造の混成集積回路はプリンタコントロラに要求さ
れる小型化の要求に一応、応えることができ、また絶縁
金属基板を使用するため機器の放熱の問題も解決されて
いる。The hybrid integrated circuit having the above structure can meet the demand for miniaturization required for printer controllers, and also solves the problem of heat dissipation of the device because an insulated metal substrate is used.
（ハ）発明が解決しようとする課題
しかしながら、１６ビツトのデータバスと２０ビツトも
のアドレス空間を有し、しかも大規模構成されるディジ
タル回路の配線パターンは極めて複雑であり、従来の製
造方法によれば、第４図に示されるように、データバス
、アドレスバス等の導電路を基板上の処断で、ジャンピ
ングワイア接続と称される技術を用いて相互に接続しな
ければならなかった。その結果、ジャンピングワイアを
固着するためのノ＜ラド数の増加による基板有効実装面
積の低下および装置の小型化の点で限界があり、大容量
かつ超小型の混成集積回路の実現が困難であった。(c) Problems to be Solved by the Invention However, the wiring pattern of a large-scale digital circuit having a 16-bit data bus and a 20-bit address space is extremely complex, and conventional manufacturing methods cannot be used. For example, as shown in FIG. 4, conductive paths such as data buses and address buses had to be interconnected by cutting on the substrate using a technique called jumping wire connection. As a result, the effective mounting area of the board decreases due to the increase in the number of rads required to secure the jumping wires, and there are limits to miniaturization of the device, making it difficult to realize large-capacity and ultra-small hybrid integrated circuits. Ta.
また、多層配線技術により上記の問題を解決する方法が
いくつか提案されているが、予め多層構造とされた配線
基板に素子を固着、搭載し混成集積回路を完成する方法
によれば、半田固着等の基板の高温処理によって配線基
板間の絶縁性能並びに接続の信頼性が低下する問題を有
している。これに対して、製造工程の途中で主基板とサ
ブ基板を固着し多層基板構造とすれば上記した問題は解
消できる。しかし、製造工程中において主基板とサブ基
板を接着する接着剤の選択によっては問題が発生する１
例えば、接着性樹脂含浸シート等の熱硬化タイプの接着
剤を使用する場合には、熱処理中に加圧する必要がある
ため、サブ基板の固着時にチップ状の集積回路素子の表
面を損傷するおそれがある。In addition, several methods have been proposed to solve the above problems using multilayer wiring technology. There is a problem in that insulation performance and connection reliability between wiring boards deteriorate due to high-temperature processing of such boards. On the other hand, the above-mentioned problem can be solved by fixing the main board and the sub-board during the manufacturing process to form a multilayer board structure. However, problems may occur depending on the adhesive selected to bond the main board and sub-board during the manufacturing process.
For example, when using a thermosetting adhesive such as an adhesive resin-impregnated sheet, it is necessary to apply pressure during heat treatment, so there is a risk of damaging the surface of the chip-shaped integrated circuit element when the sub-board is fixed. be.
さらには、主基板の特に集積回路素子周辺は微細パター
ンに形成されるため、パッド等のパターンを覆うことが
ないように接着層を精度良（形成することは困難であっ
た。Furthermore, since a fine pattern is formed on the main substrate, especially around the integrated circuit element, it has been difficult to form an adhesive layer with high precision so as not to cover patterns such as pads.
以上の理由のため、基板の単一面に搭載素子とサブ基板
を備える多層配線構造を達成することは一般的に困難で
あった。For the above reasons, it has generally been difficult to achieve a multilayer wiring structure that includes mounting elements and sub-boards on a single surface of the board.
（ニ）課題を解決するための手段
本発明は上記課題に鑑みてなされたものであって、所定
形状に配線パターンを形成したサブ基板の一生面にこの
サブ基板と実質的に同一形状を有した接着性樹脂含浸シ
ートを仮接着することによりサブ基板の接着の煩雑を解
消し、このサブ基板を、半田工程等の絶縁硬質基板が比
較的高温に晒される工程の終了後であって、集積回路素
子の固着前に絶縁硬質基板上の所定の領域に接着するこ
とによって、従来の製造方法が有する基板有効実装面積
の低下の問題、配線基板間の絶縁性能並びに接続の信頼
性の低下の問題、さらには集積回路素子の損傷の問題を
解決するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and has a sub-board on which a wiring pattern is formed in a predetermined shape, the whole surface of which has substantially the same shape as the sub-board. By temporarily bonding the adhesive resin-impregnated sheet, the complexity of adhering the sub-boards can be eliminated, and the sub-boards can be integrated after the soldering process or other process in which the insulating hard substrate is exposed to relatively high temperatures. By adhering circuit elements to a predetermined area on an insulating hard substrate before fixing them, problems associated with conventional manufacturing methods include a reduction in the effective mounting area of the board, as well as a reduction in insulation performance and connection reliability between wiring boards. , and further solves the problem of damage to integrated circuit elements.
（ホ）作用
サブ基板に形成された導電路を介してアドレスバス、デ
ータバス等の接続が行われるため長スパンの接続が可能
になり、マイクロコンピュータとその周辺回路素子間の
接続、並びにマイクロコンピュータおよびその周辺回路
素子と所定の導電路との接続において、従来の如きジャ
ンピングワイア接続を不要とすることができる。(e) Since the address bus, data bus, etc. are connected via the conductive paths formed on the working sub-board, long span connections are possible, and connections between the microcomputer and its peripheral circuit elements, as well as the microcomputer Further, in connection between peripheral circuit elements and a predetermined conductive path, conventional jumping wire connections can be made unnecessary.
また、サブ基板の一生面に接着性樹脂含浸シートが仮接
着されているためサブ基板の位置精度に留意するのみで
接着樹脂含浸シートを高精度に位置決めすることができ
、位置ずれによる含浸樹脂のパターン汚染の問題および
工程の煩雑さの問題が解消される。In addition, since the adhesive resin-impregnated sheet is temporarily bonded to the entire surface of the sub-board, the adhesive resin-impregnated sheet can be positioned with high precision just by paying attention to the positional accuracy of the sub-board. The problem of pattern contamination and the problem of process complexity are solved.
さらに、半田工程等の終了後にサブ基板が固着されるた
め半田印刷、ソルダーレジスト印刷等の殆どの印刷工程
がサブ基板に阻害されることなく行えると共に半田工程
等の高温によりサブ基板およびその接着剤が絶縁破壊す
ることがない。Furthermore, since the sub-board is fixed after the soldering process, etc., most printing processes such as solder printing and solder resist printing can be performed without being obstructed by the sub-board, and the high temperature of the soldering process can cause the sub-board and its adhesive to will not cause dielectric breakdown.
さらにまた、集積回路素子の固着工程の前にサブ基板が
固着されるため、その固着工程においてチップ状の集積
回路素子を損傷するおそれがない、しかも、集積回路素
子を固着するＡｇペースト層はスタンプ法により形成さ
れるためサブ基板の存在はＡｇペースト層形成の障害と
ならない。Furthermore, since the sub-substrate is fixed before the process of fixing the integrated circuit elements, there is no risk of damaging the chip-shaped integrated circuit elements during the fixing process. Since it is formed by the method, the existence of the sub-substrate does not hinder the formation of the Ag paste layer.
（へ）実施例
本発明に特徴的なそれぞれの工程における混成集積回路
を断面図で示す第１図（Ａ）乃至（Ｄ）を参照して本発
明の一実施例を説明する。(F) Embodiment An embodiment of the present invention will be described with reference to FIGS. 1A to 1D, which show cross-sectional views of a hybrid integrated circuit in each process characteristic of the present invention.
第１図（Ａ）を参照すると、絶縁硬質基板（１０）はセ
ラミックス、耐熱樹脂あるいは金属等の任意の硬質基板
が使用される。放熱特性に優れるアルミニウムが使用さ
れる場合には、陽極酸化によりその表面がアルマイト処
理され、その−主面にエボ牛シ樹脂あるいはポリイミド
樹脂等による接着性を有する絶縁樹脂層（１２）と銅箔
のクラッドが貼着される０図示する導電路（１４）、外
部リード用パッド（１８）はその銅箔をホトエツチング
して形成されたものであり、第２図の平面図に示される
ように、絶縁硬質基板（１０）上に所要のパターンに形
成され、一部バス構造を形成する。なお、導電路（１４
）は後述するザブ基板（４０）の下部にも形成されてい
る。Referring to FIG. 1(A), the insulating hard substrate (10) may be any hard substrate such as ceramics, heat-resistant resin, or metal. When aluminum, which has excellent heat dissipation properties, is used, its surface is alumite-treated by anodizing, and its main surface is coated with an insulating resin layer (12) with adhesive properties made of ebo-silk resin or polyimide resin, etc., and copper foil. The illustrated conductive path (14) and external lead pad (18) to which the cladding is attached are formed by photo-etching the copper foil, and as shown in the plan view of FIG. It is formed into a desired pattern on an insulating hard substrate (10), forming a part of the bus structure. In addition, the conductive path (14
) is also formed at the bottom of the sub-board (40), which will be described later.
次に第１図（Ｂ）を参照すると、絶縁硬質基板（１０）
の所定の導電路（１４）上に半田が印刷され、その個所
にチップ抵抗、あるいはチップコンデンサ等のチップ素
子（３４）が載置される。そして、絶縁硬質基板（１０
）が加熱されて、半田の溶融によりそれらチップ素子（
３４）が導電路（１４）に固着される。Next, referring to FIG. 1(B), an insulating rigid substrate (10)
Solder is printed on a predetermined conductive path (14), and a chip element (34) such as a chip resistor or a chip capacitor is placed at that location. Then, an insulating hard substrate (10
) are heated and the solder melts, causing those chip elements (
34) is fixed to the conductive path (14).
第２図の平面図に示されるように、チップ抵抗、あるい
はチップコンデンサ等のチップ素子（３４）はサブ基板
（４０）に離間配置される。このため、第２図の１−１
線断面図である第１図（Ｂ）にはそれらチップ素子（３
４）は側面図で示されている。As shown in the plan view of FIG. 2, chip elements (34) such as chip resistors or chip capacitors are spaced apart from each other on the sub-substrate (40). For this reason, 1-1 in Figure 2
FIG. 1(B), which is a line cross-sectional view, shows these chip elements (3
4) is shown in side view.
第１図（Ｃ）を参照すると、次に絶縁硬質基板（１０）
上に形成したガイドボスト（図示しない）に係合させる
等してサブ基板（４ｏ）と接着樹脂含浸シー） （６０
）の積層体が絶縁硬質基板（１ｏ）上の所定の領域（第
２図参照）に載置される。同図には先のチップ素子（３
４）が省略されている。Referring to FIG. 1(C), next is the insulating rigid substrate (10).
The sub-board (4o) and the adhesive resin-impregnated sheet (60
) is placed on a predetermined area (see FIG. 2) on an insulating hard substrate (1o). The same figure shows the previous chip element (3
4) has been omitted.
接着樹脂含浸シー） （６０）は厚さ０．５ｍｍ程度の
和紙に接着性を有する例えばエポキシ系の樹脂を含浸さ
せたものであり、所定のパターンに導電路（４４）等を
形成したサブ基板（４０）に積層し、例えば９０°Ｃ１
３０分の熱処理によりサブ基板（４０）に仮接着された
ものである。この接着樹脂含浸シト（６０）は押圧下で
、所定の温度条件で絶縁硬質基板（］Ｉ０を加熱するこ
とにより、その含浸樹脂が再度溶融し、熱硬化して絶縁
硬質基板（］Ｉ０とサブ基板（４０）を強固に接着する
。Adhesive resin-impregnated sheet (60) is Japanese paper about 0.5 mm thick impregnated with an adhesive, such as an epoxy resin, and is a sub-board on which conductive paths (44) etc. are formed in a predetermined pattern. (40), e.g. 90°C1
It was temporarily bonded to the sub-substrate (40) by heat treatment for 30 minutes. This adhesive resin-impregnated sheet (60) is heated under pressure to the insulating rigid substrate (]I0 under predetermined temperature conditions, so that the impregnated resin is melted again and thermally hardened, and the insulating rigid substrate (]I0 and the sub-board are bonded to each other. The substrate (40) is firmly bonded.
サブ基板の一生面に接着性樹脂含浸シートを仮接着する
本発明によればガイドボスト等の手段によりサブ基板（
４０）の位置精度を向上させるのみで接着樹脂含浸シー
ト（６０）の位置精度が向上し、位置ずれによる含浸樹
脂のパターン汚染の問題および工程の煩雑さの問題が解
消される。なお、本発明によれば、サブ基板（４０）の
接着時には集積回路素子が固着されていないので、サブ
基板（４０）の押圧を自在に行うことができる。According to the present invention, which temporarily adheres an adhesive resin-impregnated sheet to the permanent surface of the sub-board, the sub-board (
40), the positional accuracy of the adhesive resin-impregnated sheet (60) is improved, and the problem of pattern contamination of the impregnated resin due to positional deviation and the problem of process complexity are solved. According to the present invention, since the integrated circuit element is not fixed when the sub-board (40) is bonded, the sub-board (40) can be pressed freely.
ここで、第３図を参照してサブ基板（４０）を説明する
。Here, the sub-board (40) will be explained with reference to FIG.
サブ基板（４０）は厚さ０．６ｍｍ 〜１．０ｍｍのガ
ラスエポキシ、紙エポキシ、紙フェノール、ポリイミド
等の樹脂により形成され、例えばゲートアレイ、マイク
ロコンピュータおよびメモリ等のチップを露出させる孔
（４２）あるいは切り欠き（４２）が図示するように形
成されている。なお、以下の説明により明かとなるが、
この孔（４２）はマイクロコンピュータ等の集積回路素
子の周辺にポンディングパッドを多層に配列するｔこめ
に形成されるものであって、実質的にその目的が達成さ
れる形状であれば孔に限定されるものではない。The sub-substrate (40) is made of resin such as glass epoxy, paper epoxy, paper phenol, polyimide, etc. and has a thickness of 0.6 mm to 1.0 mm, and has holes (42) for exposing chips such as gate arrays, microcomputers, and memories. ) or notches (42) are formed as shown. As will become clear from the explanation below,
This hole (42) is formed at the periphery of an integrated circuit element such as a microcomputer where bonding pads are arranged in multiple layers. It is not limited.
また、このサブ基板（４０）の両面には周知の方法によ
り、その一部を図示するように、アドレスバス、データ
バス等の導電路（４４）が形成され、適宜の位置でスル
ーホール（４６）により接続されている。In addition, conductive paths (44) such as address buses and data buses are formed on both sides of this sub-board (40) by a well-known method, as shown in part, and through holes (46) are formed at appropriate positions. ) are connected by.
所定の導電路（４４）の一部はサブ基板（４０）の周端
部に延在形成されて、絶縁硬質基板（１０）上に形成さ
れたバンドとボンディング接続されるパッド（４８）が
形成され、他の所定の導電路（４４）の一部は孔（４２
）の周囲に延在形成されて、ゲートアレイ、マイクロコ
ンピュータあるいはメモリ等の電極とボンディング接続
されるパッド（５０）が形成されている。当然のことな
がら、サブ基板（４０）のパターンを多面構成として接
着樹脂含浸シー） ＜６０）の仮接着後に単面に切断す
るのが好ましい。A part of the predetermined conductive path (44) is formed to extend on the peripheral edge of the sub-substrate (40) to form a pad (48) that is bonded to a band formed on the insulating hard substrate (10). A part of the other predetermined conductive path (44) is formed by a hole (42).
A pad (50) is formed extending around the periphery of the pad (50) to be connected by bonding to an electrode of a gate array, a microcomputer, a memory, or the like. Naturally, it is preferable that the pattern of the sub-substrate (40) be multi-sided and cut into a single plane after temporary adhesion of the adhesive resin-impregnated sheet (60).
再び第１図（Ｃ）を参照すると、サブ基板（４０）に形
成された孔（４２）により露出される所定の領域にスタ
ンプ法によりＡｇペースト層（Ｉ５）が形成される０本
発明ではＡｇペースト層（１５）の形成にスタンプ法を
使用するためサブ基板の存在がＡｇペースト層（１５）
の形成の障害とならない点に注意が必要である。Referring again to FIG. 1(C), an Ag paste layer (I5) is formed by a stamping method in a predetermined area exposed by a hole (42) formed in a sub-substrate (40). Since the stamping method is used to form the paste layer (15), the presence of the sub-substrate makes the Ag paste layer (15)
Care must be taken to ensure that it does not become an obstacle to the formation of
続いて、第１図（Ｄ）を参照すると、前記Ａｇペースト
層（１５）上にチップ状の所定の集積回路素子、例えば
第１および第２のゲートアレイ（２４）（３０）、マイ
クロコンピュータ（２６）、メモリ（２８）を載置した
後、絶縁硬質基板（］Ｏ）を】５５°Ｃ程度に加熱する
ことによりＡｇペースト層（１５）が硬化し、前記集積
回路素子を絶縁硬質基板（１０）上に形成した所定の導
電路（１４）に強固に固着する。Next, referring to FIG. 1(D), predetermined chip-shaped integrated circuit elements such as first and second gate arrays (24) (30), a microcomputer ( 26), after mounting the memory (28), the insulating hard substrate (]O) is heated to approximately 55°C to harden the Ag paste layer (15), and the integrated circuit element is mounted on the insulating hard substrate (). 10) Firmly adhere to a predetermined conductive path (14) formed above.
上記のように、また第１図に端的に示されるように、孔
（４２）により所定の集積回路素子が露出されるように
サブ基板（４０）が絶縁接着されると、第１および第２
のゲートアレイ（２４）（３０）、マイクロコンピュー
タ（２６）、メモリ（２８）の周辺にはそれら集積回路
素子の電極と接続すべきパッドが２層に配列され、最短
距離で絶縁硬質基板（１０）上の導電路（１４）あるい
はサブ基板（４０）上の導電路（４４）の何れかにワイ
ヤボンディングする、ことが可能になる。それら集積回
路素子の電極と導電路（１４）を接続するホンディング
ワイヤを参照番号（３６）、集積回路素子の電極とサブ
基板（４０）のパッド（５０）を接続するボンディング
ワイヤを参照番号（５２）、さらにサブ基板（４０）の
パッド（４８）と導電路（Ｉ４）を接続するボンディン
グワイヤを参照番号（５４）で示す。As described above and as clearly shown in FIG.
Around the gate arrays (24) (30), microcomputer (26), and memory (28), pads to be connected to the electrodes of these integrated circuit elements are arranged in two layers, and the insulating hard substrate (10 ) or the conductive path (44) on the sub-substrate (40). The bonding wires connecting the electrodes of the integrated circuit elements and the conductive paths (14) are reference number (36), and the bonding wires connecting the electrodes of the integrated circuit elements and the pads (50) of the sub-board (40) are reference number (36). 52), and a bonding wire connecting the pad (48) of the sub-board (40) and the conductive path (I4) is indicated by the reference number (54).
上記のように、本発明ではザブ基板（４０）の接着後に
チップ状の集積回路素子の固着が行われるｔこめサブ基
板（４０）の接着工程により集積回路素子が損傷するこ
とがない。また、本発明により得られる混成集積回路で
はサブ基板（４０）に形成された導電路（４４）を介し
てアドレスバス、データバス等の接続が行われるため、
絶縁硬質基板（１０）上の導電路（１４）相互の接続を
最大２個所のワイヤボンディングにより行うことができ
る。また、サブ基板（４０）の導電路（４４）は１個所
のワイヤボンディングにより絶縁硬質基板（１０）上の
任意の導電路（１４）に接続することができ、中継パッ
ド数を著しく削減することができる。また、これにより
マイクロコンピュータおよびその周辺回路素子のレイア
ウトを規格化し、図示するようにシンプルにすることが
できる。As described above, in the present invention, the integrated circuit element is not damaged by the bonding process of the T-type sub-substrate (40), in which the chip-shaped integrated circuit element is fixed after the sub-substrate (40) is bonded. Furthermore, in the hybrid integrated circuit obtained by the present invention, the address bus, data bus, etc. are connected via the conductive path (44) formed on the sub-substrate (40).
The conductive paths (14) on the insulating hard substrate (10) can be connected to each other by wire bonding at a maximum of two locations. Furthermore, the conductive path (44) on the sub-board (40) can be connected to any conductive path (14) on the insulating rigid substrate (10) by wire bonding at one location, significantly reducing the number of relay pads. I can do it. Furthermore, this allows the layout of the microcomputer and its peripheral circuit elements to be standardized and simplified as shown in the figure.
以上、本発明を一実施例に基づいて説明したが、本発明
の、例えば接着樹脂含浸シートの素材、レイアウトを規
格化すべきマイクロコンピュータおよびその周辺回路素
子の範囲、種類等は種々の変更が可能であって本発明が
実施例に限定されるものでないことは当業者に明らかで
ある。Although the present invention has been described above based on one embodiment, various changes can be made to the material of the present invention, for example, the range and type of the microcomputer and its peripheral circuit elements whose layout should be standardized. However, it is clear to those skilled in the art that the present invention is not limited to the examples.
（ト）発明の効果
以上述べたように本発明によれば、
（１）サブ基板の一生面に接着性樹脂含浸シートを仮接
着するためガイドポスト等の手段によりサブ基板の位置
精度を向上させるのみで接着樹脂含浸シートの位置精度
が向上し、位置ずれによる含浸樹脂のパターン汚染の問
題および接着工程の煩雑の問題が解消される。(G) Effects of the Invention As described above, according to the present invention, (1) In order to temporarily bond the adhesive resin-impregnated sheet to the entire surface of the sub-board, the positional accuracy of the sub-board is improved by means such as guide posts. The positional accuracy of the adhesive resin-impregnated sheet is improved by simply applying the adhesive resin, and the problem of pattern contamination of the impregnated resin due to positional deviation and the problem of complication in the bonding process are solved.
（２）半田固着工程等の比較的高温度処理工程の終了後
に接着樹脂含浸シートによるサブ基板の本接着を行うた
め接着樹脂含浸シートおよびサブ基板の熱的な絶縁破壊
が回避される。(2) Since the main bonding of the sub-board with the adhesive resin-impregnated sheet is performed after the completion of a relatively high-temperature treatment process such as a solder fixing process, thermal dielectric breakdown of the adhesive resin-impregnated sheet and the sub-board is avoided.
（３）サブ基板の接着後にチップ状の集積回路素子の固
着が行われるためサブ基板の接着工程により集積回路素
子が損傷することがない。(3) Since the chip-shaped integrated circuit element is fixed after the sub-substrate is bonded, the integrated circuit element is not damaged by the process of bonding the sub-substrate.
（４）ワイヤボンディング数が削減されるため工程が簡
素化される。また、混成集積回路の信頼性が向上する。(4) The process is simplified because the number of wire bonding is reduced. Additionally, the reliability of the hybrid integrated circuit is improved.
（５）長スパンの接続が可能になり、中継パッドが削減
されるｔｃめ実装落度が向上する。(5) It becomes possible to connect over a long span, and the number of relay pads is reduced, which improves the accuracy of mounting.
（６）マイクロコンピュータおよびその周辺回路素子の
所定の電極が最短距離で接続されるため、配線容量に起
因する障害がない。(6) Since the predetermined electrodes of the microcomputer and its peripheral circuit elements are connected by the shortest distance, there is no problem caused by wiring capacitance.
（７）マイクロコンピュータおよび周辺回路素子のレイ
アウトを小型かつ規格化することができるため、混成集
積回路のパターン設計が容易になる。(7) Since the layout of the microcomputer and peripheral circuit elements can be miniaturized and standardized, pattern design of hybrid integrated circuits becomes easier.
第１図（Ａ）乃至（Ｄ）は本発明の製造方法を説明する
図であって、それぞれ本発明に特徴的な各工程における
混成集積回路の断面図、第２図は本発明による混成集積
回路の平面図、第３図は本発明に使用されるサブ基板の
平面図、第４図は従来の製造方法による混成集積回路の
平面図。
す、 （４０） サブ基板、 （４２）・・・孔、
（４６）・スルーホール、 （６０）・・・接着樹脂含
浸シート。1A to 1D are diagrams explaining the manufacturing method of the present invention, and are sectional views of a hybrid integrated circuit at each step characteristic of the present invention, and FIG. 2 is a cross-sectional view of a hybrid integrated circuit according to the present invention. FIG. 3 is a plan view of a sub-board used in the present invention, and FIG. 4 is a plan view of a hybrid integrated circuit manufactured by a conventional manufacturing method. (40) Sub-board, (42)...hole,
(46)・Through hole, (60)・・・Adhesive resin impregnated sheet.
Claims (6)
を形成する工程と、 前記絶縁硬質基板を加熱し、前記導電路の所定位置にチ
ップ抵抗、チップコンデンサ等のチップ部品を固着する
工程と、 所定形状に配線パターンを形成したサブ基板の一主面に
このサブ基板と実質的に同一形状を有した接着性樹脂含
浸シートを仮接着する工程と、前記サブ基板を絶縁硬質
基板上の所定領域に配置し、絶縁硬質基板を所定温度に
加熱し、前記接着性樹脂含浸シートの含浸樹脂を溶融さ
せ、前記サブ基板と絶縁硬質基板を固着する工程と、前
記サブ基板を固着した後、前記絶縁硬質基板上に形成し
た導電路上にチップ状のメモリおよびマイクロコンピュ
ータ等の集積回路素子を固着する工程とを備えたことを
特徴とする混成集積回路の製造方法。(1) Forming a conductive path in a predetermined shape on an insulating hard substrate that will serve as the main substrate, and heating the insulating hard substrate to fix chip components such as chip resistors and chip capacitors in predetermined positions on the conductive path. a step of temporarily adhering an adhesive resin-impregnated sheet having substantially the same shape as the sub-board to one main surface of the sub-board on which a wiring pattern has been formed in a predetermined shape; and a step of temporarily bonding the sub-board on an insulating hard substrate. heating the insulating hard substrate to a predetermined temperature to melt the impregnated resin of the adhesive resin-impregnated sheet and fixing the sub-board and the insulating hard substrate; and after fixing the sub-board. A method for manufacturing a hybrid integrated circuit, comprising the steps of: fixing an integrated circuit element such as a chip-shaped memory or a microcomputer on a conductive surface formed on the insulating hard substrate.
請求項１記載の混成集積回路の製造方法。(2) The method for manufacturing a hybrid integrated circuit according to claim 1, characterized in that the chip components are fixed by solder.
回路素子をＡｇペーストで固着することを特徴とする請
求項１記載の混成集積回路の製造方法。(3) The method of manufacturing a hybrid integrated circuit according to claim 1, wherein the integrated circuit elements such as the memory and the microcomputer are fixed with Ag paste.
樹脂を含浸させて形成したことを特徴とする請求項１記
載の混成集積回路の製造方法。(4) The method of manufacturing a hybrid integrated circuit according to claim 1, wherein the adhesive resin-impregnated sheet is formed by impregnating paper with an epoxy adhesive resin.
ことを特徴とする請求項１記載の混成集積回路の製造方
法。(5) The method for manufacturing a hybrid integrated circuit according to claim 1, characterized in that the hard substrate is a metal substrate treated with insulation.
あるいはポリイミド等の樹脂基板を用いたことを特徴と
する請求項１記載の混成集積回路の製造方法。(6) Glass epoxy, paper phenol,
2. The method of manufacturing a hybrid integrated circuit according to claim 1, further comprising using a resin substrate made of polyimide or the like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20122390A JPH079966B2 (en) | 1990-07-31 | 1990-07-31 | Method for manufacturing hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20122390A JPH079966B2 (en) | 1990-07-31 | 1990-07-31 | Method for manufacturing hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0487356A true JPH0487356A (en) | 1992-03-19 |
| JPH079966B2 JPH079966B2 (en) | 1995-02-01 |
Family
ID=16437379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20122390A Expired - Fee Related JPH079966B2 (en) | 1990-07-31 | 1990-07-31 | Method for manufacturing hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH079966B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5576934A (en) * | 1992-07-09 | 1996-11-19 | Robert Bosch Gmbh | Mounting unit for a multilayer hybrid circuit having power components including a copper coated ceramic center board |
| JP2009033185A (en) * | 2008-09-05 | 2009-02-12 | Sanyo Electric Co Ltd | Semiconductor device and its production method |
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| US5576934A (en) * | 1992-07-09 | 1996-11-19 | Robert Bosch Gmbh | Mounting unit for a multilayer hybrid circuit having power components including a copper coated ceramic center board |
| JP2009033185A (en) * | 2008-09-05 | 2009-02-12 | Sanyo Electric Co Ltd | Semiconductor device and its production method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH079966B2 (en) | 1995-02-01 |
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