JPH0484456A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0484456A JPH0484456A JP2199555A JP19955590A JPH0484456A JP H0484456 A JPH0484456 A JP H0484456A JP 2199555 A JP2199555 A JP 2199555A JP 19955590 A JP19955590 A JP 19955590A JP H0484456 A JPH0484456 A JP H0484456A
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- forming
- type
- ion implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 abstract description 13
- 230000003321 amplification Effects 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 7
- 229910052796 boron Inorganic materials 0.000 abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- -1 boron ions Chemical class 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052785 arsenic Inorganic materials 0.000 abstract 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 7
- 108091006146 Channels Proteins 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 5
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-FTXFMUIASA-N arsenic-70 Chemical compound [70As] RQNWIZPPADIBDY-FTXFMUIASA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の製造方法に関し、特に相補型
ＭＯ８電界効果トランジスタを含む集積回路装置の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly to a method of manufacturing an integrated circuit device including complementary MO8 field effect transistors.
相補型ＭｏＳ電界効果トランジスタを含む集積回路装置
（以下ＣＭＯ８ＩＣと略す）は低消費電力であり、高集
積化が可能なことから多くの集積回路に使用されている
。An integrated circuit device including a complementary MoS field effect transistor (hereinafter abbreviated as CMO8IC) has low power consumption and can be highly integrated, so it is used in many integrated circuits.
第３図に一般的な０ＭＯ８ＩＣの断面構造図を示す。FIG. 3 shows a cross-sectional structural diagram of a general 0MO8IC.
以下製造工程順に説明する。先ず、Ｐ型半導体基板１に
Ｎ型ウェル領域２とＰ型ウェル領域３を順次形成し、素
子分離酸化膜４を形成する。次にゲート酸化膜を熱酸化
により形成し、ｖＴコントロールのためのチャンネルド
ープをＮ型ウェル領域２．Ｐ型ウェル領域３にそれぞれ
行う。The manufacturing steps will be explained below in order. First, an N-type well region 2 and a P-type well region 3 are sequentially formed on a P-type semiconductor substrate 1, and an element isolation oxide film 4 is formed. Next, a gate oxide film is formed by thermal oxidation, and channel doping for vT control is applied to the N-type well region 2. This is done in each of the P-type well regions 3.
次にゲート電極となる多結晶シリコンを全面に形成し、
Ｎ型不純物であるリンの拡散を行ない多結晶シリコン層
を低抵抗化させ所望の形状に加工する。Next, polycrystalline silicon that will become the gate electrode is formed on the entire surface.
Phosphorus, which is an N-type impurity, is diffused to lower the resistance of the polycrystalline silicon layer and process it into a desired shape.
次に、ゲート電極である多結晶シリコン９をマスクとし
て、Ｐ型ウェル領域にはＮ型高濃度ソース・ドレイン領
域１０をイオン注入法により形成し、Ｎ型ウェル領域に
はＰ型窩濃度ソース・ドレイン領域１１を形成し、０Ｍ
Ｏ３ＩＣは出来上る。Next, using the polycrystalline silicon 9 serving as the gate electrode as a mask, an N-type high-concentration source/drain region 10 is formed in the P-type well region by ion implantation, and a P-type well-concentrated source/drain region 10 is formed in the N-type well region. Form the drain region 11 and
O3IC is completed.
この従来の０ＭＯ８ＩＣでは（特にＮ型ＭＯ８ＦＥＴ）
高速、高集積化のため、横方向の微細化が進んでいるが
、それに伴い縦方向も浅くなって来ている。In this conventional 0MO8IC (especially N-type MO8FET)
In order to achieve high speed and high integration, horizontal miniaturization is progressing, but along with this, vertical dimensions are also becoming shallower.
特にＮ型ＭＯ８ＦＥＴではソース・ドレイン拡散層とＰ
型ウェルとの接合深さは、０１〜０．２μｍ程度にまで
浅く形成されている。このため、ドレイン拡散層とＰ型
ウェルとの接合は急峻であり、ドレイン近傍は高電界が
発生し、この高電界によりソースから流れて来た電子が
加速され、アバランシェ効果により電子と正孔対を発生
させる。発生した電子はドレイン側へ、正孔はウェル側
へ流れ込むことになり、ウェル側に流れ込んだ正孔は最
終的にソースへ到達するが、発生した正孔が多いとウェ
ルの抵抗が高いため、ウェルの電位を上昇させ第４図に
示す寄生ＮＰＮ）ランジスタが動作し、ドレインからソ
ースへ急激に電流が流れてしまう（スナップバック電流
）。この結果第５図のような特性となってしまい使用電
圧範囲が狭くなってしまうという問題点があった。この
ためドレイン近傍の電界を弱めるため、ドレインの構造
を二重拡散ドレイン（ＤＤＤ）としたりＬＤＤ構造を行
っているが、その効果は、スナップバック電位の抑制に
は十分ではなかった。In particular, in N-type MO8FET, the source/drain diffusion layer and P
The junction depth with the mold well is formed as shallow as about 01 to 0.2 μm. Therefore, the junction between the drain diffusion layer and the P-type well is steep, and a high electric field is generated near the drain. This high electric field accelerates the electrons flowing from the source, and the avalanche effect causes electron-hole pairing. to occur. The generated electrons will flow to the drain side, and the holes will flow to the well side, and the holes that flowed into the well side will eventually reach the source, but if there are many holes generated, the resistance of the well will be high. When the potential of the well is increased, the parasitic NPN transistor shown in FIG. 4 operates, and a current suddenly flows from the drain to the source (snapback current). As a result, the characteristics shown in FIG. 5 are obtained, resulting in a problem that the usable voltage range becomes narrow. Therefore, in order to weaken the electric field near the drain, the drain structure is made into a double diffused drain (DDD) or an LDD structure, but the effect is not sufficient to suppress the snapback potential.
又、Ｐ型ＭＯ８ＦＥＴに関しても同様である。The same applies to the P-type MO8FET.
Ｎ型ＭＯ８ＦＥＴのスナップバックの発生をおさえるに
は第４図に示す寄生ＮＰＮ Ｔｒの電流増幅率を低下
させ寄生ＮＰＮ）ランジスタが導通しにくくすることが
有効である。In order to suppress the occurrence of snapback in the N-type MO8FET, it is effective to lower the current amplification factor of the parasitic NPN transistor shown in FIG. 4 to make it difficult for the parasitic NPN transistor to conduct.
本発明では寄生ＮＰＮ）ランジスタの電流増幅率を低下
させるため、寄生ＮＰＮ）ランジスタのベース領域であ
るＰ型ウェル領域に高エネルギーのポロンイオン注入に
より、ＭＯＳ）ランシスタの特性に影響を及ぼさない領
域に高濃度のＰ型領域の島を作る工程を付加することに
より寄生ＮＰＮトランジスタのベース領域の抵抗を下げ
、電流増幅率も低下させる方法を用いている。Ｐ型Ｍ○
５ＦＥＴも同様に考えることが臼来、Ｎ型ウェル領域に
高エネルギーのリンイオン注入によりＮ型ウェル領域内
部に高濃度Ｎ型の島を形成することにより寄生ＰＮＰ
）ランジスタのベース抵抗を下げ電流増幅率を低下させ
る。In the present invention, in order to reduce the current amplification factor of the parasitic NPN) transistor, high-energy poron ions are implanted into the P-type well region, which is the base region of the parasitic NPN) transistor, in a region that does not affect the characteristics of the MOS) transistor. A method is used in which the resistance of the base region of the parasitic NPN transistor is lowered and the current amplification factor is also lowered by adding a step of creating islands of highly doped P-type regions. P type M○
5FET can be considered in the same way.Usuki said that by implanting high-energy phosphorus ions into the N-type well region, a high-concentration N-type island is formed inside the N-type well region, thereby eliminating the parasitic PNP.
) Lower the base resistance of the transistor and lower the current amplification factor.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を示す工程順
に示した断面図である。FIGS. 1(a) to 1(d) are sectional views showing an embodiment of the present invention in the order of steps.
先ず、第１図（ａ）に示すようにＰ型半導体基板１にＮ
型ウェル領域２をリンのイオン注入（１５０ＫｅＶ、
１．５ Ｘ １０ ”ａｍ−２）後、１２００℃４時間
の熱処理を行ない形成し、次にＰ型ウェル領域３をポ０
７のイオン注入（１００ＫｅＶ、 １．５ Ｘ １０
”Ｃｍ−２）後、１２００℃２時間の熱処理により形成
する。次に素子分離酸化膜４を８０００人程度熱酸化に
より形成する。First, as shown in FIG. 1(a), N is applied to a P-type semiconductor substrate 1.
Type well region 2 is implanted with phosphorus ions (150KeV,
After 1.5 x 10" am-2), heat treatment is performed at 1200°C for 4 hours to form the P-type well region 3.
7 ion implantation (100KeV, 1.5 x 10
After "Cm-2), it is formed by heat treatment at 1200 DEG C. for 2 hours. Next, the element isolation oxide film 4 is formed by thermal oxidation by about 8000 people.
次に、第１図（ｂ）に示す様にＰ型ＭＯ８ＦＥＴ形成領
域（Ｎ型ウェル領域）を開口したイオン注入マスク５
（例えばアルミニウム）を形成し、リンを５００Ｘ〜Ｉ
ＭｅＶ、 Ｉ Ｘ １０”〜Ｉ Ｘ １０”ａｍ−２
の注入条件でイオン注入し、Ｎ型ウェル領域内に高濃度
のＮ型の島６を形成する。この時、イオン注入マスクは
チャンネルドープのマスクと共用出来る。Next, as shown in FIG. 1(b), an ion implantation mask 5 with an opening for the P-type MO8FET formation region (N-type well region)
(e.g. aluminum) and phosphorus from 500X to I
MeV, I x 10"~I x 10" am-2
Ion implantation is performed under the following implantation conditions to form a highly doped N-type island 6 in the N-type well region. At this time, the ion implantation mask can be used in common with the channel doping mask.
次に、第１図（ｃ）に示す様にＮ型ＭＯ８ＦＥＴ形成領
域（Ｐ型ウェル領域）を開口したイオン注入マスク７を
形成し、ボロンを４００に〜ＩＭｅＶ。Next, as shown in FIG. 1(c), an ion implantation mask 7 with an opening in the N-type MO8FET formation region (P-type well region) is formed, and boron is heated to 400 to IMeV.
ｌ×１０１３〜ｌＸｌ０”ロー２の条件でイオン注入し
、Ｐ型ウェル領域内に高濃度のＰ型の島８を形成する。Ion implantation is performed under the condition of 1×10 13 to 1×10” low 2 to form a highly concentrated P-type island 8 in the P-type well region.
この時、イオン注入マスクはチャンネルドープのマスク
と共用出来るため、１回のイオン注入工程の増加で形成
出来る。At this time, since the ion implantation mask can be used in common with the mask for channel doping, the ion implantation process can be performed in one additional ion implantation process.
次に、第１図（ｄ）に示す様にゲート多結晶シリコン９
を形成し、Ｎ型ＭＯ８ＦＥＴ形成領域にヒ素７０ Ｋｅ
ｙ、 ５ Ｘ １０１５ｃｍ−２の条件でイオン注入し
、Ｎ型高濃度ソース・ドレイン領域１０を形成する。同
様にして、Ｐ型ＭＯ８ＦＥＴ形成領域にボロン、 ３０
ＫｅＶ、 ５ Ｘ １０１５ａｍ−２の条件でイオン注
入し、Ｐ空高濃度ソース・ドレイン領域１１を形成する
。以上のようにして本発明の半導体装置は製造される。Next, as shown in FIG. 1(d), the gate polycrystalline silicon 9
and arsenic 70 Ke in the N-type MO8FET formation region.
Ion implantation is performed under the conditions of y, 5 x 1015 cm-2 to form N-type heavily doped source/drain regions 10. Similarly, boron, 30
Ion implantation is performed under the conditions of KeV and 5 x 1015 am-2 to form P-vacant high concentration source/drain regions 11. The semiconductor device of the present invention is manufactured as described above.
第２図（ａ）〜（ｃ）は本発明の第２の実施例を工程順
に示した断面図である。FIGS. 2(a) to 2(c) are cross-sectional views showing the second embodiment of the present invention in the order of steps.
第２図（ａ）に示す様にＮ型ウェル領域２内に高濃度の
Ｎ型の島を形成する際、フィールド上の所定領域にも注
入する様にイオン注入マスクを形成し、８００〜２．０
ＭｅＶ、 １〜５ Ｘ １０ ”ｃｍ−２の条件でリ
ンのイオン注入を行う。これにより、Ｎ型ウェル内に高
濃度のＮ型の島６を作ると同時にＮ型のチャンネル・ス
トッパー領域１２を形成出来、しかもマスクはチャンネ
ルドープのイオン注入マスクと共用出来るため、リソグ
ラフィー工程を増やすことなく、イオン注入工程−回だ
けの増加で済む。As shown in FIG. 2(a), when forming a highly doped N-type island in the N-type well region 2, an ion implantation mask is formed so that the ion implantation is also carried out in a predetermined region on the field. .0
Phosphorus ion implantation is performed under the conditions of MeV and 1 to 5 x 10"cm-2. This creates a highly concentrated N-type island 6 in the N-type well and at the same time forms an N-type channel stopper region 12. Moreover, since the mask can be used in common with the ion implantation mask for channel doping, the number of ion implantation steps can be increased without increasing the number of lithography steps.
第２図（ｂ）に示す様にＰ型ウェル領域３に高濃度Ｐ型
頭域８を形成する時、所定領域のイオン注入マスクも開
口し、４００〜ＩＭｅＶ、 １〜５×１０ ”ｃｍ−
２の条件でボロンのイオン注入を行なうことにより高濃
度Ｐ型頭域８と同時にＰ型チャンネル・ストッパー領域
１３を形成する。As shown in FIG. 2(b), when forming the high-concentration P-type head region 8 in the P-type well region 3, the ion implantation mask in a predetermined region is also opened, and the ion implantation mask is heated at 400 to IMeV, 1 to 5×10”cm−.
By performing boron ion implantation under the conditions of 2, the P-type channel stopper region 13 is formed simultaneously with the high-concentration P-type head region 8.
この時イオン注入マスクは、チャンネルドープのイオン
注入マスクと共用出来るため、イオン注入工程の増加だ
けで済む。以下第１の実施例と同様に第２図（Ｃ）に示
す様にゲート多結晶シリコン層９及び高濃度Ｎ型ソース
・ドレイン領域１０゜高濃度Ｐ型ソース・ドレイン領域
１１を形成して完成する。At this time, since the ion implantation mask can be used in common with the ion implantation mask for channel doping, only an increase in the number of ion implantation steps is required. Thereafter, as in the first embodiment, a gate polycrystalline silicon layer 9, a highly doped N-type source/drain region 10°, and a highly doped P-type source/drain region 11 are formed as shown in FIG. 2(C). do.
以上説明したように本発明によれば、Ｐ型ウェル領域及
びＮ型ウェル領域内にそれぞれ高濃度のＰ型の島、Ｎ型
の島を形成することにより、スナップバックを発生させ
る寄生ＰＮＰ又はＮＰＮトランジスタの電流増幅率を低
下させることが出来、第６図に示す様にスナップバック
は発生しなくなるという効果がある。又、寄生ＰＮＰ、
ＮＰＮトランジスタの電流増幅率が小さいため、ラッチ
アップにも非常に強くなるという利点もある。As explained above, according to the present invention, by forming highly concentrated P-type islands and N-type islands in the P-type well region and the N-type well region, respectively, parasitic PNP or NPN that causes snapback can be formed. This has the effect that the current amplification factor of the transistor can be lowered, and snapback no longer occurs as shown in FIG. Also, parasitic PNP,
Since the current amplification factor of the NPN transistor is small, it also has the advantage of being extremely resistant to latch-up.
工程としてはＰ型ウェル領域及びＮ型ウェル領域に行な
うチャンネルドープのイオン注入マスクを共用出来、そ
れぞれ１回づつのイオン注入工程の増加ですむ。又、高
エネルギーイオン注入を行った場合、結晶欠陥の発生が
問題となるが、結晶欠陥は高濃度Ｎ及びＰ型の島近傍に
集中し、基板表面は無欠陥領域となるため、デバイス特
性にはほとんど影響を与えない。As for the process, the ion implantation mask for channel doping in the P-type well region and the N-type well region can be shared, and only one ion implantation step is required for each. Furthermore, when performing high-energy ion implantation, the occurrence of crystal defects becomes a problem, but the crystal defects are concentrated near the islands of high concentration N and P types, and the substrate surface becomes a defect-free region, which affects device characteristics. has almost no effect.
第２の実施例で示した様にＰ型及びＮ型のチャンネル・
ストッパー領域をウェル内高濃度Ｎ及びＰ型の島と同時
に形成することも可能であり、工程の短縮が出来るとい
う利点も発生する。この様に、イオン注入工程を１回又
は２回増やすたけで、非常に使いやすいトランジスタが
得られ、しかもラッチ７ツプにも強いという利点のある
半導体装置が出来上る。As shown in the second embodiment, P-type and N-type channels
It is also possible to form the stopper region at the same time as the high-concentration N- and P-type islands in the well, which has the advantage of shortening the process. In this way, by increasing the number of ion implantation steps by one or two times, a transistor that is extremely easy to use can be obtained, and a semiconductor device that has the advantage of being resistant to latch failures can be completed.
これまで、Ｎ型、Ｐ型ウェル領域双方に高濃度の島を設
けることを述べて来たが、Ｐ型ウェル領域内にのみ設け
ても効果は十分にある。So far, it has been described that high concentration islands are provided in both the N-type and P-type well regions, but the effect is sufficient even if they are provided only in the P-type well region.
５・・・・・・イオン注入マスク、６・・・・・・高濃
度Ｎ型領域、７・・・・・・イオン注入マスク、８・・
・・・・高濃度Ｐ型頭域、９・・・・・ゲート多結晶シ
リコン、１０・・・・・・Ｎ型ソース・ドレイン領ｔｌ
ｌ・・・・・・Ｐ型ソース・Ｆレイン領域、１２・・・
・・・Ｎ型チャンネル・ストツバ−領域、１３・・・・
・・Ｐ型チャンネル・ストッパー領域、１４・・・・・
・寄生ＮＰＮ）ランジスタ、１５・・・・寄生ＰＮＰ
）ランジスタ。5...Ion implantation mask, 6...High concentration N type region, 7...Ion implantation mask, 8...
...High concentration P type head region, 9...Gate polycrystalline silicon, 10...N type source/drain region tl
l...P-type source/F rain region, 12...
...N-type channel stopper region, 13...
...P-type channel stopper area, 14...
- Parasitic NPN) transistor, 15... Parasitic PNP
) Langista.
代理人 弁理士 内 原 晋Agent: Patent Attorney Susumu Uchihara
第１図（ａ）〜（ｄ）は本発明の一実施例を工程順に示
した断面図、第２図（ａ）〜（ｃ）は第２の実施例を示
す断面図、第３図は従来方法を示す断面図、第４図は寄
生トランジスタを示すための断面図、第５図は従来の特
性を示す工ゎ−ｖ９．特性、第６図は本発明の効果を示
す工。−ｖＤ、特性である。
１・・・・・・Ｐ型半導体基板、２・・・・・・Ｎ型ウ
ェル領域、３・・・・・・Ｐ型ウェル領域、４・・・・
・・素子分Ｍ酸化膜、（ｂ）
第 ｌ 図
第２ 図
（り
第
図
第
第４図
とン
弔
図
第６FIGS. 1(a) to (d) are cross-sectional views showing one embodiment of the present invention in the order of steps, FIGS. 2(a) to (c) are cross-sectional views showing the second embodiment, and FIG. FIG. 4 is a sectional view showing a conventional method, FIG. 4 is a sectional view showing a parasitic transistor, and FIG. 5 is a sectional view showing conventional characteristics. Characteristics: Figure 6 shows the effects of the present invention. -vD, characteristic. 1... P-type semiconductor substrate, 2... N-type well region, 3... P-type well region, 4...
...Element M oxide film, (b) Figure 1 Figure 2 (Figure 4 and Funeral Figure 6)
Claims (5)
を形成する工程と、第１導電型半導体基板内に高エネル
ギーのイオン注入を行ない、高濃度の第１導電型領域を
形成する工程とを含むことを特徴とする半導体装置の製
造方法。(1) Forming a second conductivity type well region in the first conductivity type semiconductor substrate, and performing high energy ion implantation into the first conductivity type semiconductor substrate to form a highly concentrated first conductivity type region. A method for manufacturing a semiconductor device, comprising the steps of:
を形成する工程と、第１導電型ウェル領域を形成する工
程と、この第１導電型ウェル領域内に高エネルギーイオ
ン注入を用いて高濃度の第１導電型領域を形成する工程
とを含むことを特徴とする半導体装置の製造方法。(2) A step of forming a second conductivity type well region in a first conductivity type semiconductor substrate, a step of forming a first conductivity type well region, and using high energy ion implantation into the first conductivity type well region. forming a highly concentrated first conductivity type region.
電型のウェル領域を形成する工程と、この第２導電型ウ
ェル領域内に高エネルギーイオン注入により高濃度の第
２導電型領域を形成する工程と、第１導電型ウェル領域
内に高エネルギーイオン注入を用いて高濃度第１導電型
領域を形成する工程とを含むことを特徴とする半導体装
置の製造方法。(3) forming well regions of the second conductivity type and the first conductivity type in the first conductivity type semiconductor substrate, and implanting high-concentration second conductivity type well regions into the second conductivity type well regions by high-energy ion implantation; 1. A method of manufacturing a semiconductor device, comprising: forming a region; and forming a highly concentrated first conductivity type region in a first conductivity type well region using high energy ion implantation.
ル領域を形成する工程と、素子分離酸化膜を形成する工
程と、第１導電型ウェル領域内に第１導電型高濃度領域
を高エネルギーイオン注入により形成すると同時に、素
子分離酸化膜直下に第１導電型チャンネルストッパー領
域を形成する工程とを含むことを特性とする半導体装置
の製造方法。(4) A step of forming second and first conductivity type well regions in the first conductivity type semiconductor substrate, a step of forming an element isolation oxide film, and a first conductivity type high concentration region in the first conductivity type well region. 1. A method for manufacturing a semiconductor device, comprising the step of forming a first conductivity type channel stopper region directly under an element isolation oxide film at the same time as forming a first conductivity type channel stopper region by high-energy ion implantation.
ェル領域を形成する工程と、素子分離酸化膜を形成する
工程と、第１導電型ウェル領域内に第１導電型高濃度領
域を高エネルギーイオン注入を用いて形成すると同時に
、素子分離酸化膜直下に第１導電型チャンネルストッパ
ー領域を形成する工程と、第２導電型ウェル領域内に高
エネルギーイオン注入により高濃度第２導電型ウェル領
域を形成すると同時に、素子分離酸化膜直下に第２導電
型チャンネルストッパー領域を形成する工程とを含むこ
とを特徴とする半導体装置の製造方法。(5) forming second and first conductivity type well regions in the first conductivity type semiconductor substrate; forming an element isolation oxide film; and forming a first conductivity type high concentration layer in the first conductivity type well region. A step of forming a channel stopper region of the first conductivity type directly under the element isolation oxide film at the same time as forming a channel stopper region using high energy ion implantation, and a step of forming a channel stopper region of the first conductivity type in the well region of the second conductivity type by high energy ion implantation. 1. A method of manufacturing a semiconductor device, comprising the step of forming a second conductivity type channel stopper region directly under an element isolation oxide film at the same time as forming a type well region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2199555A JPH0484456A (en) | 1990-07-27 | 1990-07-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2199555A JPH0484456A (en) | 1990-07-27 | 1990-07-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0484456A true JPH0484456A (en) | 1992-03-17 |
Family
ID=16409777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2199555A Pending JPH0484456A (en) | 1990-07-27 | 1990-07-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0484456A (en) |
-
1990
- 1990-07-27 JP JP2199555A patent/JPH0484456A/en active Pending
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