JPH0483366A - Semiconductor integrated circuit device and its manufacture - Google Patents
Semiconductor integrated circuit device and its manufactureInfo
- Publication number
- JPH0483366A JPH0483366A JP2197032A JP19703290A JPH0483366A JP H0483366 A JPH0483366 A JP H0483366A JP 2197032 A JP2197032 A JP 2197032A JP 19703290 A JP19703290 A JP 19703290A JP H0483366 A JPH0483366 A JP H0483366A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- cap
- package substrate
- solder
- solder bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229910000679 solder Inorganic materials 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 239000011347 resin Substances 0.000 claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 21
- 238000005219 brazing Methods 0.000 claims description 19
- 238000002844 melting Methods 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 238000007740 vapor deposition Methods 0.000 claims 1
- 239000000919 ceramic Substances 0.000 abstract description 7
- 239000011248 coating agent Substances 0.000 abstract description 5
- 238000000576 coating method Methods 0.000 abstract description 5
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 239000009719 polyimide resin Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 7
- 238000007789 sealing Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229920000052 poly(p-xylylene) Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
〔産業上の利用分野）
本発明は、半導体集積回路装置およびその製造技術に関
し、特にチップキャリヤ（Ｃｈｉｐ Ｃａｒｒｉｅｒ）
形半導体集積回路装置の高信頼化に適用して有効な技術
に関するものである。
〔従来の技術〕
パッケージ基板上に実装した半導体チップをキャップで
気密封止したパッケージ構造を有するチップキャリヤに
ついては、例えば特開昭６２−２４９４２９号、特開昭
６３−３１０１３９号公報などに記載されている。
第２図は、上記文献に記載されたチップキャリヤの断面
構造を示している。このチップキャリヤ２０は、ムライ
トなどのセラミック材料からなるパッケージ基板２１の
主面の電極２２上に半田バンプ２３を介して半導体チッ
プ２４をフェイスダウンボンディングし、この半導体チ
ップ２４をキャップ２５で気密封止したパッケージ構造
を備えている。キャップ２５は、窒化アルミニウム（Ａ
ＩＮ）などの高熱伝導性セラミックからなり、封止用半
田２６によってパッケージ基板２１の主面に接合されて
いる。パッケージ基板２１の主面の周縁部およびキャッ
プ２５の脚部の下面のそれぞれには、封止用半田２６の
濡れ性を向上させるためのメタライズ層２７が設けられ
ている。上記パッケージ基板２１とキャップ２５とによ
って周囲を囲まれたキャビティ、内のチップ２４の背面
（上面）は、伝熱用半田２８によってキャップ２５の下
面に接合されている。これは、チップ２４から発生した
熱を伝熱用半田２８を通じてキャップ２５に伝達するた
めである。キャップ２５の上面には必要に応じてヒート
シンク（図示せず）が接合される。上記伝熱用半田２８
の濡れ性を向上させるため、キャップ２５の下面（また
はチップ２４の背面）には、メタライズ層２７が設けら
れている。
パッケージ基板２１の内層には、例えばＷ（タングステ
ン）からなる内部配線２９が形成され、この内部配線２
９を通じてパッケージ基板２１の主面側の電極２２と下
面側の電極２２とが電気的に接続されている。下面側の
電極２２には、チップキャリヤ２０をモジュール基板な
どに実装する際の外部端子となる半田バンプ３０が接合
される。
〔発明が解決しようとする課題〕
前記チップキャリヤは、半田バンプを介してパッケージ
基板の主面に実装したチップの背面をキャップの下面に
半田付けし、さらに上記キャップをパッケージ基板の主
面に半田付けしたパッケージ構造を有している。そのた
め、チップ、パッケージ基板およびキャップの熱膨張係
数差に起因して、接合面積が最も小さい箇所であるパッ
ケージ基板の電極と半田バンプとの界面に応力が集中し
易く、半田バンプの接続信頼性や接続寿命を充分に確保
することが困難であった。
また、前記チップキャリヤは、高価なセラミック製の多
層配線基板をパッケージ基板に用いているため、これが
チップキャリヤの製造コストを高くする一因になってい
た。
本発明は、上記した問題点に着目してなされたものであ
り、その目的は、チップキャリヤ形半導体集積回路装置
の信頼性を向上させる技術を提供することにある。
本発明の他の目的は、チップキャリヤ形半導体集積回路
装置の製造コストを低減する技術を提供することにある
。
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。
〔課題を解決するための手段〕
本戦において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、次のとおりである。
本願の一発明は、可撓性樹脂で構成したパッケージ基板
の主面に半田バンプを介してフェイスダウンボンディン
グしたチップの背面にろう材を介してキャップを接合す
るとともに、上記チップの表面に耐湿性有機被膜をコー
ティングしたチップキャリヤ形半導体集積回路装置であ
る。
〔作用〕
上記した手段によれば、パッケージ基板を可撓性樹脂で
構成したことにより、パッケージ基板の電極と半田バン
プとの界面に集中した応力をパッケージ基板の変形によ
って緩和、吸収することができる。また、パッケージ基
板とキャップとが接触しない構造となっているため、パ
ッケージ基板の電極と半田バンプとの界面に集中する応
力を小さくすることができる。一方、チップの表面に耐
湿性有機被膜をコーティングしたことにより、チップを
気密封止しなくともその耐湿性を確保することができる
。また、チップの背面にろう材を介してキャップを接合
することにより、チップの放熱性を確保することができ
る。
さらに、パッケージ基板を樹脂で構成したことにより、
パッケージ基板を高価なセラミックで構成する場合に比
べてチップキャリヤの製造コストが低減される。
〔実施例〕
第１図に示すように、本実施例のチップキャリヤ１は、
ポリイミド樹脂からなるパッケージ基板２の主面の電極
３上に半田バンプ４を介して半導体チップ５をフェイス
ダウンボンディングし、さらに上記チップ５の背面にろ
う材６を介してキャツブ７を接合したパッケージ構造を
備えている。
上記キャップ７は、ＡＩＮなどの高熱伝導性セラミック
からなり、その上には図示しないヒートシンクが搭載さ
れ、チップ５からろう材６を通じてキャップ７に伝達さ
れた熱を上記ヒートシンクの表面から外部に逃がす構造
になっている。上記半田バンプ４およびろう材６は、例
えば３〜４重量％程度のＳｎを含有するＰ ｂ ／ Ｓ
ｎ合金（溶融温度＝３２０〜３３０℃程度）からなる
。上記キャップ７の下面には、ろう材６の濡れ性を向上
させるためのメタライズ層８が設けられている。上記メ
タライズ層８は、例えばＴｉ、ＮｉおよびＡｕの薄膜を
積層した複合金属膜からなる。上記メタライズ層８は、
チップ５の背面に設けてもよい。
パッケージ基板２の内層には、例えばＣｕからなる内部
配線９が形成されており、上記内部配線９を通じてパッ
ケージ基板２の主面側の電極３と下面側の電極３とが電
気的に接続されている。上記下面側の電極３には、チッ
プキャリヤ１をモジュール基板などに実装する際の外部
端子となる半田バンプ１０が接合される。上記半田バン
プ１０は、半田バンプ４およびろう材６よりも低融点の
半田、例えば１０重量％程度のＳｎを含有するＰｂ／Ｓ
ｎ合金（溶融温度＝２９０〜３３０℃程度）または３０
重量％程度のＳｎを含有するＰｂ／Ｓｎ合金（溶融温度
＝２５０〜２６０℃程度）からなる。
上記チップキャリヤｌは、キャップ７の脚部とパッケー
ジ基板２の主面との間に僅かな隙間が設けられており、
キャップ７とパッケージ基板２とが接触しないパッケー
ジ構造となっている。そして、上記キャップ７とパッケ
ージ基板２とによって周囲を囲まれたキャビティ１１の
内部におけるチップ５、半田バンプ４、電極３、キャッ
プ７およびパッケージ基板２のそれぞれの表面には、膜
厚が１〜２μｍ程度の耐湿性有機被膜１２がコーティン
グされている。上配耐湿性有機被腹１２は、例えばパリ
レン樹脂からなる。
上記チップキャリヤ１を組み立てるには、まず集積回路
形成面の電極パッド１３上に半田バンプ４を形成したチ
ップ５を用意し、上記チップ５をその集積回路形成面を
下に向けてパッケージ基板２の主面に載せ、半田バンプ
４と電極３とを正確に位置合わせする。この位置合わせ
はチップマウント装置などの機械を用いて行う。続いて
チップ５の背面にその寸法に合わせて成形した板状のろ
う材６を載せ、さらにろう材６の上にキャップ７を被せ
る。次に、上記パッケージ基板２をリフロー炉に搬送し
、炉内の温度を半田バンプ４およびろう材６の溶融温度
よりも幾分高め（３４０〜３５０℃程度）に設定して半
田バンプ４およびろう材６を加熱、溶融することによっ
て、チップ５をパッケージ基板２の主面にフェイスダウ
ンボンディングするとともに、チップ５の背面とキャッ
プ７の下面とをろう材６で接合する。上記リフロー炉内
には、半田バンプ４やろう材６０表面の酸化を防止する
ために、窒素、アルゴンなどの不活性ガス、または上記
不活性ガスに水素を混合した還元性ガスが充填される。
また、半田バンプ４およびろう材６を加熱、溶融した際
にキャップ７の重みで半田バンプ４が潰れる虞れのある
場合は、例えばキャップ７の脚部とパッケージ基板２の
主面との隙間に薄い板材を挿入することによって、キャ
ップ７が必要以上に沈み込むのを防止する。
次に、例えばパリレン樹脂のような耐湿性有機樹脂を加
熱し、低分子化したその蒸気をキャップ７とパッケージ
基板２との隙間を通じてキャビティ１１内に流入する。
これにより、上記耐湿性有機樹脂の低分子蒸気は、チッ
プ５、半田バンプ４、電極３、キャップ７およびパッケ
ージ基板２のそれぞれの表面で冷却され、耐湿性有機被
膜１２となる。上記耐湿性有機被膜１２は、水分を吸着
する性質を有しているため、キャップ７とパッケージ基
板２との隙間を通じてキャビティ１１内に浸入した水分
がチップ５の内部に浸入することはない。
最後に、パッケージ基板２の下面側の電極３に半田バン
プ１０を接合することにより、上記チップキャリヤ１が
完成する。
上記のように構成された本実施例のチップキャリヤ１に
よれば、下記のような作用、効果を得ることができる。
（１）、パッケージ基板２を可撓性樹脂で構成したこと
により、電極３と半田バンプ４との界面に集中した応力
がパッケージ基板２の変形によって緩和、吸収される。
（２）、パッケージ基板２とキャップ７とが接触しない
パッケージ構造にしたことにより、電極３と半田バンプ
４との界面に集中する応力が低減される。
（３）、上記（１〕、（２）により、半田バンプ４の接
続信頼性や接続寿命を充分に確保することできる。
（４）、チップ５の表面に耐湿性有機被膜１２をコーテ
ィングしたことにより、チップ５を気密封止しないパッ
ケージ構造であるにもかかわらず、チップ５の耐湿性を
充分に確保することができる。
（５）、チップ５の背面にろう材６を介してキャップ７
を接合したことにより、チップ５の放熱性を充分に確保
することができる。
（６）、上記（３）〜（５）により、信頼性の高いチッ
プキャリヤ１を提供することができる。
（７）、パッケージ基板２をセラミックよりも安価なポ
リイミド樹脂で構成したことにより、その製造コストが
低減される。
（８）、半田バンプ４とろう材６とを同一の半田材料で
構成したことにより、チップ５をパッケージ基板２にフ
ェイスダウンボンディングする作業と、チップ５とキャ
ップ７とを接合する作業とを同時に行うことができるの
で、チップキャリヤ１の組立て工程が低減される。
（９）、パッケージ基板２とキャップ７とが接触しない
パッケージ構造にしたことにより、パッケージ基板２の
主面の周辺部やキャップ７の脚部に封止用半田の濡れ性
を向上させるためのメタライズ層を設ける工程が不要と
なるので、チップキャリヤ１の組立て工程が低減される
。
σ〔、上記（７）〜[Industrial Application Field] The present invention relates to a semiconductor integrated circuit device and its manufacturing technology, and particularly to a chip carrier.
The present invention relates to techniques that are effective when applied to increase the reliability of semiconductor integrated circuit devices. [Prior Art] Chip carriers having a package structure in which a semiconductor chip mounted on a package substrate is hermetically sealed with a cap are described in, for example, Japanese Patent Laid-Open No. 62-249429 and Japanese Patent Laid-Open No. 63-310139. ing. FIG. 2 shows the cross-sectional structure of the chip carrier described in the above-mentioned document. This chip carrier 20 has a semiconductor chip 24 face-down bonded onto an electrode 22 on the main surface of a package substrate 21 made of a ceramic material such as mullite via solder bumps 23, and this semiconductor chip 24 is hermetically sealed with a cap 25. It has a unique package structure. The cap 25 is made of aluminum nitride (A
It is made of highly thermally conductive ceramic such as IN) and is bonded to the main surface of the package substrate 21 with sealing solder 26. A metallized layer 27 is provided on each of the peripheral edge of the main surface of the package substrate 21 and the lower surface of the legs of the cap 25 to improve the wettability of the sealing solder 26. The back surface (upper surface) of the chip 24 inside the cavity surrounded by the package substrate 21 and the cap 25 is bonded to the lower surface of the cap 25 with heat transfer solder 28 . This is to transfer the heat generated from the chip 24 to the cap 25 through the heat transfer solder 28. A heat sink (not shown) is bonded to the upper surface of the cap 25, if necessary. The above heat transfer solder 28
A metallized layer 27 is provided on the lower surface of the cap 25 (or the back surface of the chip 24) in order to improve the wettability of the cap 25. An internal wiring 29 made of, for example, W (tungsten) is formed in the inner layer of the package substrate 21.
The electrode 22 on the main surface side of the package substrate 21 and the electrode 22 on the lower surface side are electrically connected through 9 . Solder bumps 30 that serve as external terminals when the chip carrier 20 is mounted on a module substrate or the like are bonded to the electrodes 22 on the lower surface side. [Problem to be Solved by the Invention] The chip carrier is provided by soldering the back side of the chip mounted on the main surface of the package substrate via solder bumps to the lower surface of the cap, and further soldering the cap to the main surface of the package substrate. It has an attached package structure. Therefore, due to the difference in thermal expansion coefficient between the chip, the package substrate, and the cap, stress tends to concentrate at the interface between the package substrate electrode and the solder bump, where the bonding area is the smallest, and the connection reliability of the solder bump is affected. It was difficult to ensure a sufficient connection life. Furthermore, since the chip carrier uses an expensive ceramic multilayer wiring board as a package substrate, this has been a factor in increasing the manufacturing cost of the chip carrier. The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide a technique for improving the reliability of a chip carrier type semiconductor integrated circuit device. Another object of the present invention is to provide a technique for reducing the manufacturing cost of a chip carrier type semiconductor integrated circuit device. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] Among the inventions disclosed in this competition, a brief overview of typical inventions is as follows. One invention of the present application is to bond a cap via a brazing material to the back surface of a chip that is face-down bonded to the main surface of a package substrate made of a flexible resin via solder bumps, and to attach a cap to the back surface of the chip using a brazing material. This is a chip carrier type semiconductor integrated circuit device coated with an organic film. [Function] According to the above means, since the package substrate is made of flexible resin, the stress concentrated at the interface between the electrodes of the package substrate and the solder bumps can be alleviated and absorbed by deformation of the package substrate. . Furthermore, since the package substrate and the cap do not come into contact with each other, stress concentrated at the interface between the electrodes of the package substrate and the solder bumps can be reduced. On the other hand, by coating the surface of the chip with a moisture-resistant organic film, the moisture resistance of the chip can be ensured without hermetically sealing the chip. Furthermore, by bonding the cap to the back surface of the chip via a brazing material, the heat dissipation performance of the chip can be ensured. Furthermore, by composing the package substrate with resin,
The cost of manufacturing the chip carrier is reduced compared to when the package substrate is made of expensive ceramic. [Example] As shown in FIG. 1, the chip carrier 1 of this example is
A package structure in which a semiconductor chip 5 is face-down bonded onto an electrode 3 on the main surface of a package substrate 2 made of polyimide resin via a solder bump 4, and a cap 7 is further bonded to the back surface of the chip 5 via a brazing material 6. It is equipped with The cap 7 is made of highly thermally conductive ceramic such as AIN, has a heat sink (not shown) mounted thereon, and has a structure that allows heat transferred from the chip 5 to the cap 7 through the brazing material 6 to escape from the surface of the heat sink. It has become. The solder bumps 4 and the brazing filler metal 6 are made of, for example, Pb/S containing about 3 to 4% by weight of Sn.
n alloy (melting temperature = about 320 to 330°C). A metallized layer 8 is provided on the lower surface of the cap 7 to improve the wettability of the brazing material 6. The metallized layer 8 is made of a composite metal film in which thin films of Ti, Ni, and Au are laminated, for example. The metallized layer 8 is
It may also be provided on the back surface of the chip 5. An internal wiring 9 made of, for example, Cu is formed in the inner layer of the package substrate 2, and the electrode 3 on the main surface side of the package substrate 2 and the electrode 3 on the lower surface side are electrically connected through the internal wiring 9. There is. Solder bumps 10, which serve as external terminals when the chip carrier 1 is mounted on a module substrate or the like, are bonded to the electrodes 3 on the lower surface side. The solder bump 10 is made of solder having a lower melting point than the solder bump 4 and the brazing filler metal 6, for example, Pb/S solder containing about 10% by weight of Sn.
n alloy (melting temperature = about 290-330℃) or 30
It is made of a Pb/Sn alloy (melting temperature = about 250 to 260°C) containing about % by weight of Sn. The chip carrier 1 has a slight gap between the leg of the cap 7 and the main surface of the package substrate 2,
The package structure is such that the cap 7 and the package substrate 2 do not come into contact with each other. The surfaces of the chip 5, the solder bumps 4, the electrodes 3, the cap 7, and the package substrate 2 inside the cavity 11 surrounded by the cap 7 and the package substrate 2 have a film thickness of 1 to 2 μm. It is coated with a moisture-resistant organic film 12 of a certain degree. The upper moisture-resistant organic covering 12 is made of, for example, parylene resin. To assemble the chip carrier 1, first prepare a chip 5 with solder bumps 4 formed on the electrode pads 13 on the integrated circuit forming surface, and place the chip 5 on the package substrate 2 with the integrated circuit forming surface facing down. Place it on the main surface and accurately align the solder bumps 4 and electrodes 3. This alignment is performed using a machine such as a chip mount device. Subsequently, a plate-shaped brazing material 6 formed to match the dimensions of the chip 5 is placed on the back surface of the chip 5, and a cap 7 is placed on top of the brazing material 6. Next, the package substrate 2 is transferred to a reflow furnace, and the temperature inside the furnace is set to be slightly higher (about 340 to 350°C) than the melting temperature of the solder bumps 4 and the solder material 6, and the solder bumps 4 and the solder material 6 are heated. By heating and melting the material 6, the chip 5 is face-down bonded to the main surface of the package substrate 2, and the back surface of the chip 5 and the lower surface of the cap 7 are joined using the brazing material 6. In order to prevent the surfaces of the solder bumps 4 and the brazing material 60 from being oxidized, the reflow oven is filled with an inert gas such as nitrogen or argon, or a reducing gas made by mixing the inert gas with hydrogen. In addition, if there is a risk that the solder bumps 4 may be crushed by the weight of the cap 7 when the solder bumps 4 and the brazing material 6 are heated and melted, the gap between the legs of the cap 7 and the main surface of the package substrate 2, for example, should be By inserting the thin plate material, the cap 7 is prevented from sinking more than necessary. Next, a moisture-resistant organic resin such as parylene resin is heated, and its vapor, which has been reduced to a low molecular weight, flows into the cavity 11 through the gap between the cap 7 and the package substrate 2. As a result, the low-molecular vapor of the moisture-resistant organic resin is cooled on each surface of the chip 5, solder bumps 4, electrodes 3, cap 7, and package substrate 2, and becomes a moisture-resistant organic coating 12. Since the moisture-resistant organic coating 12 has the property of adsorbing moisture, moisture that has entered the cavity 11 through the gap between the cap 7 and the package substrate 2 will not infiltrate into the inside of the chip 5. Finally, the chip carrier 1 is completed by bonding the solder bumps 10 to the electrodes 3 on the lower surface of the package substrate 2. According to the chip carrier 1 of this embodiment configured as described above, the following actions and effects can be obtained. (1) Since the package substrate 2 is made of flexible resin, the stress concentrated at the interface between the electrode 3 and the solder bump 4 is relaxed and absorbed by the deformation of the package substrate 2. (2) By adopting a package structure in which the package substrate 2 and the cap 7 do not come into contact with each other, stress concentrated at the interface between the electrode 3 and the solder bump 4 is reduced. (3) Through (1) and (2) above, the connection reliability and connection life of the solder bumps 4 can be sufficiently ensured. (4) The surface of the chip 5 is coated with a moisture-resistant organic film 12. As a result, the moisture resistance of the chip 5 can be sufficiently ensured even though the package structure does not hermetically seal the chip 5. (5) The cap 7 is attached to the back of the chip 5 via the brazing material 6
By bonding them together, sufficient heat dissipation performance of the chip 5 can be ensured. (6) With the above (3) to (5), a highly reliable chip carrier 1 can be provided. (7) Since the package substrate 2 is made of polyimide resin, which is cheaper than ceramic, the manufacturing cost is reduced. (8) By configuring the solder bumps 4 and the brazing material 6 with the same solder material, the work of face-down bonding the chip 5 to the package substrate 2 and the work of joining the chip 5 and the cap 7 can be performed simultaneously. Therefore, the assembly process of the chip carrier 1 is reduced. (9) By adopting a package structure in which the package substrate 2 and the cap 7 do not come into contact with each other, metallization is applied to the periphery of the main surface of the package substrate 2 and the legs of the cap 7 to improve the wettability of the sealing solder. Since the process of providing layers is not necessary, the assembly process of the chip carrier 1 is reduced. σ [, above (7) ~
〔９〕により、チップキャリヤ１を
安価に提供することができる。
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は、前記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。
本発明は、例えばパッケージ基板２の主面に複数のチッ
プを実装したマルチチップキャリヤに適用することもで
きる。
〔発明の効果〕
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。
可撓性樹脂で構成したパッケージ基板の主面に半田バン
プを介してフェイスダウンボンディングしたチップの背
面にろう材を介してキャップを接合するとともに、上記
チップの表面に耐湿性有機被膜をコーティングしたチッ
プキャリヤ形半導体集積回路装置構造とすることにより
、半田バンプの接続信頼性や接続寿命、チップの耐湿性
およびチップの放熱性が充分に確保されるので、信頼性
の高いチップキャリヤ形半導体集積回路装置を提供する
ことができる。
また、パッケージ基板をセラミックよりも安価な樹脂で
構成したことにより、チップキャリヤ形半導体集積回路
装置を安価に提供することができる。[9] makes it possible to provide the chip carrier 1 at low cost. As above, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist thereof. Needless to say. The present invention can also be applied to, for example, a multi-chip carrier in which a plurality of chips are mounted on the main surface of the package substrate 2. [Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below. A chip that is face-down bonded to the main surface of a package substrate made of flexible resin via solder bumps, a cap is bonded to the back side of the chip via a brazing material, and the surface of the chip is coated with a moisture-resistant organic film. The carrier type semiconductor integrated circuit device structure ensures sufficient connection reliability and connection life of solder bumps, chip moisture resistance, and chip heat dissipation, resulting in a highly reliable chip carrier type semiconductor integrated circuit device. can be provided. Furthermore, since the package substrate is made of resin, which is cheaper than ceramic, the chip carrier type semiconductor integrated circuit device can be provided at low cost.
第１図は、本発明の一実施例であるチップキャリヤ形半
導体集積回路装置を示す断面図、第２図は、従来のチッ
プキャリヤ形半導体集積回路装置を示す要部破断正面図
である。
１．２０・・・チップキャリヤ、２．２１・・・パッケ
ージ基板、３．２２・・・電極、４，１０．２３．３０
・・・半田バンプ、５．２４・・・半導体チップ、６・
・・ろう材、７．２５・・・キャップ、８．２７・・・
メタライズ層、９゜２９・・・内部配線、 １１・・
・キャビティ、１２・・・耐湿性有機被膜、１３・・・
電極パッド、２６・・・封止用半田、２８・・・伝熱用
半田。
代理人 弁理士 筒 井 大 和FIG. 1 is a sectional view showing a chip carrier type semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a front view with a main part cut away showing a conventional chip carrier type semiconductor integrated circuit device. 1.20...Chip carrier, 2.21...Package substrate, 3.22...Electrode, 4,10.23.30
...Solder bump, 5.24...Semiconductor chip, 6.
... Brazing filler metal, 7.25 ... Cap, 8.27 ...
Metallized layer, 9°29...Internal wiring, 11...
・Cavity, 12... Moisture-resistant organic coating, 13...
Electrode pad, 26...Solder for sealing, 28...Solder for heat transfer. Agent Patent Attorney Daiwa Tsutsui
Claims (1)
バンプを介してフェイスダウンボンディングした半導体
チップの背面にろう材を介してキャップを接合するとと
もに、前記半導体チップの表面に耐湿性有機被膜をコー
ティングしたことを特徴とする半導体集積回路装置。 ２、半田バンプの溶融温度とほぼ等しいか低温の溶融温
度を有するろう材を用いて半導体チップの背面にキャッ
プを接合することを特徴とする請求項１記載の半導体集
積回路装置の製造方法。 ３、蒸着法を用いて半導体チップの表面に耐湿性有機被
膜をコーティングすることを特徴とする請求項１記載の
半導体集積回路装置の製造方法。[Claims] 1. A cap is bonded via a brazing material to the back side of a semiconductor chip which is face-down bonded to the main surface of a package substrate made of flexible resin via solder bumps, and A semiconductor integrated circuit device characterized by having its surface coated with a moisture-resistant organic film. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the cap is bonded to the back surface of the semiconductor chip using a brazing material having a melting temperature substantially equal to or lower than the melting temperature of the solder bumps. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the surface of the semiconductor chip is coated with a moisture-resistant organic film using a vapor deposition method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2197032A JPH0483366A (en) | 1990-07-25 | 1990-07-25 | Semiconductor integrated circuit device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2197032A JPH0483366A (en) | 1990-07-25 | 1990-07-25 | Semiconductor integrated circuit device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0483366A true JPH0483366A (en) | 1992-03-17 |
Family
ID=16367607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2197032A Pending JPH0483366A (en) | 1990-07-25 | 1990-07-25 | Semiconductor integrated circuit device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0483366A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0797247A1 (en) * | 1996-03-21 | 1997-09-24 | Matsushita Electric Industrial Co., Ltd | Substrate on which bumps are formed and method of forming the same |
| US6271058B1 (en) | 1998-01-06 | 2001-08-07 | Nec Corporation | Method of manufacturing semiconductor device in which semiconductor chip is mounted facedown on board |
| JP2008545265A (en) * | 2005-07-07 | 2008-12-11 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Package, method of manufacturing the package, and use of the method |
| JP2011091436A (en) * | 2011-01-11 | 2011-05-06 | Fujitsu Ltd | Packaged device |
-
1990
- 1990-07-25 JP JP2197032A patent/JPH0483366A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0797247A1 (en) * | 1996-03-21 | 1997-09-24 | Matsushita Electric Industrial Co., Ltd | Substrate on which bumps are formed and method of forming the same |
| US5914274A (en) * | 1996-03-21 | 1999-06-22 | Matsushita Electric Industrial Co., Ltd. | Substrate on which bumps are formed and method of forming the same |
| US6042953A (en) * | 1996-03-21 | 2000-03-28 | Matsushita Electric Industrial Co., Ltd. | Substrate on which bumps are formed and method of forming the same |
| US6271058B1 (en) | 1998-01-06 | 2001-08-07 | Nec Corporation | Method of manufacturing semiconductor device in which semiconductor chip is mounted facedown on board |
| JP2008545265A (en) * | 2005-07-07 | 2008-12-11 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Package, method of manufacturing the package, and use of the method |
| JP2011091436A (en) * | 2011-01-11 | 2011-05-06 | Fujitsu Ltd | Packaged device |
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