JPH0478184B2 - - Google Patents
Info
- Publication number
- JPH0478184B2 JPH0478184B2 JP59243306A JP24330684A JPH0478184B2 JP H0478184 B2 JPH0478184 B2 JP H0478184B2 JP 59243306 A JP59243306 A JP 59243306A JP 24330684 A JP24330684 A JP 24330684A JP H0478184 B2 JPH0478184 B2 JP H0478184B2
- Authority
- JP
- Japan
- Prior art keywords
- package
- welding
- layer
- pins
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 12
- 238000003466 welding Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910000640 Fe alloy Inorganic materials 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000007747 plating Methods 0.000 description 4
- 238000005219 brazing Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はピン・グリツド・アレイ型等の底面に
接続ピンを有する半導体装置パツケージの製造方
法に係り、半導体装置パツケージに接続ピンを装
着する方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device package having connection pins on the bottom surface of a pin grid array type, etc., and a method for attaching connection pins to a semiconductor device package. Regarding.
半導体装置パツケージに接続ピンを装着するの
に、従来はＡｇろう材を使用して、電極パツドに
接続ピンをろう付けしていた。このろう付け工程
はチツプ実装前に行なうが、パツケージを約600
℃に加熱するので、パツケージ全体に熱応力を与
える欠点を有する。
Conventionally, to attach connecting pins to a semiconductor device package, the connecting pins were brazed to electrode pads using Ag brazing material. This brazing process is performed before chip mounting, and the package is approximately 600
Since it is heated to ℃, it has the disadvantage of imparting thermal stress to the entire package.
上記欠点を解消することである。 The purpose is to eliminate the above drawbacks.
〔問題点を解決するための手段〕
半導体装置パツケージに接続ピンを装着する方
法であつて、パツケージの電極パツドにNi層を
被覆して溶接中間層とし、この層を介してNi含
有Fe合金接続ピンを電気溶接することを特徴と
する方法によつて、この問題を解決することがで
きる。[Means for solving the problem] A method of attaching connection pins to a semiconductor device package, in which the electrode pads of the package are coated with a Ni layer to form a welding intermediate layer, and a Ni-containing Fe alloy connection is made through this layer. This problem can be solved by a method characterized by electric welding of the pins.
第１図に示すように、通常のセラミツクパツケ
ージ１は底面（図では上面）に電極パツド２を有
し、これはバイアホール３および内層パターン４
を介して、外周めつき用端子５に接続している。
As shown in FIG. 1, a typical ceramic package 1 has an electrode pad 2 on the bottom surface (top surface in the figure), which is connected to a via hole 3 and an inner layer pattern 4.
It is connected to the outer circumferential plating terminal 5 via.
この電極パツド２に電気溶接すべき接続ピン６
として、材質は通常のように42％Ni含有Fe合金
または29％Ni，17％Co含有Fe合金を使用するこ
とができるが、上端部は溶接時に外部電源との接
続を容易にするために平板状とすることが便宜で
あり、この上端部は溶接した後に切断する。また
電極面への装着を確実にするために下端部を円錐
状にすることが便宜である。 Connection pin 6 to be electrically welded to this electrode pad 2
As for the material, 42% Ni-containing Fe alloy or 29% Ni, 17% Co-containing Fe alloy can be used as usual, but the upper end is a flat plate to facilitate connection with an external power source during welding. It is convenient to have a shape, and this upper end is cut after welding. It is also convenient to make the lower end conical in order to ensure attachment to the electrode surface.
電極パツド２は、通常のように材質をＷまたは
Moとすることができるが、これらの金属は接続
ピンのNi含有Fe合金との融着性が良好でないの
で、電極パツド２の上に溶接中間層としてNi層
を被覆することが必要である。この層は蒸着また
はめつきによつて形成することができる。 The material of the electrode pad 2 is W or W as usual.
However, since these metals do not have good fusion properties with the Ni-containing Fe alloy of the connecting pin, it is necessary to cover the electrode pad 2 with a Ni layer as a welding intermediate layer. This layer can be formed by vapor deposition or plating.
電気溶接を行なうときは、接続ピン６の上端部
とパツケージ１の外周めつき用端子５とを外部電
源に接続して、接続ピン６の下端面を電極パツド
２を被覆するNi層７に押圧し、接触面で発熱さ
せる。下端面の直径が0.2mmのとき交流電圧数百
Ｖを印加して溶接することができた。 When performing electric welding, the upper end of the connecting pin 6 and the terminal 5 for plating the outer periphery of the package 1 are connected to an external power source, and the lower end of the connecting pin 6 is pressed against the Ni layer 7 covering the electrode pad 2. and generates heat on the contact surface. When the diameter of the lower end surface was 0.2 mm, welding could be performed by applying an AC voltage of several hundred volts.
本発明の方法は、接続ピンの接着性が良好であ
るのみならず、局部加熱であるので、パツケージ
全体に熱応力を与えることがなく、かつ従来のろ
う付け工程のようにろう材のだれがないので、接
続ピンの間隔を従来の約1.27〜2.54mmから0.5mmと
することができる。
The method of the present invention not only provides good adhesion of the connecting pins, but also uses local heating, so it does not apply thermal stress to the entire package, and unlike the conventional brazing process, there is no dripping of the filler metal. Therefore, the spacing between the connecting pins can be reduced from the conventional approximately 1.27 to 2.54 mm to 0.5 mm.
第１図は本発明の方法によつて半導体装置パツ
ケージに接続ピンを溶接する工程を示す断面図で
ある。
１……パツケージ、２……電極パツド、３……
バイアホール、４……内層パターン、５……外周
めつき用端子、６……接続ピン、７……溶接中間
層。
FIG. 1 is a sectional view showing the process of welding a connecting pin to a semiconductor device package by the method of the present invention. 1...Package, 2...Electrode pad, 3...
Via hole, 4... Inner layer pattern, 5... Terminal for outer plating, 6... Connection pin, 7... Welding intermediate layer.
Claims (1)
方法であつて、パツケージの電極パツドにNi層
を被覆して溶接中間層とし、この層を介してNi
含有Fe合金接続ピンを電気溶接することを特徴
とする方法。 ２ Ni，Co含有Fe合金接続ピンを電気溶接す
る、特許請求の範囲第１項記載の方法。[Claims] 1. A method for attaching connection pins to a semiconductor device package, which includes coating electrode pads of the package with a Ni layer to form a welding intermediate layer, and applying Ni through this layer.
A method characterized by electrically welding Fe-containing alloy connecting pins. 2. The method according to claim 1, wherein Ni, Co-containing Fe alloy connection pins are electrically welded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24330684A JPS61123160A (en) | 1984-11-20 | 1984-11-20 | Welding method for pin of package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24330684A JPS61123160A (en) | 1984-11-20 | 1984-11-20 | Welding method for pin of package for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61123160A JPS61123160A (en) | 1986-06-11 |
| JPH0478184B2 true JPH0478184B2 (en) | 1992-12-10 |
Family
ID=17101869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24330684A Granted JPS61123160A (en) | 1984-11-20 | 1984-11-20 | Welding method for pin of package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61123160A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4970570A (en) * | 1986-10-28 | 1990-11-13 | International Business Machines Corporation | Use of tapered head pin design to improve the stress distribution in the braze joint |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5466467A (en) * | 1977-11-04 | 1979-05-29 | Hitachi Ltd | Method of connecting parts to printed circuit substrate |
-
1984
- 1984-11-20 JP JP24330684A patent/JPS61123160A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5466467A (en) * | 1977-11-04 | 1979-05-29 | Hitachi Ltd | Method of connecting parts to printed circuit substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61123160A (en) | 1986-06-11 |
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