JPH0475191A - Ic card - Google Patents
Ic cardInfo
- Publication number
- JPH0475191A JPH0475191A JP2191642A JP19164290A JPH0475191A JP H0475191 A JPH0475191 A JP H0475191A JP 2191642 A JP2191642 A JP 2191642A JP 19164290 A JP19164290 A JP 19164290A JP H0475191 A JPH0475191 A JP H0475191A
- Authority
- JP
- Japan
- Prior art keywords
- sram
- signal line
- power supply
- data
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000000872 buffer Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はSRAMを搭載し、高速アクセスかつデータ
保持が長寿命のICカードに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC card equipped with an SRAM, which provides high-speed access and long-life data retention.
第2図は従来のSRAMを搭載したICカードの回路を
示すブロック図である。図において111FiIc:l
’J−ド、(2)は外部Vca電源、(3)はGND電
源、I4)は電源切り替え回路、(6)は電池。FIG. 2 is a block diagram showing a circuit of an IC card equipped with a conventional SRAM. In the figure 111FiIc:l
'J-de, (2) is an external Vca power supply, (3) is a GND power supply, I4) is a power supply switching circuit, and (6) is a battery.
61は抵抗、)7)はダイオード、(8)は内部Vcc
電源、191#:tSRAM、1αはアドレスバス%(
ロ)ハDE信号線、■はCFi信号線、+1場はVZC
信号線。61 is a resistor, )7) is a diode, (8) is an internal Vcc
Power supply, 191#: tSRAM, 1α is address bus% (
B) DE signal line, ■ is CFi signal line, +1 field is VZC
Signal line.
Iはデータバス%a6は電池電源である。I is a data bus %a6 is a battery power supply.
次に動作について説明する。従来のICカード…は外部
Vcc電源(りの電圧と、電池電源QFAの電圧を電源
切り替え回路(41によって比較し、高い電圧電圧の電
源を内部Vcc電源(81としてIOカード111内部
に供給することになる。すなわち、通常8 RA M
+91に読み出し動作や、書き込み動作させる場合、外
部Vcc電源(2)の方が電池電源−より電圧が高いた
め、内部Vca電源(8)は外部Vcc電源+21に切
り替わる。次にデータ保持させる場合は外部Vcc電源
12)に電圧が与えられないため、電池電圧aφの方が
、内部Vac電源(8)に切り替わる・
〔発明が解決しようとする課題〕
従来のICカードは以上のように構成されているので、
SRAMが高速アクセスできるものであれば、スタンド
バイ時の電流が多く流れ。Next, the operation will be explained. Conventional IC cards...compare the voltage of the external Vcc power supply (2) and the voltage of the battery power supply QFA by the power supply switching circuit (41), and supply the high voltage power to the inside of the IO card 111 as the internal Vcc power supply (81). i.e. typically 8 RAM
When performing a read operation or a write operation at +91, the external Vcc power supply (2) has a higher voltage than the battery power supply -, so the internal Vca power supply (8) is switched to the external Vcc power supply +21. Next, when data is to be retained, no voltage is applied to the external Vcc power supply 12), so the battery voltage aφ is switched to the internal Vac power supply (8). [Problem to be solved by the invention] Conventional IC cards Since it is configured as above,
If the SRAM can be accessed at high speed, a lot of current will flow during standby.
スタンドバイ時の電流が小さいものであれば、アクセス
タイムが遅く、両方を兼ねそなえているSRAMがない
ため、以上のような問題点があった。If the current during standby is small, the access time is slow, and there are no SRAMs that have both functions, resulting in the above-mentioned problems.
この発明は上記のよう々問題点を解消するためになされ
たもので、高速でアクセスでき、しかも、データ保持寿
命が長いICカードを得ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide an IC card that can be accessed at high speed and has a long data retention life.
この発明に係るICカードは、高速アクセスSRAMと
、スタンドバイ時の電流が大変小さいSRAMの両方を
搭載したものである。The IC card according to the present invention is equipped with both a high-speed access SRAM and an SRAM that consumes very little current during standby.
この発明におけるICカード#−t%読み出し、書き込
み時は高速アクセスSRAMを使用し、データ保持の時
は、データをスタンドバイ電流の小さいSRAMKゴビ
ーして、そのSRAMのみを電池でバックアップさせ、
長寿命のデータ保持を可能にさせる。The IC card #-t% in this invention uses a high-speed access SRAM when reading and writing, and when storing data, the data is transferred to an SRAMK with a small standby current, and only that SRAM is backed up by a battery.
Enables long-life data retention.
以下、この発明の一実施例を図について説明する。第1
図においてIII〜Q@は第8図の従来例に示したもの
と同等であるので説明を省略する。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, III to Q@ are the same as those shown in the conventional example of FIG. 8, so their explanation will be omitted.
Q・は高速アクセス日RAM%IIηはコピー信号線、
+I11は最上位アドレス、翰はコピーモード時のO
K信号線、翰はτ1デコード回路、圓はwgデコード回
路、’12.B、u、@、はトライステートバッファ、
Cはコピーモード切り替えスイッチ群、翰はDIコント
ロールバッファ、凶はアドレスバッファ、鴫はOK2信
号線、0′DはC]!il信号線、@はWK2信号線、
(至)はWlx信号線、(至)は内部アドレスバス、(
至)は内部OE信号線である。Q is the high-speed access day RAM%IIη is the copy signal line,
+I11 is the highest address, 翺 is O in copy mode
K signal line, the wire is the τ1 decoding circuit, the circle is the wg decoding circuit, '12. B, u, @ is a tri-state buffer,
C is the copy mode switch group, the wire is the DI control buffer, the arrow is the address buffer, the black is the OK2 signal line, and 0'D is C]! il signal line, @ is WK2 signal line,
(to) is the Wlx signal line, (to) is the internal address bus, (
) is the internal OE signal line.
次にICカードは)の動作及び使用方法について説明す
る。まず最初に外部Vcc電源(!lに電圧を与える。Next, the operation and usage of the IC card will be explained. First, apply voltage to the external Vcc power supply (!l).
アドレスバスtlO)を設定し最上位アドレス賭を“L
” に設定し、08信号線[12+を” II ”。address bus tlO) and set the highest address bet to “L”.
” and set the 08 signal line [12+ to “II”.
WX信号線(11t−”L#K、ニア ヒーf1号線Q
nk”r、rnにする・するとトライステートバッファ
2iB、23゜−はすべてHlh−Zの状態となり代り
にトライステートバッファー、(至)がバッファとして
働く。WX signal line (11t-”L#K, near hee f1 line Q
When nk''r, rn are set, the tristate buffers 2iB and 23°- are all in the Hlh-Z state, and the tristate buffer (to) works as a buffer instead.
そのためOXデコード@路頭によってchl信号41(
2)を“H,” QWm信号線−が“L〃となる。Therefore, chl signal 41 (
2) becomes “H” and the QWm signal line becomes “L”.
また、Wxデコード回路圓によってWllil信号線@
i−H” Wllia信号線(至)が“L〃となり高速
アクセスSRAM111が書き込み状態になる。この時
データをデータバスa4に設定すると高速の書き込みが
できる。In addition, the Wllil signal line @
The i-H”Wllia signal line (to) becomes “L” and the high-speed access SRAM 111 enters the write state. At this time, if data is set on data bus a4, high-speed writing is possible.
次に読み出し時は同じく、アドレスバスuo+ 1設定
し、最上位アドレスバスをL#に設定、aS信号線Q2
)を“L 〃、 W llt信号線0濁を“■”、DI
信信号線時を“L#にし、コピー信号線07)t−”L
”にする。するとOKデコード回回路例よって、上記と
同じように高速アクセスS RA M IIが選択され
、データバスIにデータが現われ、高速の読み出しがで
きる。Next, when reading, the address bus uo+ is set to 1, the highest address bus is set to L#, and the aS signal line Q2 is set.
) to "L", Wllt signal line 0 to "■", DI
Set the signal signal line to "L#" and copy signal line 07)t-"L
Then, the OK decoding circuit example selects high-speed access S RAM II in the same way as above, and data appears on data bus I, allowing high-speed reading.
この時、外[5V c c電源1りは電池電源(l@よ
りも電圧が高いため、内部Vcc電源(8)は電源切り
替え回路(4)によって外部Vcc電源(2)となって
いるため、電池illから電流が流れることはない。次
にデータの保持方法について説明する。まず高速7り一
!7.SRAMQ11のデータを低スタンドバイ電流の
SRA M +91にコピーする。コピー信号線[17
)をII HPI、最上位アドレスα槌を“I、 ”
、 CB信号線Oat“L ’l 、 W It!信号
線Daft ” H〃、 OK信号線συを“L〃にす
るとトライステートバッファ翰、[有]、+219と、
WEデコード回路2υと、コピーモード切り替えスイッ
チ群nによって高速アクセスSRAMQ61が読み出し
状態、低スタンドバイ電流のS RA M +91が書
き込み状態となりアドレスをインクリメントしてやると
データがデータバスa4に現われて、低スタンドバイ電
流のEIRAM(91に書き込まれる。すべてのデータ
を書き込んで、外部vcct源(21を切断すると電源
切り替え回路14+によって内部Vaa電源電源切り替
わり、低スタンドバイ電流のSRAM+91のデータを
保持することが可能となる。この時、電池(6)は低ス
タンドバイを流のS RA M +91のみをバックア
ップするので、電池の長寿命化が可能となる。At this time, since the external [5V cc power supply 1] has a higher voltage than the battery power supply (l@), the internal Vcc power supply (8) has become the external Vcc power supply (2) by the power supply switching circuit (4), No current flows from the battery ill.Next, we will explain how to hold data.First, copy the data in the high-speed 7RI1!7.SRAMQ11 to the low standby current SRAM+91.Copy signal line [17
) to II HPI, the highest address α is “I,”
, CB signal line Oat "L'l, W It! signal line Daft" H〃, When OK signal line συ is set to "L", tri-state buffer wire, [Yes], +219,
The WE decode circuit 2υ and the copy mode switch group n put the high-speed access SRAM Q61 in the read state and the low standby current SRAM+91 in the write state.When the address is incremented, data appears on the data bus a4 and the low standby current is set. The current is written to the EIRAM (91). When all data is written and the external vcct source (21 is disconnected, the internal Vaa power supply is switched by the power supply switching circuit 14+, making it possible to hold the data in the SRAM+91 with a low standby current. At this time, the battery (6) backs up only S RAM +91 in low standby mode, making it possible to extend the life of the battery.
次に再び、読み出し動作する時は、外部■cc電源12
1に電圧を与え、コピー信号線T:17)を“H”+最
上位アドレス帖を“H’) 、 CEl信号線α匂を”
L、WZ信号線圓を“H#に設定するとトライステート
バッファd 、 Zl 、 @ トコビーモード切替え
スイッチ群−によって低スタンドバイ電流(D 8 R
A M (91が読み出し状態、高速アクセスSRA
M 18が書き込み状態となり、アドレスインクリメン
トするとS、RAM+91のデータがすべて高速アクセ
スSRAMQ・に書き込まれることになる。このように
して後は通常の読み出し・書き込みを行えば、高速アク
セスs RA M 11を使用しているため、高速でア
クセスすることができる。Next, when performing the read operation again, use the external CC power supply 12.
Apply voltage to 1, copy signal line T: 17) to “H” + top address line to “H’), CEL signal line α”
When the L and WZ signal lines are set to "H#," a low standby current (D 8 R
A M (91 is read state, high speed access SRA
When M18 enters the write state and the address is incremented, all data in S and RAM+91 will be written to the high-speed access SRAMQ. If normal reading and writing are performed in this manner, high-speed access can be achieved since the high-speed access RAM 11 is used.
なお上記実施例では、データを保持するために低スタン
ドバイ電流の8 RA M +91を用いた場合につい
て説明したが、高速アクセスBRAMαeとタイミング
を除いて同じように読み出し。In the above embodiment, a case has been described in which 8 RAM +91 with a low standby current is used to hold data, but reading is performed in the same manner as the high-speed access BRAM αe except for the timing.
書き込みができるROMであってもよい。その際には電
源切り替え回路(41及び電池(61などは不要である
。It may also be a writable ROM. In this case, the power supply switching circuit (41), battery (61, etc.) are not required.
以上のようにこの発明によれば、ICカード内に高速ア
クセスSRAMと低スタンドバイ電流のSRAMを設け
、使い分けるようにしたので、高速アクセスができ、し
かもデータのバックアップ時の電流が非常に小さい工0
カードが得られる効果がるる。As described above, according to the present invention, a high-speed access SRAM and a low standby current SRAM are provided in an IC card and used separately, so that high-speed access is possible and the current consumption during data backup is extremely small. 0
The effect that the card can obtain increases.
第1図はこの発明の一実施例によるICカードの回路を
示すブロック図、第8図は従来のICカードの回路を示
すブロック図である。
図において田はICカード%12)は外部vCC電源、
)31は()NDt源、(4)は電源切り替え回路、(
5)は電池、(6)は抵抗、(7)はダイオード%(8
)は内部Vcc電源、(9)はSRAM、(10)はア
ドレスバス、αυはOXg号m、 +121 、 (l
lfl CK(W号線、(+31dwm信号線、041
ij r l ハX、Q51 ハiI & 電源。
(I四は高速アクセスSRAM%aηはコピー信号線、
α樽は最上位アドレスバス、四はORデコード回路%ば
はWXXココ−回路、−〜(至)はトライステートバッ
ファ、nはコピーモード切り替えスイッチ群、圀はOE
コントロールバッファ、四はアドレスバッファ、働は0
12信号線、(ロ)はOKI信号線、@はWl、2信号
線、(至)はWE1信号線、(至)は内部アドレスバス
、(7)は内部OE信号線である。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a block diagram showing a circuit of an IC card according to an embodiment of the present invention, and FIG. 8 is a block diagram showing a circuit of a conventional IC card. In the figure, field is IC card %12) is external vCC power supply,
)31 is ()NDt source, (4) is power supply switching circuit, (
5) is the battery, (6) is the resistor, (7) is the diode% (8
) is the internal Vcc power supply, (9) is the SRAM, (10) is the address bus, αυ is OXg, +121, (l
lfl CK (Line W, (+31dwm signal line, 041
ij r l HaX, Q51 High iI & Power. (I4 is a high-speed access SRAM%aη is a copy signal line,
α barrel is the highest address bus, 4 is the OR decoding circuit, % is the WXX circuit, -~ (to) is the tri-state buffer, n is the copy mode switch group, and the area is OE
Control buffer, 4 is address buffer, function is 0
12 signal lines, (b) is the OKI signal line, @ is the Wl, 2 signal line, (to) is the WE1 signal line, (to) is the internal address bus, and (7) is the internal OE signal line. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
読み出し、書き込みが可能なメモリとスタンドバイ状態
での電流が大変小さいSRAMの両方を有し、動作時は
高速で読み出し、書き込みが可能なメモリを使用し、デ
ータのバツクアツプ時には、スタンドバイ電流が小さい
SRAMを使用することによつて、高速で読み出し書き
込みができ、しかも、スタンドバイ電流が小さいことを
特徴とするICカード。For IC cards equipped with semiconductor memory elements, use memory that can be read and written at high speed and has both memory that can be read and written at high speed and SRAM that has a very low current in standby state, and that can be read and written at high speed during operation. However, when backing up data, an IC card is characterized in that by using an SRAM with a small standby current, it is possible to read and write at high speed, and the standby current is small.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2191642A JPH0475191A (en) | 1990-07-17 | 1990-07-17 | Ic card |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2191642A JPH0475191A (en) | 1990-07-17 | 1990-07-17 | Ic card |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0475191A true JPH0475191A (en) | 1992-03-10 |
Family
ID=16278052
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2191642A Pending JPH0475191A (en) | 1990-07-17 | 1990-07-17 | Ic card |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0475191A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6325294B2 (en) | 1992-06-17 | 2001-12-04 | Micron Technology, Inc. | Method of manufacturing an enclosed transceiver |
US7948382B2 (en) | 1997-08-20 | 2011-05-24 | Round Rock Research, Llc | Electronic communication devices, methods of forming electrical communication devices, and communications methods |
US8018340B2 (en) | 1992-08-12 | 2011-09-13 | Round Rock Research, Llc | System and method to track articles at a point of origin and at a point of destination using RFID |
-
1990
- 1990-07-17 JP JP2191642A patent/JPH0475191A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6325294B2 (en) | 1992-06-17 | 2001-12-04 | Micron Technology, Inc. | Method of manufacturing an enclosed transceiver |
US8018340B2 (en) | 1992-08-12 | 2011-09-13 | Round Rock Research, Llc | System and method to track articles at a point of origin and at a point of destination using RFID |
US7948382B2 (en) | 1997-08-20 | 2011-05-24 | Round Rock Research, Llc | Electronic communication devices, methods of forming electrical communication devices, and communications methods |
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