JPH0473956A - Carrier for semiconductor device - Google Patents

Carrier for semiconductor device

Info

Publication number
JPH0473956A
JPH0473956A JP2187663A JP18766390A JPH0473956A JP H0473956 A JPH0473956 A JP H0473956A JP 2187663 A JP2187663 A JP 2187663A JP 18766390 A JP18766390 A JP 18766390A JP H0473956 A JPH0473956 A JP H0473956A
Authority
JP
Japan
Prior art keywords
substrate
ribbon frame
wiring
carrier
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2187663A
Other languages
Japanese (ja)
Inventor
Yasunobu Oshima
大島　康伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Electric Kagoshima Ltd
NEC Kagoshima Ltd
Original Assignee
Nippon Electric Kagoshima Ltd
NEC Kagoshima Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Kagoshima Ltd, NEC Kagoshima Ltd filed Critical Nippon Electric Kagoshima Ltd
Priority to JP2187663A priority Critical patent/JPH0473956A/en
Publication of JPH0473956A publication Critical patent/JPH0473956A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/023—Mount members, e.g. sub-mount members
    • H01S5/02325—Mechanically integrated components on mount members or optical micro-benches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/02345—Wire-bonding

Abstract

PURPOSE:To facilitate the automation of assembly and screening lines by providing a semiconductor carrier, which includes a high-thermal-conductivity and high-electrical resistivity substrate having metal films on both surfaces, interconnections on the upper surface, V-grooves for separation in the lower surface, and a ribbon frame having leads brazed to the interconnections on the substrate. CONSTITUTION:A carrier for a semiconductor device includes a high-resistance substrate 1 of good thermal conductor having upper and lower surfaces coated with metallic film 2. The upper surface has wiring and the lower surface has a V-groove 3 for cutting. The wiring of the substrate is brazed to leads 5 and 5' of a ribbon frame 4. For example, the substrate is made of such a material as high-resistance silicon, BN, and BC, and it is coated with the metallic film for brazing. The wiring of the substrate is bonded with high-temperature brazing metal 6 to the leads 5 and 5' of the ribbon frame, and then the lead 5' is removed from the ribbon frame. A semiconductor laser chip 7 is mounted, and a bonding wire 8 is connected to the chip. Such a chip on the ribbon frame undergoes screening.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体素子用のキャリアに関し、特に光通信
もしくはビーム応用に使われる半導体レーザ用の汎用リ
ボンフレーム付サブキャリアに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to carriers for semiconductor devices, and more particularly to a general-purpose ribbon-framed subcarrier for semiconductor lasers used in optical communications or beam applications.

〔従来の技術〕[Conventional technology]

従来、この種のキャリアは、第４図（ａ）（ｂ）、（ｃ
）に示すように、まず半導体レーザチップ１１を矩形の
熱伝導性の良い材質のヒートシンク１２にロー付の後、
金属リード１３が付いたより大きな金属性のブロック１
４に組み込む構造をしていた。このキャリアの状態で選
別スクリーニングを行なうため、別途選別用の補助治具
への取り付は用のネジ穴１５がキャリアに付けられてい
るのが特徴であった。Conventionally, this type of carrier has been used as shown in Figs.
), first, the semiconductor laser chip 11 is brazed to a rectangular heat sink 12 made of a material with good thermal conductivity, and then
Larger metal block 1 with metal leads 13
It was structured to be incorporated into 4. In order to carry out sorting screening in this carrier state, the carrier is characterized by having screw holes 15 for attachment to a separate auxiliary jig for sorting.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この種のキャリアケースは、目的・用途に応じて種々の
形状をしており、その形状に合わせて選別用の補助治具
はすべて準備せねばならず、組込み用の補助治具に付い
ても同じであった。このことは、半導体レーザの用途が
ふえ、ケースの種類がふえるにつれて構造ラインの構成
を混乱させるばかりでなく、自動化設備の導入を阻害す
る要因ともなって来た。又、補助治具へのセット、リセ
ットの工数、その時の半導体レーザチップへ作業ミスに
より加える損傷等、コスト阻害要因も大きな問題であっ
た。This type of carrier case has various shapes depending on the purpose and use, and all auxiliary jigs for sorting must be prepared according to the shape. It was the same. As the applications of semiconductor lasers have increased and the types of cases have increased, this has not only caused confusion in the structure line configuration, but has also become a factor that inhibits the introduction of automated equipment. In addition, cost-inhibiting factors such as the number of man-hours required for setting on an auxiliary jig and resetting, and damage caused to the semiconductor laser chip due to operational errors were also major problems.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、熱伝導性の良い高抵抗の基板の上下面に金属
膜を付け、上面に所定の配線加工を行ない、裏面に分割
用のＶ溝を付けた後、リボンフレームの所定のリードに
この基板の配線部をロー付した構成を有している。In the present invention, metal films are attached to the upper and lower surfaces of a high-resistance substrate with good thermal conductivity, a predetermined wiring process is performed on the top surface, and a V-groove for division is provided on the back surface, and then the predetermined leads of the ribbon frame are connected to the metal films. The wiring portion of this board is brazed.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第１図
（ａ）、（ｂ）、（ｃ）は、それぞれ本発明の第１の実
施例の平面図、Ａ−Ａ’断面図および正面図である。ま
ず、熱伝導性の良い高抵抗基板１を準備する。これは、
半導体レーザ用のヒートシンクをかねることを目的とす
るため、レーザ素材と膨張係数を出来るだけ合わせる必
要があり、高抵抗シリコン、ＢＮ、ＢＣ等が使われる。Next, the present invention will be explained with reference to the drawings. FIGS. 1(a), (b), and (c) are a plan view, an AA' sectional view, and a front view, respectively, of a first embodiment of the present invention. First, a high resistance substrate 1 with good thermal conductivity is prepared. this is,
Since the purpose is to serve as a heat sink for a semiconductor laser, it is necessary to match the expansion coefficient with the laser material as much as possible, and high-resistance silicon, BN, BC, etc. are used.

この基板１の上下面にロー付を目的とした金属膜２をも
うけ、上面金属膜には配線加工を行なう、そして裏面に
は分割用のＶ？１１３を付ける。ここまでは、通常大き
な基板状態で加工した後、個別に切断して多数を一度に
準備する。この後リボンフレーム４のリード部５と基板
の配線部を銀ロー等の高温ロー材６でロー付し、一部の
リード部５′はリボンフレームから切離す。A metal film 2 for the purpose of brazing is formed on the upper and lower surfaces of this substrate 1, wiring is processed on the upper metal film, and a V for dividing is formed on the back surface. Add 113. Up to this point, usually a large substrate is processed and then cut individually to prepare a large number of substrates at once. Thereafter, the lead portions 5 of the ribbon frame 4 and the wiring portions of the board are brazed with a high-temperature brazing material 6 such as silver solder, and some of the lead portions 5' are separated from the ribbon frame.

この状態で第２図に示すリボンフレーム付汎用サブキャ
リアができあがる０次に第１図に示すように半導体レー
ザチップ７をマウントしボンディングワイヤー８を付け
る。In this state, a general-purpose subcarrier with a ribbon frame as shown in FIG. 2 is completed.The semiconductor laser chip 7 is mounted on the zeroth order as shown in FIG. 1, and bonding wires 8 are attached.

この組み込みおよびその後の選別スクリーニングは、リ
ボンフレーム状態のため従来のような補助治具がいらず
、容易に自動化が可能となる。選別スクリーニングの後
、良品汎用キャリア、所定の特性区分の汎用キャリアを
種々の用途に合わせ、所定のキャリアや回路基板にリボ
ンフレームからＶ溝部で切離した後組み込む。This incorporation and subsequent screening can be easily automated because the ribbon frame does not require any auxiliary jigs as in the past. After selection screening, non-defective general-purpose carriers and general-purpose carriers with predetermined characteristic classifications are assembled into predetermined carriers or circuit boards after being cut from the ribbon frame at the V-groove portion according to various uses.

第３図（ａ）、（ｂ）は、それぞれ本発明の第２の実施
例の平面図およびＢ−Ｂ’断面図である。基本構成は、
第１図と同じであるが、基板の分離用の■溝部がリボン
リード５′を２本付けて分離できるようもうけられ、又
、その２本のリードが平行して出ている所に特徴がある
。この構成は、特に高速応答用のキャリアとして、有利
である。FIGS. 3(a) and 3(b) are a plan view and a BB' sectional view of the second embodiment of the present invention, respectively. The basic configuration is
It is the same as Fig. 1, but the groove part for separating the board is provided so that two ribbon leads 5' can be attached and separated, and the two leads come out in parallel. be. This configuration is particularly advantageous as a carrier for high-speed response.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明はキャリアをリボンフレー
ム化することにより、組立・選別ライン設備の自動化を
容易にし、選別スクリーニングの後、リボンフレームか
らＶ渭により小キャリアを分離することにより、種々の
用途に合わせたキャリアケース及び回路基板に組み込む
ことのできる汎用性を有している。As explained above, the present invention facilitates the automation of assembly and sorting line equipment by forming carriers into ribbon frames, and by separating small carriers from the ribbon frame with a V-way after sorting and screening, various types of It has the versatility of being able to be incorporated into carrier cases and circuit boards tailored to the application.

る。Ru.

１・・・高抵抗基板、２・・・金属膜、３・・・分割用
Ｖ溝、４・・・リボンフレーム、５，５′・・・リード
、６・・・ロー材、７・・・半導体レーザチップ、８・
・・ボンディングワイヤー、１１・・・半導体レーザチ
ップ、１２・・・ヒートシンク、１３・・・金属リード
、１４・・・金属ブロック、１５・・・取付用ネジ穴。DESCRIPTION OF SYMBOLS 1... High resistance board, 2... Metal film, 3... V-groove for division, 4... Ribbon frame, 5, 5'... Lead, 6... Brazing material, 7...・Semiconductor laser chip, 8・
...Bonding wire, 11...Semiconductor laser chip, 12...Heat sink, 13...Metal lead, 14...Metal block, 15...Screw hole for mounting.

Claims (1)

【特許請求の範囲】[Claims] 　熱伝導性の良い高抵抗の基板の上下面に金属膜を付け
、上面に所定の配線加工を行ない、裏面に分割用のＶ溝
を付けた後、リボンフレームの所定のリードに該基板の
配線部をロー付したことを特徴とする半導体素子用キャ
リア。After attaching metal films to the top and bottom surfaces of a high-resistance substrate with good thermal conductivity, and performing the specified wiring processing on the top surface and forming a V-groove for division on the back surface, connect the wiring of the substrate to the specified leads of the ribbon frame. A carrier for semiconductor elements characterized by having a brazed portion.
JP2187663A 1990-07-16 1990-07-16 Carrier for semiconductor device Pending JPH0473956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2187663A JPH0473956A (en) 1990-07-16 1990-07-16 Carrier for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2187663A JPH0473956A (en) 1990-07-16 1990-07-16 Carrier for semiconductor device

Publications (1)

Publication Number Publication Date
JPH0473956A true JPH0473956A (en) 1992-03-09

Family

ID=16210002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2187663A Pending JPH0473956A (en) 1990-07-16 1990-07-16 Carrier for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0473956A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012514860A (en) * 2009-01-09 2012-06-28 シーアン フォーカスライト テクノロジーズ カンパニー リミッテッド High power semiconductor laser and manufacturing method thereof
JP2020533797A (en) * 2017-09-12 2020-11-19 ロジャーズ ジャーマニー ゲーエムベーハーＲｏｇｅｒｓ Ｇｅｒｍａｎｙ ＧｍｂＨ Adapter elements for joining components such as laser diodes to heat sinks, systems including laser diodes, heat sinks and adapter elements, and methods of manufacturing adapter elements.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012514860A (en) * 2009-01-09 2012-06-28 シーアン フォーカスライト テクノロジーズ カンパニー リミッテッド High power semiconductor laser and manufacturing method thereof
JP2020533797A (en) * 2017-09-12 2020-11-19 ロジャーズ ジャーマニー ゲーエムベーハーＲｏｇｅｒｓ Ｇｅｒｍａｎｙ ＧｍｂＨ Adapter elements for joining components such as laser diodes to heat sinks, systems including laser diodes, heat sinks and adapter elements, and methods of manufacturing adapter elements.

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