JPH0469950A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0469950A JPH0469950A JP18237790A JP18237790A JPH0469950A JP H0469950 A JPH0469950 A JP H0469950A JP 18237790 A JP18237790 A JP 18237790A JP 18237790 A JP18237790 A JP 18237790A JP H0469950 A JPH0469950 A JP H0469950A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- capacitance
- layers
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 4
- 239000012212 insulator Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に多層配線を有するゲー
トアレイ半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a gate array semiconductor device having multilayer wiring.
従来この種のゲートアレイ半導体装置は、３層信号配線
を有する場合第３図に示すように、トランジスタ等の素
子が形成されている基板３０５上に、それぞれ絶縁体３
０６で電気的に分離された第１層配線３０１、第２層配
線３０２および第３層配＠ ３０３を有し、かつ各層間
を電気的に接続するスルーホール３０４を有している。Conventionally, when this type of gate array semiconductor device has three-layer signal wiring, as shown in FIG.
It has a first layer wiring 301, a second layer wiring 302, and a third layer wiring 303 that are electrically separated by a wire 06, and has a through hole 304 that electrically connects each layer.
第３図に示すような配線構造を用いてロジックＬＳＩを
構成する場合、配線に寄生する容量は、第２層配線を例
にとると、■第２層配線−基板間の容Ｊｉ３１１ 、■
第２層配線間の容量３１０、■第２層配線−第３層配線
間の容量３１２の３つがあり、加えてこの寄生容量は第
２層配線の上下層にパターンがある場合と熱い場合、上
下層の電位の状態等によって変化するため、レイアウト
パターンからの正確な容量の見積りが非常に髭しい。特
に、ランダムロジックＬＳＩの場合、配線パターンの組
合せがランダムになるので精度の良い遅延値の設計をす
るには膨大な計算量が必要となる。また、図中、３０７
は第１層配線−基板間の容量、３０８は第１Ｎ配線間の
容量、３０９は第１層配線−第２層配線間の容量、３１
３は第３層配線間の容量、３１４は第３層配線−第１層
配Ｒ間の容量、３１５は第３層配線−基板間の容量であ
る。When configuring a logic LSI using the wiring structure shown in FIG. 3, the capacitance parasitic to the wiring is, taking the second layer wiring as an example, ■ the capacitance between the second layer wiring and the board Ji311,
There are three types of capacitance: capacitance 310 between the second layer wiring, and capacitance 312 between the second layer wiring and the third layer wiring. Since it changes depending on the potential state of the upper and lower layers, it is extremely difficult to accurately estimate the capacitance from the layout pattern. In particular, in the case of a random logic LSI, since the combinations of wiring patterns are random, a huge amount of calculation is required to design accurate delay values. Also, in the figure, 307
is the capacitance between the first layer wiring and the board, 308 is the capacitance between the 1Nth wiring, 309 is the capacitance between the first layer wiring and the second layer wiring, 31
3 is the capacitance between the third layer wiring, 314 is the capacitance between the third layer wiring and the first layer wiring R, and 315 is the capacitance between the third layer wiring and the substrate.
この従来の半導体装置は、配線層間が電気的にシールド
されていないため、信号配線の寄生容量を算出する場合
には上下層の配線のレイアウトパターンを考慮し、かつ
上下層の配線の電位状態をも考慮しなければならず、膨
大な計算量が必要となる。特に、ゲートアレイのような
ランダムロジックしＳ■の場合には、配線パターンの組
合せは特定できないので、眉間容量を正確に見積ること
は事実上不可能であった。In this conventional semiconductor device, the wiring layers are not electrically shielded, so when calculating the parasitic capacitance of the signal wiring, the layout pattern of the wiring in the upper and lower layers must be considered, and the potential state of the wiring in the upper and lower layers must be considered. must also be taken into account, which requires a huge amount of calculation. In particular, in the case of a random logic system such as a gate array, it is virtually impossible to accurately estimate the glabella capacitance because the combination of wiring patterns cannot be specified.
本発明の目的は配線容量の正確な見積りを可能にした半
導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that allows accurate estimation of wiring capacitance.
前記目的を達成するため、本発明に係る半導体装置にお
いては、ｍ層（ｍ≧２、ｍは整数）の配線層を有する半
導体装置であって、半導体基板ｍ１から第ｎ番目（１≦
ｎ≦ｍ−１．ｎは整数）の配線層と第ｎ＋１番目の配線
層との間に、一定電位が与えられる導電体層を有するも
のである。In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having m wiring layers (m≧2, m is an integer), and has an nth (1≦1) wiring layer from a semiconductor substrate m1.
n≦m−1. A conductor layer to which a constant potential is applied is provided between the wiring layer (n is an integer) and the (n+1)th wiring layer.
ｍ層の配線層のうち下からｎ番目の配線層とｎ＋１番目
の配線層の間に（２≦ｎ≦ｍ−１．ｎは整数）、一定電
位を与えられた導電層を有し、配線層間の電気的影響を
シールドする。Between the n-th wiring layer and the n+1-th wiring layer from the bottom among the m wiring layers (2≦n≦m-1, n is an integer), there is a conductive layer given a constant potential, and the wiring Shielding electrical influences between layers.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
（実施例１）
第１図は本発明を３層配線を有する半導体チップに適用
した実施例１を示す断面図である。(Example 1) FIG. 1 is a sectional view showing Example 1 in which the present invention is applied to a semiconductor chip having three-layer wiring.
図において、トランジスタ素子等が形成されている基板
１０５上に、基板側から第１層配線１０１、接地された
シールドＮ１１０７、第２層配線１０２、接地されたシ
ールド層１０７、第３層配線１０３の順に形成され、各
層間は絶縁体１０６で電気的に分離され、必要に応じて
１−２層スルーホール１０４等で電気的に接続されてい
る。In the figure, a first layer wiring 101, a grounded shield N1107, a second layer wiring 102, a grounded shield layer 107, and a third layer wiring 103 are placed on a substrate 105 on which transistor elements and the like are formed. The layers are formed in sequence, and each layer is electrically isolated by an insulator 106, and electrically connected by a 1-2 layer through hole 104 or the like as necessary.
本実施例において、第２層配線１０２の寄生容量を例に
とると、第２層配線−シールド層間の容量１１１ 、１
１３は、上下層の配線パターンおよび電位状態に拘らず
一定であり、第１層配線１０１０２の面積に比例した値
となるため、第２層配線間の容量１１２と合わせて、第
２層配線１０２だけのレイアウトパターンから配線容量
の算出が可能となる。In this embodiment, taking the parasitic capacitance of the second layer wiring 102 as an example, the capacitance between the second layer wiring and the shield layer 111, 1
13 is constant regardless of the wiring pattern and potential state of the upper and lower layers, and has a value proportional to the area of the first layer wiring 10102. Therefore, together with the capacitance 112 between the second layer wiring, the second layer wiring 102 It becomes possible to calculate the wiring capacitance from the layout pattern.
第２層配線１０２が最小線幅、最小ピッチで並列してい
る場合を考える。実用レベルで第２Ｎ！配線の最小線幅
１．８μｍ、ｆｉ小間隔１，２μｍ、厚さ０．８μｍ、
第２層配線−シールド層間隔０，４μｍで、絶縁体の誘
電率が均一とすると、単位長さ当り第２層配線−シール
ド層間容量１１１ 、１１３の方が第２層配線間容量１
１２よりも
［（１，８１０，８） ｘ （１，２１０，４） ］
ｘ ２ｇ１３倍大きいので、実用上は第２層配線間容量
１１２を無視して（単位長さ当りの第２層配線−シール
ド層間容量）×配線長で配線容量を見積ることができる
。このことは、第１層配線−基板間の容量１０８、第１
層配線間の容量１０９、第１層配線−シールド層間の容
量１１０、第３層配線−シールド層間の容量、第３層配
線間の容量１１５についても同様である。Consider a case where the second layer wirings 102 are arranged in parallel with the minimum line width and minimum pitch. 2nd N in practical level! Minimum wiring width 1.8 μm, fi small spacing 1.2 μm, thickness 0.8 μm,
Assuming that the distance between the second layer wiring and the shield layer is 0.4 μm and the dielectric constant of the insulator is uniform, the capacitance between the second layer wiring and the shield layer per unit length is 111 and 113, whereas the capacitance between the second layer wiring and the shield layer is 1
than 12 [(1,810,8) x (1,210,4) ]
x2g13 times as large, so in practice, the wiring capacitance can be estimated by (capacitance between the second layer wiring and the shield layer per unit length) x wiring length, ignoring the capacitance 112 between the second layer wiring. This means that the capacitance 108 between the first layer wiring and the board,
The same applies to the capacitance 109 between layer wirings, the capacitance 110 between the first layer wiring and the shield layer, the capacitance between the third layer wiring and the shield layer, and the capacitance 115 between the third layer wiring.
（実施例２）
第２図は本発明を４層配線を有する半導体チップに適用
した実施例２を示す断面図である。(Example 2) FIG. 2 is a sectional view showing Example 2 in which the present invention is applied to a semiconductor chip having four-layer wiring.
図において、トランジスタ素子等が形成されている基板
２０６上に、基板側から第１層配線２０１、接地された
シールド層２０８、第２層配線２０２、接地されたシー
ルド層２０８、第３層配線２０３、接地されたシールド
層２０８、第４層配ｋｊ！、２０４の順に形成され、各
層間は絶縁体２０７で電気的に分離され、必要に応じて
１−２層スルーホール２０５等で電気的に接続されてい
る。また、図中、２０９は第１層配線−基板間の容量、
２１０は第１層配線間の容量、２１１は第１層配線−シ
ールド層間の容量、２１５．２１７は第３層配線−シー
ルド層間の容量、２１６は第３層配線間の容量、２１８
は第４層配線−シールド層間の容量、２１９は第４層配
線間の容量である。In the figure, on a substrate 206 on which transistor elements etc. are formed, from the substrate side, first layer wiring 201, grounded shield layer 208, second layer wiring 202, grounded shield layer 208, third layer wiring 203 , grounded shield layer 208, fourth layer distribution kj! , 204 are formed in this order, and each layer is electrically isolated by an insulator 207 and electrically connected by a 1-2 layer through hole 205 or the like as necessary. In addition, in the figure, 209 is the capacitance between the first layer wiring and the board;
210 is the capacitance between the first layer wiring, 211 is the capacitance between the first layer wiring and the shield layer, 215.217 is the capacitance between the third layer wiring and the shield layer, 216 is the capacitance between the third layer wiring, 218
is the capacitance between the fourth layer wiring and the shield layer, and 219 is the capacitance between the fourth layer wiring.
本実施例において、第２層配線の容量算出には、第２層
配線−シールド層間の容量２１２，２１４と第２層配線
間の容量２１３を考慮すれば良く、第２層配線と基板間
、第１層配線間、第３層配線間、第４層配線間の容量お
よび電位の影響は考慮する必要がない。In this embodiment, to calculate the capacitance of the second layer wiring, it is sufficient to consider the capacitances 212 and 214 between the second layer wiring and the shield layer, and the capacitance 213 between the second layer wiring, and the capacitance 213 between the second layer wiring and the board. There is no need to consider the effects of capacitance and potential between the first layer interconnects, between the third layer interconnects, and between the fourth layer interconnects.
このことはその層配線の容量算出についても同揉゛ζあ
る。This also applies to the calculation of the capacitance of the wiring layer.
（発明グ）効果］
以■−説明［５、／、・よ）に本発明は、配線層間の電
；気的な影響をＳ・−ルドし”ζいるので、配線容置の
１１確な見積りが−ｉｉ＋能になるという効果、をイ」
する。(Effects of the Invention) Hereinafter, the present invention eliminates the electrical influence between wiring layers, so The effect that the estimate becomes -ii + ability is
do.
第１図は本発明の実線例１を示す断面図、第２図は本発
明の実施例２を示″つ断面図２第３図はｔｔ来例を小（
断面図ζ、′ある。
１０１゜２０１ 、３０１・・・第１Ｎ！！配線１０２
、２０２ 、３０２・・・第２層配線１０３ 、２０
３ 、３０３・・・第３層配線２０４・・・第４層配線
１０４ 、２０５ 、３０４・・・１−２層スルーホー
ル１０５ 、２０６ 、３０５・・・１に板１０６ 、
２Ｏ７、３０ｆ３・・・絶縁体１０７ 、２０Ｂ・・・
シールドＭ（接地）１０８ 、２０９ 、３０７・・・
第１層配線−基板間の容置１０９ 、２１０ 、３ＯＳ
・・・第１層配線間の容置１１０ 、２１１・・・第１
層配線−シール１で層間の容量性
１１１．１１３ ２１２ ２１４
・・・・第２層配線−シー・ルド層間の容重１１２ 、
２１３ 、３１０・・・第２Ｍ配線間の容置１１４ 、
２１５ 、２１７
・・・第３７ｔ１１配線−シールド層間の容１１１５
、２１６ 、３１３・・・第″３Ｍ配線間の容置２１８
・・・第４層配線−シールド層間の容重２１９・・・第
４Ｍ配線間の容址
３０９・・・第１層配線−第２層配線間の容置３１１・
・・第２層配線−基板間の容置３１２・・・第２層配線
−第３層配線２０４３１４・・・第３層配線−第１層配
線間の容置３１ｊ１・・・第３層配線−基板間の容置許
出願人 ＩＩ本電気株式会社
゛（三・ひ
ｍ１第３畳・＃？縛
、−”７−−〜−−一−・、−、−、、、、、、、、、
−Ｌ−、、、、、、、、、、、、、、、、、、、−、、
、−／
、２ｒ −
第１６図
第
図Fig. 1 is a sectional view showing a solid line example 1 of the present invention, Fig. 2 is a sectional view showing a second embodiment of the invention.
There are cross-sectional views ζ and ′. 101°201, 301...1st N! ! Wiring 102
, 202 , 302 . . . second layer wiring 103 , 20
3, 303...Third layer wiring 204...Fourth layer wiring 104, 205, 304...1-2 layer through holes 105, 206, 305... 1 on the board 106,
2O7, 30f3... Insulator 107, 20B...
Shield M (ground) 108, 209, 307...
Container 109, 210, 3OS between first layer wiring and board
. . . Receptacles 110 and 211 between the first layer wirings . . .
Capacitance between layers between layer wiring and seal 1 111.113 212 214 . . . Capacitance between second layer wiring and shield layer 112,
213, 310... Reservoir 114 between the second M wirings,
215, 217... Capacity 1115 between the 37th t11 wiring and the shield layer
, 216, 313... Receptacle 218 between the ``3M'' wires
... Capacity between the fourth layer wiring and the shield layer 219 ... Capacity between the fourth M wiring 309 ... Capacity between the first layer wiring and the second layer wiring 311
... Receptacle 312 between second layer wiring and substrate ... Second layer wiring - third layer wiring 204314 ... Receptacle 31j1 between third layer wiring and first layer wiring ... Third layer wiring - Applicant for storage permit between boards: II Hondenki Co., Ltd. ,,
-L-,,,,,,,,,,,,,,,,,-,,,
, -/ , 2r - Figure 16
Claims (1)
体装置であつて、半導体基板側から第ｎ番目（１≦ｎ≦
ｍ−１、ｎは整数）の配線層と第ｎ＋１番目の配線層と
の間に、一定電位が与えられる導電体層を有することを
特徴とする半導体装置。(1) A semiconductor device having m wiring layers (m≧2, m is an integer), the nth layer (1≦n≦) from the semiconductor substrate side.
1. A semiconductor device comprising a conductor layer to which a constant potential is applied between a wiring layer (m-1, n is an integer) and an (n+1)th wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18237790A JPH0469950A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18237790A JPH0469950A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0469950A true JPH0469950A (en) | 1992-03-05 |
Family
ID=16117248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18237790A Pending JPH0469950A (en) | 1990-07-10 | 1990-07-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0469950A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0703617A2 (en) * | 1994-09-22 | 1996-03-27 | Nippon Telegraph And Telephone Corporation | High frequency monolithic integrated circuit |
| WO1999001939A1 (en) * | 1997-07-03 | 1999-01-14 | Seiko Epson Corporation | Ladder type resistance circuit, and digital-analog converter and semiconductor device using the same |
| US6380567B1 (en) | 1998-02-02 | 2002-04-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
-
1990
- 1990-07-10 JP JP18237790A patent/JPH0469950A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0703617A2 (en) * | 1994-09-22 | 1996-03-27 | Nippon Telegraph And Telephone Corporation | High frequency monolithic integrated circuit |
| EP0703617A3 (en) * | 1994-09-22 | 1997-02-26 | Nippon Telegraph & Telephone | High frequency monolithic integrated circuit |
| US5739560A (en) * | 1994-09-22 | 1998-04-14 | Nippon Telegraph And Telephone Corporation | High frequency masterslice monolithic integrated circuit |
| WO1999001939A1 (en) * | 1997-07-03 | 1999-01-14 | Seiko Epson Corporation | Ladder type resistance circuit, and digital-analog converter and semiconductor device using the same |
| US6208281B1 (en) | 1997-07-03 | 2001-03-27 | Seiko Epson Corporation | Resistance ladder together with digital-analog converter and semiconductor using the same |
| US6380567B1 (en) | 1998-02-02 | 2002-04-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
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